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61. 发明授权

US07288954B2 Compliant contact pin test assembly and methods thereof 有权
标题翻译：符合接触针测试组件及其方法
公开(公告)号：US07288954B2
公开(公告)日：2007-10-30
申请号：US11477217
申请日：2006-06-29
申请人： Kyle K. Kirby , Warren M. Farnworth , James M. Wark , William M. Hiatt , David R. Hembree , Alan G. Wood
发明人： Kyle K. Kirby , Warren M. Farnworth , James M. Wark , William M. Hiatt , David R. Hembree , Alan G. Wood
IPC分类号： G01R31/02
CPC分类号： G01R1/0735 , G01R1/07314 , H01L23/13 , H01L23/481 , H01L23/49811 , H01L23/49827 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16235 , H01L2924/00014 , H01L2924/09701 , H01L2924/15311 , H01L2924/3511 , H01R12/714 , H01R13/24 , H01R2201/20 , H05K3/326 , H05K7/1069 , H05K2201/0314 , H05K2201/09036 , H05K2201/10378 , Y10T29/49165 , Y10T29/49174 , Y10T29/49204 , Y10T29/49222 , H01L2224/05599
摘要： A compliant contact pin assembly and a contactor card and methods for testing therewith are provided. The compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a compliant coupling structure. The suspension within the substrate results in a compliant deflection orthogonal to the plane of the substrate. The contact pin assembly is formed by generally thinning the substrate around the contact pin location and then specifically thinning the substrate immediately around the contact pin location for forming a void. The contact pin is compliantly coupled, in one embodiment by compliant coupling material, and in another embodiment by compliantly flexible portions of the substrate.
摘要翻译：提供了一种柔性接触销组件和接触器卡以及用于测试的方法。柔性接触销组件包括由基板的一部分形成的接触销，其中触头销顺从地保持通过柔性联接结构悬挂在基板内。衬底内的悬浮液导致与衬底的平面垂直的柔顺偏转。接触销组件通过使基板围绕接触销位置大体变薄而形成，然后特别地使基板在接触销位置周围特别地变薄以形成空隙。在一个实施例中，接触销被顺从地联接，在一个实施例中通过柔性耦合材料，并且在另一个实施例中，通过柔性柔性部分的衬底。

62. 发明授权

US07224051B2 Semiconductor component having plate and stacked dice 有权
标题翻译：半导体元件具有板和堆叠的骰子
公开(公告)号：US07224051B2
公开(公告)日：2007-05-29
申请号：US11333662
申请日：2006-01-17
申请人： Warren M. Farnworth , Alan G. Wood , William M. Hiatt , James M. Wark , David R. Hembree , Kyle K. Kirby , Pete A. Benson
发明人： Warren M. Farnworth , Alan G. Wood , William M. Hiatt , James M. Wark , David R. Hembree , Kyle K. Kirby , Pete A. Benson
IPC分类号： H01L23/02
CPC分类号： H01L21/561 , B33Y70/00 , B33Y80/00 , H01L21/563 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2221/68331 , H01L2224/02372 , H01L2224/0401 , H01L2224/05111 , H01L2224/05118 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05178 , H01L2224/0518 , H01L2224/05181 , H01L2224/05184 , H01L2224/05559 , H01L2224/05569 , H01L2224/05572 , H01L2224/05624 , H01L2224/05644 , H01L2224/05664 , H01L2224/05666 , H01L2224/13005 , H01L2224/13006 , H01L2224/13009 , H01L2224/13024 , H01L2224/13099 , H01L2224/16145 , H01L2224/73204 , H01L2224/97 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06582 , H01L2225/06596 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15312 , H01L2924/18161 , H01L2924/19015 , H01L2924/19041 , H01L2924/351 , H01L2924/207 , H01L2224/05552 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the base die. The component also includes an array of terminal contacts on the circuit side of the base die in electrical communication with the conductive vias. The component can also include an encapsulant on the back side of the base die, which substantially encapsulates the secondary die, and a polymer layer on the circuit side of the base die which functions as a protective layer, a rigidifying member and a stencil for forming the terminal contacts. A method for fabricating the component includes the step of bonding singulated secondary dice to base dice on a base wafer, or bonding a secondary wafer to the base wafer, or bonding singulated secondary dice to singulated base dice.
摘要翻译：半导体部件包括基模和层叠在基模上的二次模。基模具包括形成用于部件的内部信号传输系统的导电通孔，并允许二次管芯的电路侧接合到基座的后侧。该组件还包括与导电通孔电连通的基座芯片的电路侧上的端子触点阵列。该组件还可以包括在基模的背侧上的密封剂，其基本上封装次模，以及在用作保护层的基模的电路侧上的聚合物层，用于形成的用于固化的模板终端接触。一种用于制造该部件的方法包括将单个二次骰子接合到基底晶片上的基底骰子上，或将次晶片接合到基底晶片，或将单个二次骰子接合到单个基体骰子的步骤。

63. 发明授权

US07223626B2 Spacers for packaged microelectronic imagers and methods of making and using spacers for wafer-level packaging of imagers 有权
标题翻译：用于封装的微电子成像器的间隔器以及制造和使用间隔件用于成像器的晶片级封装的方法
公开(公告)号：US07223626B2
公开(公告)日：2007-05-29
申请号：US10922192
申请日：2004-08-19
申请人： Warren M. Farnworth , Alan G. Wood , James M. Wark , David R. Hembree , Rickie C. Lake
发明人： Warren M. Farnworth , Alan G. Wood , James M. Wark , David R. Hembree , Rickie C. Lake
IPC分类号： H01L21/00
CPC分类号： H01L31/0203 , H01L27/14618 , H01L27/14625 , H01L27/14634 , H01L27/14683 , H01L2224/48227 , H01L2224/48091 , H01L2924/00014
摘要： Methods of packaging microelectronic imagers and packaged microelectronic imagers. An embodiment of such a method can include providing an imager workpiece having a plurality of imager dies arranged in a die pattern and providing a cover substrate through which a desired radiation can propagate. The imager dies include image sensors and integrated circuitry coupled to the image sensors. The method further includes providing a spacer having a web that includes an adhesive and has openings arranged to be aligned with the image sensors. For example, the web can be a film having an adhesive coating, or the web itself can be a layer of adhesive. The method continues by assembling the imager workpiece with the cover substrate such that (a) the spacer is between the imager workpiece and the cover substrate, and (b) the openings are aligned with the image sensors. The attached web is not cured after the imager workpiece and the cover substrate have both been adhered to the web. As such, the web does not outgas contaminants into the compartments in which the image sensors are housed.
摘要翻译：包装微电子成像仪和封装的微电子成像仪的方法。这种方法的实施例可以包括提供具有以模片图案布置的多个成像模具的成像工件，并提供覆盖基板，期望的辐射可以通过该基板传播。成像器裸片包括耦合到图像传感器的图像传感器和集成电路。该方法还包括提供具有包括粘合剂并具有布置成与图像传感器对准的开口的腹板的间隔件。例如，网可以是具有粘合剂涂层的膜，或者网本身可以是一层粘合剂。该方法通过将成像器工件与盖基板组装成使得（a）间隔件位于成像器工件和盖基板之间，并且（b）开口与图像传感器对准，该方法继续。在成像器工件和盖基板都已经粘附在卷材上之后，连接的卷材不固化。因此，纸幅不会将污染物排出到其中容纳图像传感器的隔室中。

64. 发明授权

US06900459B2 Apparatus for automatically positioning electronic dice within component packages 失效
标题翻译：电子骰子在组件包中自动定位的装置
公开(公告)号：US06900459B2
公开(公告)日：2005-05-31
申请号：US10310752
申请日：2002-12-05
申请人： Warren M. Farnworth , Alan G. Wood , John O. Jacobson , David R. Hembree , James M. Wark , Jennifer L. Folaron , Robert J. Folaron , Jay C. Nelson , Lelan D. Warren
发明人： Warren M. Farnworth , Alan G. Wood , John O. Jacobson , David R. Hembree , James M. Wark , Jennifer L. Folaron , Robert J. Folaron , Jay C. Nelson , Lelan D. Warren
IPC分类号： G01R31/26 , G01R31/28 , G01R31/311 , H01L21/00 , H01L21/60 , H01L21/66 , H01L21/68 , H05K13/08 , H01L23/58 , G01R31/02
CPC分类号： H01L21/67276 , G01R31/2851 , G01R31/2886 , G01R31/2893 , G01R31/311 , H01L21/67126 , H01L21/67242 , H01L21/67259 , H01L21/681 , H01L24/74 , H01L2924/12042 , H01L2924/14 , H05K13/08 , Y10T29/49004 , Y10T29/49131 , Y10T29/53174 , Y10T29/53178 , H01L2924/00
摘要： A method and apparatus of assembling and disassembling semiconductor dice to be tested from the components of a temporary test package. A computer-controlled vision system is employed to align the dice with the temporary test package bases, and an automated robot arm system is employed to retrieve and assemble the dice with the various package components. The invention has particular utility in the burn-in and other pre-packaging testing of dice to establish known good dice (KGD).
摘要翻译：从临时测试包的组件组装和拆卸要测试的半导体骰子的方法和装置。采用计算机控制的视觉系统将骰子与临时测试包基座对准，并且采用自动机器人手臂系统来检索和组装骰子与各种包装部件。本发明在骰子的老化和其他预包装测试中具有特殊的用途，以建立已知的骰子（KGD）。

65. 发明授权

US06620731B1 Method for fabricating semiconductor components and interconnects with contacts on opposing sides 有权
公开(公告)号：US06620731B1
公开(公告)日：2003-09-16
申请号：US10035355
申请日：2002-01-04
申请人： Warren M. Farnworth , Alan G. Wood , David R. Hembree
发明人： Warren M. Farnworth , Alan G. Wood , David R. Hembree
IPC分类号： H01L2144
CPC分类号： H01L21/486 , H01L21/6835 , H01L21/76898 , H01L23/13 , H01L23/481 , H01L23/49827 , H01L23/5389 , H01L24/16 , H01L24/75 , H01L24/81 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/05569 , H01L2224/0557 , H01L2224/05573 , H01L2224/13099 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/16225 , H01L2224/16235 , H01L2224/73204 , H01L2224/75 , H01L2224/81801 , H01L2224/82039 , H01L2225/06513 , H01L2225/06541 , H01L2225/1005 , H01L2225/1058 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H05K1/0306 , H05K1/112 , H05K3/0029 , H05K3/0032 , H05K2201/09472 , H05K2201/0959 , H05K2201/09827 , H05K2201/09845 , H05K2201/10674 , H05K2201/10734 , H01L2924/00
摘要： A method for fabricating semiconductor components and interconnects includes the steps of providing a substrate, such as a semiconductor die, forming external contacts on opposing sides of the substrate by laser drilling vias through the substrate, and forming conductive members in the vias. The conductive members include enlarged terminal portions that are covered with a non-oxidizing metal. The method can be used to fabricate stackable semiconductor packages having integrated circuits in electrical communication with the external contacts. The method can also be used to fabricate interconnects for electrically engaging packages, dice and wafers for testing or for constructing electronic assemblies.

66. 发明授权

US06396291B1 Method for testing semiconductor components 失效
标题翻译：半导体元件测试方法
公开(公告)号：US06396291B1
公开(公告)日：2002-05-28
申请号：US09723101
申请日：2000-11-28
申请人： Salman Akram , David R. Hembree , Warren M. Farnworth , Derek Gochnour , Alan G. Wood , John O. Jacobson
发明人： Salman Akram , David R. Hembree , Warren M. Farnworth , Derek Gochnour , Alan G. Wood , John O. Jacobson
IPC分类号： G01R3102
CPC分类号： G01R1/0466 , G01R1/0483
摘要： A system and method for testing semiconductor components are provided. The system includes: a test board, sockets mounted to the test board in electrical communication with test circuitry, and carriers mounted to the sockets for housing the components. The carriers include bases, and interconnects mounted thereon, having contact members configured to make temporary electrical connections with contacts on the components. In addition, the contact members on the interconnects can be shaped to perform an alignment function, and to prevent excessive deformation of the contacts on the components. The sockets include camming members and electrical connectors configured to electrically contact the carriers with a zero insertion force. During a test procedure, the bases and interconnects can remain mounted to the sockets on the test board, as the components are aligned and placed in electrical contact with the interconnects. However, different bases and interconnects can be mounted to the sockets for testing different types of components.
摘要翻译：提供了一种用于测试半导体部件的系统和方法。该系统包括：测试板，安装在与测试电路电气通信的测试板上的插座，以及安装到插座以用于容纳部件的载体。载体包括底座和安装在其上的互连件，其具有被配置为与部件上的触点进行临时电连接的接触构件。此外，互连上的接触构件可以成形为执行对准功能，并且防止部件上的触点的过度变形。插座包括凸轮构件和被配置为以零插入力电接触托架的电连接器。在测试过程中，基板和互连件可以保持安装到测试板上的插座上，因为组件对齐并放置成与互连件电接触。然而，可以将不同的基座和互连件安装到插座以测试不同类型的部件。

67. 发明授权

US06340894B1 Semiconductor testing apparatus including substrate with contact members and conductive polymer interconnect 失效
标题翻译：半导体测试装置包括具有接触构件的基板和导电聚合物互连
公开(公告)号：US06340894B1
公开(公告)日：2002-01-22
申请号：US08947087
申请日：1997-10-08
申请人： Warren M. Farnworth , Alan G. Wood , Trung Tri Doan , David R. Hembree
发明人： Warren M. Farnworth , Alan G. Wood , Trung Tri Doan , David R. Hembree
IPC分类号： G01R3102
CPC分类号： H05K3/4007 , G01R1/0466 , G01R1/0483 , G01R3/00 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/48 , H01L24/85 , H01L2224/05554 , H01L2224/05573 , H01L2224/056 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/85001 , H01L2224/85205 , H01L2225/06562 , H01L2924/00014 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01032 , H01L2924/01033 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10161 , H01L2924/14 , H01L2924/15151 , H01L2924/15153 , H01L2924/15165 , H01L2924/15174 , H01L2924/15787 , H01L2924/16195 , H05K3/0058 , H05K3/0067 , H05K3/423 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H01L2224/78 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A die contacting substrate establishes ohmic contact with the die by means of raised portions on contact members. The raised portions are dimensioned so that a compression force applied to the die against the substrate results in a limited penetration of the contact member into the bondpads. The arrangement may be used for establishing electrical contact and with a burn-in oven and with a discrete die tester. This permits the die to be characterized prior to assembly, so that the die may then be transferred in an unpackaged form. A Z-axis anisotropic conductive interconnect material may be interposed between the die attachment surface and the die.
摘要翻译：模具接触衬底通过接触构件上的凸起部分与模具建立欧姆接触。凸起部分的尺寸被设计成使得对模具施加到基板上的压缩力导致接触构件有限地渗透到粘合垫中。该装置可以用于建立电接触以及使用老化烘箱和离散模具测试仪。这允许在组装之前对模具进行表征，从而可以以未包装的形式转移模具。 Z轴各向异性导电互连材料可以插入在模具附接表面和模具之间。

68. 发明授权

US06275052B1 Probe card and testing method for semiconductor wafers 有权
标题翻译：半导体晶圆的探针卡和测试方法
公开(公告)号：US06275052B1
公开(公告)日：2001-08-14
申请号：US09303367
申请日：1999-04-30
申请人： David R. Hembree , Warren M. Farnworth , Salman Akram , Alan G. Wood , C. Patrick Doherty , Andrew J. Krivy
发明人： David R. Hembree , Warren M. Farnworth , Salman Akram , Alan G. Wood , C. Patrick Doherty , Andrew J. Krivy
IPC分类号： G01R1073
CPC分类号： G01R1/073 , G01R31/2886
摘要： A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers. The membrane can be similar to multi layered TAB tape including metal foil conductors attached to a flexible, electrically-insulating, elastomeric tape. The probe card can be configured to contact all of the dice on the wafer at the same time, so that test signals can be electronically applied to selected dice as required.
摘要翻译：提供了用于测试半导体晶片的探针卡，以及使用探针卡测试晶片的方法和系统。探针卡被配置用于与测试电路电连通的常规测试装置，例如晶片探测器处理器。探针卡包括具有用于与晶片上的接触位置建立电连通的接触构件的互连基板。探针卡还包括用于将互连基板物理和电连接到测试装置的膜，以及用于缓冲由测试装置施加在互连基板上的压力的可压缩构件。互连衬底可以由具有穿透突起的凸起接触构件的硅形成。或者，接触构件可以形成为用于测试凸起的晶片的凹陷。膜可以类似于多层TAB带，其包括附接到柔性，电绝缘的弹性体带的金属箔导体。探针卡可以配置为同时接触晶片上的所有骰子，以便测试信号可以根据需要以电子方式应用于选定的骰子。

69. 发明授权

US06222379B1 Conventionally sized temporary package for testing semiconductor dice 失效
标题翻译：用于测试半导体骰子的常规尺寸的临时包装
公开(公告)号：US06222379B1
公开(公告)日：2001-04-24
申请号：US09093357
申请日：1998-06-08
申请人： Warren M. Farnworth , Alan G. Wood , David R. Hembree , Salman Akram
发明人： Warren M. Farnworth , Alan G. Wood , David R. Hembree , Salman Akram
IPC分类号： G01R3102
CPC分类号： G01R1/0466 , G01R1/0483 , G01R3/00 , G01R31/2863 , G01R31/2893 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/48 , H01L24/80 , H01L24/85 , H01L2224/16145 , H01L2224/48 , H01L2224/85001 , H01L2225/06562 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/0105 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H05K3/0058 , H05K3/0067 , H05K3/4007 , H05K3/423 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H01L2224/78 , H01L2224/45099 , H01L2224/05599 , H01L2924/00
摘要： A method for packaging and testing a semiconductor die is provided. The method includes forming a temporary package for the die that has a size, shape and lead configuration that is the same as a conventional plastic or ceramic semiconductor package. The temporary package can be used for burn-in testing of the die using standard equipment. The die can then be removed from the package and certified as a known good die. In an illustrative embodiment the package is formed in a SOJ configuration. The package includes a base, an interconnect and a force applying mechanism. The package base can be formed of ceramic or plastic using a ceramic lamination process or a Cerdip formation process.
摘要翻译：提供了一种用于封装和测试半导体管芯的方法。该方法包括形成具有与常规塑料或陶瓷半导体封装相同的尺寸，形状和引线配置的裸片的临时封装。临时包装可用于使用标准设备对模具进行老化测试。然后可以将模具从包装中取出并被认证为已知的好的模具。在说明性实施例中，封装形成为SOJ构造。该包装包括底座，互连和力施加机构。封装基底可以使用陶瓷层压工艺或Cerdip形成工艺由陶瓷或塑料制成。

70. 发明授权

US06215322B1 Conventionally sized temporary package for testing semiconductor dice 失效
公开(公告)号：US06215322B1
公开(公告)日：2001-04-10
申请号：US08888471
申请日：1997-07-07
申请人： Warren M. Farnworth , Alan G. Wood , David R. Hembree , Salman Akram
发明人： Warren M. Farnworth , Alan G. Wood , David R. Hembree , Salman Akram
IPC分类号： G01R3102
CPC分类号： G01R1/0466 , G01R1/0483 , G01R3/00 , G01R31/2863 , G01R31/2893 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/48 , H01L24/80 , H01L24/85 , H01L2224/16145 , H01L2224/48 , H01L2224/85001 , H01L2225/06562 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/0105 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H05K3/0058 , H05K3/0067 , H05K3/4007 , H05K3/423 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H01L2224/78 , H01L2224/45099 , H01L2224/05599 , H01L2924/00
摘要： A method for packaging and testing a semiconductor die is provided. The method includes forming a temporary package for the die that has a size, shape and lead configuration that is the same as a conventional plastic or ceramic semiconductor package. The temporary package can be used for burn-in testing of the die using standard equipment. The die can then be removed from the package and certified as a known good die. In an illustrative embodiment the package is formed in a SOJ configuration. The package includes a base, an interconnect and a force applying mechanism. The package base can be formed of ceramic or plastic using a ceramic lamination process or a Cerdip formation process.

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