专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20120281537A1 PACKET DECONSTRUCTION/RECONSTRUCTION AND LINK-CONTROL 有权
标题翻译：分组分解/重构和链接控制
公开(公告)号：US20120281537A1
公开(公告)日：2012-11-08
申请号：US13552028
申请日：2012-07-18
申请人： William H. Radke , Victor Y. Tsai , Peter Feeley , Neal A. Galbo , Robert N. Leibowitz
发明人： William H. Radke , Victor Y. Tsai , Peter Feeley , Neal A. Galbo , Robert N. Leibowitz
IPC分类号： H04L12/24 , H04W28/10 , H04W72/04 , H04L29/02 , H04L12/56
CPC分类号： H04L47/34 , H04L1/1867 , H04L47/27 , H04L69/324
摘要： The present disclosure includes methods, devices, and systems for packet processing. One method embodiment for packet flow control includes deconstructing a transport layer packet into a number of link-control layer packets, wherein each of the link-control layer packets has an associated sequence number, communicating the number of link-control layer packets via a common physical connection for a plurality of peripheral devices, and limiting a number of outstanding link-control layer packets during the communication.
摘要翻译：本公开包括用于分组处理的方法，设备和系统。用于分组流控制的一个方法实施例包括将传输层分组解构成多个链路控制层分组，其中链路控制层分组中的每一个具有相关联的序列号，经由共同的通信来传送链路控制层分组的数量用于多个外围设备的物理连接，并且在通信期间限制多个未完成的链路控制层分组。

62. 发明授权

US08296510B2 Hybrid memory management 有权
标题翻译：混合内存管理
公开(公告)号：US08296510B2
公开(公告)日：2012-10-23
申请号：US13295616
申请日：2011-11-14
申请人： William H. Radke , Michael Murray , Martin Ragnar Furuhjelm , John Geldman
发明人： William H. Radke , Michael Murray , Martin Ragnar Furuhjelm , John Geldman
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0246 , G06F2212/1016 , G06F2212/1036 , G06F2212/7201 , G06F2212/7211 , G11C16/349 , G11C2211/5641
摘要： Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage.
摘要翻译：用于使用单级和多级存储器单元来管理混合存储器件中的数据存储的方法和装置。逻辑地址可以基于执行的写操作的频率在单级和多级存储器单元之间分配。可以通过各种方法来确定与存储器中的逻辑地址相对应的数据的初始存储，包括首先将所有数据写入单级存储器或者首先将所有数据写入多级存储器。其他方法允许主机根据预期用途将逻辑地址写入指向单级或多级存储器单元。

63. 发明申请

US20120182810A1 METHODS, DEVICES, AND SYSTEMS FOR ADJUSTING SENSING VOLTAGES IN DEVICES 有权
标题翻译：用于调节设备中感应电压的方法，设备和系统
公开(公告)号：US20120182810A1
公开(公告)日：2012-07-19
申请号：US13007274
申请日：2011-01-14
申请人： William H. Radke , Zhenlei Shen , Peter Feeley
发明人： William H. Radke , Zhenlei Shen , Peter Feeley
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/0483 , G11C16/26
摘要： The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a controller configured to perform a sense operation on the memory cells using a sensing voltage to determine a quantity of the memory cells having a threshold voltage (Vt) greater than the sensing voltage and adjust a sensing voltage used to determine a state of the memory cells based, at least partially, on the determined quantity of memory cells.
摘要翻译：本公开包括用于调整设备中的感测电压的方法，设备和系统。一个或多个实施例包括存储器单元和被配置为使用感测电压对存储器单元执行感测操作的控制器，以确定具有大于感测电压的阈值电压（Vt）的存储器单元的数量并且调整感测电压用于至少部分地基于所确定的存储器单元的数量来确定存储器单元的状态。

64. 发明授权

US08122321B2 Methods of data handling 有权
标题翻译：数据处理方法
公开(公告)号：US08122321B2
公开(公告)日：2012-02-21
申请号：US12852923
申请日：2010-08-09
申请人： Brady L. Keays , Shuba Swaminathan , William H. Radke
发明人： Brady L. Keays , Shuba Swaminathan , William H. Radke
IPC分类号： G11C29/00
CPC分类号： G06F11/10 , G06F11/1048 , H03M13/132 , H03M13/1515
摘要： Methods of data handling include receiving data having a previously-generated error correction code and generating one or more error correction codes for the data, with each error correction code corresponding to the data having one or more particular bits of the data in differing data states. Such methods further include comparing the generated one or more error correction codes to the previously-generated error correction code, and if a particular one of the generated one or more error correction codes matches the previously-generated error correction code, transmitting the data having its one or more particular bits in the data states corresponding to that particular one of the generated one or more error correction codes. Methods of data handling may further include prioritizing the error correction in response to at least locations of known bad or questionable bits of the data.
摘要翻译：数据处理的方法包括接收具有先前生成的纠错码的数据并且生成数据的一个或多个纠错码，其中每个纠错码对应于具有不同数据状态的数据的一个或多个特定比特的数据。这样的方法还包括将生成的一个或多个纠错码与先前生成的纠错码进行比较，如果生成的一个或多个纠错码中的特定一个与先前生成的纠错码匹配，则发送具有其所述数据状态中的一个或多个特定位对应于所生成的一个或多个纠错码中的特定位。数据处理的方法还可以包括响应于数据的已知不良或可疑位的至少位置来对纠错进行优先排序。

65. 发明申请

US20120042225A1 DATA STORAGE WITH AN OUTER BLOCK CODE AND A STREAM-BASED INNER CODE 有权
标题翻译：数据存储与外部块代码和基于流程的内部代码
公开(公告)号：US20120042225A1
公开(公告)日：2012-02-16
申请号：US13281007
申请日：2011-10-25
申请人： William H. Radke
发明人： William H. Radke
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： G06F11/1068 , G11C7/1006 , H03M13/2906 , H03M13/2933
摘要： Apparatus and methods store stream-based error recovery data for a memory array, such as a NAND flash array. Conventionally, data is block coded per industry specification and stored in the memory array. Within the limits of the block code, this technique provides for correction of errors. By applying a stream-based inner code, that is, concatenating the outer block code with an outer code, the error correction can be further enhanced, enhancing the reliability of the device. This can also permit a relatively small-geometry device to be used in a legacy application.
摘要翻译：装置和方法存储用于诸如NAND闪存阵列的存储器阵列的基于流的错误恢复数据。通常，数据按行业规范进行块编码并存储在存储器阵列中。在块代码的限制内，该技术提供错误的校正。通过应用基于流的内部代码，即，将外部块代码与外部代码连接，可以进一步增强错误校正，增强设备的可靠性。这也可以允许在遗留应用中使用相对小的几何设备。

66. 发明申请

US20110280084A1 DETERMINING AND USING SOFT DATA IN MEMORY DEVICES AND SYSTEMS 有权
标题翻译：在存储器件和系统中确定和使用软数据
公开(公告)号：US20110280084A1
公开(公告)日：2011-11-17
申请号：US12778577
申请日：2010-05-12
申请人： William H. Radke , Zhenlei Shen , Peter Feeley
发明人： William H. Radke , Zhenlei Shen , Peter Feeley
IPC分类号： G11C16/06
CPC分类号： G11C16/26 , G11C7/14 , G11C11/26 , G11C11/5628 , G11C11/5642 , G11C16/349 , G11C29/021 , G11C29/028 , G11C29/42 , G11C29/50004
摘要： The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include an array of memory cells and control circuitry coupled to the array. The control circuitry is configured to perform a number of sense operations on the memory cells using a number of sensing voltages to determine soft data associated with a target state of the memory cells, and adjust a sensing voltage used to determine the target state based, at least partially, on the determined soft data.
摘要翻译：本公开包括用于在存储器设备和系统中确定和使用软数据的方法，设备和系统。一个或多个实施例包括耦合到阵列的存储器单元阵列和控制电路。控制电路被配置为使用多个感测电压对存储器单元执行多个感测操作，以确定与存储器单元的目标状态相关联的软数据，并且基于以下方式调整用于确定目标状态的感测电压：最少部分地在确定的软数据上。

67. 发明授权

US08051358B2 Error recovery storage along a nand-flash string 有权
标题翻译：沿着nand-flash字符串的恢复存储错误
公开(公告)号：US08051358B2
公开(公告)日：2011-11-01
申请号：US11774316
申请日：2007-07-06
申请人： William H. Radke
发明人： William H. Radke
IPC分类号： G11C29/00
CPC分类号： G06F11/1008 , G06F11/1072 , H03M13/256 , H03M13/2909
摘要： Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.
摘要翻译：设备和方法存储存储器阵列的不同维度的错误恢复数据。例如，在一个维度中，使用块纠错码（ECC），并且在另一维度中，使用补码纠错码，例如卷积码。通过使用单独的维度，缺陷影响两种错误恢复技术的可能性减弱，从而增加了可以成功执行错误恢复的概率。在一个示例中，块错误校正码用于沿着行存储的数据，并且该数据被存储在阵列的多级单元中。补充纠错码用于沿列存储的数据，例如沿着字符串的单元格，并且补充纠错码存储在与纠错码不同的电平上。

68. 发明申请

US20110185254A1 ERROR DETECTION AND CORRECTION SCHEME FOR A MEMORY DEVICE 有权
标题翻译：用于存储器件的错误检测和校正方案
公开(公告)号：US20110185254A1
公开(公告)日：2011-07-28
申请号：US13080299
申请日：2011-04-05
申请人： William H. Radke , Shuba Swaminathan , Brady L. Keays
发明人： William H. Radke , Shuba Swaminathan , Brady L. Keays
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： H03M13/096 , G06F11/1008
摘要： Data is read from a memory array. Before being stored in a data buffer, a Hamming code detection operation and a Reed-Solomon code detection operation are operated in parallel to determine if the data word has any errors. The results of the parallel detection operations are communicated to a controller circuit. If an error is present that can be corrected by the Hamming code correction operation, this is performed and the Reed-Solomon code detection operation is performed on the corrected word. If the error is uncorrectable by the Hamming code, the Reed-Solomon code correction operation is performed on the word.
摘要翻译：从存储器阵列中读取数据。在存储在数据缓冲器中之前，并行地操作汉明码检测操作和里德 - 所罗门码检测操作，以确定数据字是否具有任何错误。并行检测操作的结果被传送到控制器电路。如果存在可以通过汉明码校正操作来校正的错误，则执行该校正字，并且对校正字执行里德 - 所罗门码检测操作。如果汉明码不能校正错误，则对该字执行里德 - 所罗门码修正操作。

69. 发明申请

US20110122713A1 READ STROBE FEEDBACK IN A MEMORY SYSTEM 有权
标题翻译：在存储器系统中读取STROBE反馈
公开(公告)号：US20110122713A1
公开(公告)日：2011-05-26
申请号：US13021933
申请日：2011-02-07
申请人： William H. Radke
发明人： William H. Radke
IPC分类号： G11C7/22
CPC分类号： G11C7/1051 , G11C7/1063 , G11C16/26
摘要： A controller circuit is coupled to a memory device over a data/IO bus and a control bus. The controller circuit generates a read enable signal that is transmitted to the memory device to instruct the memory device to drive data onto the data/IO bus. The read enable signal is fed back to the controller circuit that then uses the fed back signal to read the data from the data/IO bus.
摘要翻译：控制器电路通过数据/ IO总线和控制总线耦合到存储器件。控制器电路产生读取使能信号，该信号被发送到存储器件以指示存储器件将数据驱动到数据/ IO总线上。读使能信号反馈到控制器电路，然后使用反馈信号从数据/ IO总线读取数据。

70. 发明申请

US20110047366A1 BOOTING IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION 有权
标题翻译：在具有连接配置中的设备的系统中进行操作
公开(公告)号：US20110047366A1
公开(公告)日：2011-02-24
申请号：US12545689
申请日：2009-08-21
申请人： William H. Radke , Victor Y. Tsai , Peter Feeley , Neal A. Galbo , Robert N. Leibowitz
发明人： William H. Radke , Victor Y. Tsai , Peter Feeley , Neal A. Galbo , Robert N. Leibowitz
IPC分类号： G06F15/177 , G06F13/28 , G06F12/06
CPC分类号： G06F9/4411 , G06F9/4401
摘要： The present disclosure includes methods, devices, and systems for booting in systems having devices coupled in a chained configuration. One or more embodiments include a host and a number of devices coupled to the host in a chained configuration, wherein at least one of the number of devices is a bootable device and the at least one bootable device is not directly coupled to the host.
摘要翻译：本公开包括用于在具有以链接配置耦合的设备的系统中引导的方法，设备和系统。一个或多个实施例包括以链接配置耦合到主机的主机和多个设备，其中，多个设备中的至少一个是可引导设备，并且所述至少一个可启动设备不直接耦合到主机。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式