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61. 发明授权

US6110787A Method for fabricating a MOS device 有权
标题翻译： MOS器件的制造方法
公开(公告)号：US6110787A
公开(公告)日：2000-08-29
申请号：US391886
申请日：1999-09-07
申请人： Lap Chan , Ting Cheong Ang , Shyue Pong Quek , Sang Yee Loong
发明人： Lap Chan , Ting Cheong Ang , Shyue Pong Quek , Sang Yee Loong
IPC分类号： H01L21/336 , H01L21/762 , H01L29/417 , H01L29/423
CPC分类号： H01L29/41775 , H01L21/76224 , H01L29/41783 , H01L29/6659 , H01L29/66628 , H01L29/78
摘要： A method of fabricating a MOS device having raised source/drain, raised isolation regions having isolation spacers, and a gate conductor having gate spacers is achieved. A layer of gate silicon oxide is grown over the surface of a semiconductor structure. A polysilicon layer is deposited overlying the gate silicon oxide layer. The polysilicon layer, gate silicon oxide layer and semiconductor structure are patterned and etched to form trenches. The trenches are filled with an isolation material to at least a level even with a top surface of the polysilicon layer to form raised isolation regions. The remaining polysilicon layer is patterned to remove polysilicon adjacent the raised isolation regions forming a gate conductor between the raised isolation regions. The gate conductor and the raised isolation regions having exposed sidewalls. The gate oxide layer between the gate conductor and raised isolation regions is removed. Isolation spacers are formed on the exposed sidewalls of the raised isolation regions and gate spacers are formed on the exposed sidewalls of the gate conductor. A layer of silicon is deposited and patterned to form raised source and drain adjacent the gate spacers with source and drain being doped to form a MOS device.
摘要翻译：实现了具有升高的源极/漏极，具有隔离间隔物的升高的隔离区域以及具有栅极间隔物的栅极导体的MOS器件的制造方法。在半导体结构的表面上生长栅极氧化硅层。沉积覆盖栅氧化硅层的多晶硅层。对多晶硅层，栅极氧化硅层和半导体结构进行图案化和蚀刻以形成沟槽。沟槽用隔离材料填充至少甚至具有多晶硅层的顶表面的水平以形成凸起的隔离区域。将剩余的多晶硅层图案化以去除在凸起的隔离区域之间形成栅极导体的凸起的隔离区域附近的多晶硅。栅极导体和凸起的隔离区域具有暴露的侧壁。去除栅极导体与升高隔离区之间的栅极氧化层。在凸起的隔离区域的暴露的侧壁上形成绝缘间隔物，并且栅极间隔物形成在栅极导体的暴露的侧壁上。沉积一层硅并图案化以形成与栅极间隔物相邻的凸起源极和漏极，源极和漏极被掺杂以形成MOS器件。

62. 发明授权

US6100195A Passivation of copper interconnect surfaces with a passivating metal layer 有权
公开(公告)号：US6100195A
公开(公告)日：2000-08-08
申请号：US222275
申请日：1998-12-28
申请人： Lap Chan , Kuan Pei Yap , Kheng Chok Tee , Flora S. Ip , Wye Boon Loh
发明人： Lap Chan , Kuan Pei Yap , Kheng Chok Tee , Flora S. Ip , Wye Boon Loh
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76849 , H01L21/76858 , H01L21/76867 , H01L21/76886
摘要： An interconnect line on an IMD layer on a semiconductor device is formed in an interconnect hole in the IMD layer. The interconnect hole has walls and a bottom in the IMD layer. A diffusion barrier is formed on the walls and the bottom of the hole. Fill the interconnect hole with a copper metal line. Perform a CMP step to planarize the device and to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole. Alternatively, a blanket deposit of a copper metal line layer covers the diffusion layer and fills the interconnect hole with a copper metal line. Perform a CMP process to planarize the device to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole in a self-aligned deposition process.

63. 发明授权

US5893787A Application of fast etching glass for FED manufacturing 失效
标题翻译：快速蚀刻玻璃在FED制造中的应用
公开(公告)号：US5893787A
公开(公告)日：1999-04-13
申请号：US805877
申请日：1997-03-03
申请人： Lap Chan , Simon Chooi
发明人： Lap Chan , Simon Chooi
IPC分类号： H01J9/02
CPC分类号： H01J9/025
摘要： The microtip housing cavity in a cold cathode display was formed by selecting for the dielectric layer surrounding it a material whose etch rate (for the same etchant) was 3 to 20 times faster than the etch rate of the gate layer. Specifically, a gaseous etchant that included CHF.sub.3, CH.sub.4, CO, or CO and C.sub.4 F.sub.8 was used to form the cavity in a layer consisting of silicon oxide containing between about 3 and 10 weight % boron and between about 3 and 10 weight % phosphorus, deposited by chemical vapor deposition at pressures somewhat less than atmospheric (commonly referred to as SABPSG or sub-atmospheric boro-phosphosilicate glass). The gate layer consisted of phosphorus-doped polysilicon. Using this combination, once the gate opening had been etched, etching of the cavity proceeded very rapidly with little increase in the width of the gate opening. Thus the cavity was formed in a single mask, single etchant process.
摘要翻译：冷阴极显示器中的微尖端壳体腔通过选择围绕其的介电层形成，其蚀刻速率（相同蚀刻剂）的蚀刻速率比栅极层的蚀刻速率快3至20倍。具体地，使用包括CHF 3，CH 4，CO或CO和C 4 F 8的气体蚀刻剂在由含有约3至10重量％硼和约3至10重量％磷之间的氧化硅组成的层中形成空腔，通过化学气相沉积在小于大气压（通常称为SABPSG或次大气硼硅磷酸盐玻璃）的压力下沉积。栅极层由磷掺杂多晶硅组成。使用这种组合，一旦栅极开口被蚀刻，腔的蚀刻就非常迅速地进行，门开口的宽度几乎没有增加。因此，腔形成在单个掩模中，单一蚀刻过程。

64. 发明授权

US5858870A Methods for gap fill and planarization of intermetal dielectrics 失效
标题翻译：间隙填充和金属间电介质平面化方法
公开(公告)号：US5858870A
公开(公告)日：1999-01-12
申请号：US767008
申请日：1996-12-16
申请人： Jai Zhen Zheng , Simon Yew-Meng Chooi , Lap Chan
发明人： Jai Zhen Zheng , Simon Yew-Meng Chooi , Lap Chan
IPC分类号： H01L21/314 , H01L21/318 , H01L21/768 , H01L21/283
CPC分类号： H01L21/76819 , H01L21/3144 , H01L21/318 , H01L21/3185
摘要： An improved method of gap filling and planarization in the dielectric layer by combining an anti-reflective coating with a CMP etch stop is described. Semiconductor device structures are provided in and on a semiconductor substrate. A conducting layer is deposited overlying the surfaces of the semiconductor device structures. A hard mask is deposited overlying the conducting layer wherein the hard mask acts as an anti-reflective coating. The conducting layer and the hard mask are patterned to form conducting lines wherein a gap is formed between the conducting lines. A first dielectric layer is deposited over the surfaces of the conducting lines wherein the gap remains between the conducting lines. A second dielectric layer is deposited overlying the first dielectric layer wherein the gap is filled by the second dielectric layer. The first and second dielectric layers are planarized wherein the hard mask acts as an etch stop or a polish stop. A third dielectric layer is deposited over the planarized first and second dielectric layers completing the fabrication of the integrated circuit device.
摘要翻译：描述了通过将抗反射涂层与CMP蚀刻停止层组合来改善介电层中间隙填充和平坦化的方法。半导体器件结构设置在半导体衬底中和半导体衬底上。导电层沉积在半导体器件结构的表面上。覆盖导电层的硬掩模被沉积，其中硬掩模用作抗反射涂层。导电层和硬掩模被图案化以形成导线，其中在导线之间形成间隙。第一介电层沉积在导线的表面上，其中间隙保留在导线之间。沉积第二介电层，覆盖第一介电层，其中间隙由第二介电层填充。第一和第二电介质层被平坦化，其中硬掩模用作蚀刻停止或抛光停止。第三介电层沉积在平坦化的第一和第二介电层上，完成了集成电路器件的制造。

65. 发明授权

US5731239A Method of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistance 失效
标题翻译：制造具有低薄层电阻的场效应晶体管的自对准硅化物窄栅电极的方法
公开(公告)号：US5731239A
公开(公告)日：1998-03-24
申请号：US787193
申请日：1997-01-22
申请人： Harianto Wong , Kin Leong Pey , Lap Chan
发明人： Harianto Wong , Kin Leong Pey , Lap Chan
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/66507 , H01L21/28052 , H01L29/665 , H01L29/6659 , H01L29/66545
摘要： A method for making low sheet resistance sub-quarter-micrometer gate electrode lengths on field effect transistors has been achieved. The method involves patterning gate electrodes on a silicon substrate from a conductively doped polysilicon layer having a silicon nitride layer on the surface. After forming the FET lightly doped drains (LDD), the sidewall spacers, and the heavily doped source/drain contact regions with titanium contacts, an insulating layer is chemically/mechanically polished back to the silicon nitride or silicon oxynitride on the gate electrode layer to form a planar self-aligning mask. A pre-amorphizing implantation is carried out, and a titanium silicide is selectively formed on the gate electrodes resulting in small grain sizes and much reduced sheet resistance. The self-aligned mask prevents ion implant damage to the shallow source/drain regions adjacent to the FET gate electrodes. A second embodiment uses the self-aligned mask to form selectively a cobalt silicide on the polysilicon gate electrodes for low sheet resistance, while preventing the cobalt silicide from reacting with the adjacent titanium silicide source/drain regions.
摘要翻译：已经实现了在场效应晶体管上制造低薄层电阻亚四分之一微米栅电极长度的方法。该方法包括从表面上具有氮化硅层的导电掺杂多晶硅层在硅衬底上图案化栅电极。在形成FET轻掺杂漏极（LDD），侧壁间隔物和具有钛触点的重掺杂源极/漏极接触区域之后，绝缘层被化学/机械地抛光回到栅极电极层上的氮化硅或氮氧化硅，至形成平面自对准掩模。进行预非晶化注入，并且在栅电极上选择性地形成硅化钛，导致小的晶粒尺寸和大大降低的薄层电阻。自对准掩模防止离子注入损坏与FET栅电极相邻的浅源/漏区。第二实施例使用自对准掩模在多晶硅栅电极上选择性地形成钴硅化物，用于低电阻，同时防止钴硅化物与相邻的硅化钛源极/漏极区发生反应。

66. 发明授权

US5652152A Process having high tolerance to buried contact mask misalignment by using a PSG spacer 失效
标题翻译：通过使用PSG间隔物对掩埋接触掩模未对准具有高耐受性的工艺
公开(公告)号：US5652152A
公开(公告)日：1997-07-29
申请号：US636086
申请日：1996-04-22
申请人： Yang Pan , Lap Chan , Ravi Sundaresan
发明人： Yang Pan , Lap Chan , Ravi Sundaresan
IPC分类号： H01L21/74 , H01L21/441
CPC分类号： H01L21/743
摘要： A new method of forming improved buried contact junctions is described. A layer of polysilicon overlying gate silicon oxide is provided over the surface of a semiconductor substrate and etched away to provide an opening to the substrate where a planned buried contact junction will be formed. A second doped polysilicon layer and a tungsten silicide layer are deposited and patterned to provide gate electrodes and a contact overlying the planned buried contact junction and providing an opening to the substrate where a planned source/drain region will be formed adjoining the planned buried contact junction and wherein a portion of the polysilicon layer not at the polysilicon contact remains as residue. The residue is etched away whereby a trench is etched into the substrate at the junction of the planned source/drain region and the planned buried contact junction. A doped glasseous layer is deposited overlying the patterned tungsten silicide/polysilicon layer and within the trench, then isotropically etched away until it remains only partially filling the trench. The substrate is oxidized to drive-in dopant from the doped glasseous layer within the trench into the surrounding substrate. Ions are implanted to form the planned source/drain region. Dopant is outdiffused from the second polysilicon layer to form the planned buried contact junction wherein the dopant surrounding the trench provides a conduction channel between the source/drain region and the adjoining buried contact junction.
摘要翻译：描述了形成改进的埋入接点的新方法。在半导体衬底的表面上提供覆盖栅极氧化硅的多晶硅层，并被蚀刻掉以提供到衬底的开口，其中将形成预定的埋入接触结。第二掺杂多晶硅层和硅化钨层被沉积并图案化以提供栅极电极和覆盖在计划的埋入接触结上的触点，并提供到衬底的开口，其中将形成预定的源极/漏极区域邻接计划的埋入接触结并且其中不在多晶硅接触处的多晶硅层的一部分保留为残留物。残留物被蚀刻掉，由此在规划的源极/漏极区域和计划的埋入接触结的接合处将沟槽蚀刻到衬底中。在图案化的硅化钨/多晶硅层上并在沟槽内沉积掺杂的硅酸盐层，然后各向同性地蚀刻掉，直到其仅部分地填充沟槽。衬底被氧化成驱动掺杂剂从沟槽内的掺杂的玻璃质层进入周围的衬底。植入离子以形成规划的源/漏区。掺杂剂从第二多晶硅层向外扩散以形成计划的埋入接触结，其中围绕沟槽的掺杂剂在源极/漏极区域和相邻的掩埋接触结点之间提供导电沟道。

67. 发明授权

US09015629B2 Content management systems and methods 有权
标题翻译：内容管理系统和方法
公开(公告)号：US09015629B2
公开(公告)日：2015-04-21
申请号：US13661687
申请日：2012-10-26
申请人： Lap Chan
发明人： Lap Chan
IPC分类号： G06F3/048 , G06F3/0481 , G06F3/0482 , G06F3/0486 , G06F3/0488 , H04M1/725
CPC分类号： G06F3/04817 , G06F3/0482 , G06F3/0486 , G06F3/04886 , H04M1/72519
摘要： Example systems and methods of managing content are described. In one implementation, a method accesses a first set of data, a second set of data, and menu data. The menu data is associated with multiple menu actions relevant to the first set of data and the second set of data. The method generates display data that allows a display device to present the first set of data, the second set of data, and the menu to a user such that the menu is positioned between the first set of data and the second set of data. The method receives a user selection of a menu action and, based on the user selection, generates a graphical object that allows the user to indicate whether to apply the selected menu action to the first set of data or the second set of data.
摘要翻译：描述了管理内容的示例系统和方法。在一个实现中，一种方法访问第一组数据，第二组数据和菜单数据。菜单数据与与第一组数据和第二组数据相关的多个菜单操作相关联。该方法产生允许显示设备向用户呈现第一组数据，第二组数据和菜单的显示数据，使得菜单位于第一组数据和第二组数据之间。该方法接收菜单动作的用户选择，并且基于用户选择，生成允许用户指示是否将所选择的菜单动作应用于第一组数据或第二组数据的图形对象。

68. 发明申请

US20140188552A1 METHODS AND SYSTEMS TO REACH TARGET CUSTOMERS AT THE RIGHT TIME VIA PERSONAL AND PROFESSIONAL MOOD ANALYSIS 审中-公开
标题翻译：通过个人和专业的MOOD分析，在适当的时间达到目标客户的方法和系统
公开(公告)号：US20140188552A1
公开(公告)日：2014-07-03
申请号：US13732790
申请日：2013-01-02
申请人： Lap Chan , Bin Duan
发明人： Lap Chan , Bin Duan
IPC分类号： G06Q30/02
CPC分类号： G06Q30/0269 , G06Q50/01
摘要： The disclosure generally describes computer-implemented methods, software, and systems for assessing a customer's mood by analyzing social network data. One computer-implemented method includes identifying a customer to monitor for mood, identifying at least one set of social network account information for the identified customer, accessing content items from at least one social network associated with the at least one set of social networking account information for the customer, determining a mood score for the identified customer based on the content items, and recording the determined mood score in a database.
摘要翻译：本公开通常描述了通过分析社交网络数据来评估客户心情的计算机实现的方法，软件和系统。一种计算机实现的方法包括识别客户以监视情绪，识别用于所识别的客户的至少一组社交网络帐户信息，从与至少一组社交网络帐户信息相关联的至少一个社交网络访问内容项目对于客户，基于内容项目确定所识别的客户的心情得分，并将确定的心情得分记录在数据库中。

69. 发明授权

US08237531B2 Tunable high quality factor inductor 有权
标题翻译：可调高品质因数电感
公开(公告)号：US08237531B2
公开(公告)日：2012-08-07
申请号：US11967270
申请日：2007-12-31
申请人： Ping Qiu , Chirn Chye Boon , Johnny Kok Wai Chew , Kiat Seng Yeo , Manh Anh Do , Lap Chan , Suh Fei Lim
发明人： Ping Qiu , Chirn Chye Boon , Johnny Kok Wai Chew , Kiat Seng Yeo , Manh Anh Do , Lap Chan , Suh Fei Lim
IPC分类号： H01F5/00 , H01F27/28 , H03J3/00
CPC分类号： H03J3/20 , H01F17/0006 , H01F2017/0073 , H03H11/48
摘要： An inductor circuit with high quality (Q) factor includes a primary inductor and a compensation sub-circuit. The compensation sub-circuit is electrically isolated from the primary inductor. The compensation sub-circuit is magnetically coupled with the primary inductor to compensate the loss in the primary inductor.
摘要翻译：具有高质量（Q）因子的电感器电路包括初级电感器和补偿子电路。补偿子电路与主电感器电隔离。补偿子电路与初级电感器磁耦合，以补偿初级电感器的损耗。

70. 发明授权

US08053340B2 Method for fabricating semiconductor devices with reduced junction diffusion 有权
标题翻译：制造具有减小的结扩散的半导体器件的方法
公开(公告)号：US08053340B2
公开(公告)日：2011-11-08
申请号：US11862213
申请日：2007-09-27
申请人： Benjamin Colombeau , Sai Hooi Yeong , Francis Benistant , Bangun Indajang , Lap Chan
发明人： Benjamin Colombeau , Sai Hooi Yeong , Francis Benistant , Bangun Indajang , Lap Chan
IPC分类号： H01L21/425 , H01L21/22 , H01L21/38
CPC分类号： H01L29/78612 , H01L29/66537 , H01L29/66772 , H01L29/78603 , H01L29/78621
摘要： A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling.
摘要翻译：一种晶体管，其包括设置在与栅极的相对侧相邻的衬底中的晕圈。晕区具有上部和下部区域。上部区域是具有多余空位的结晶区域，下部区域是非晶区域。源极/漏极扩散区域设置在光晕区域中。源极/漏极扩散区域与上部和下部晕圈重叠。该架构提供最小的延伸电阻以及最小的横向扩散，以实现更好的CMOS器件缩放。

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