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61. 发明授权

US07378720B2 Integrated stress relief pattern and registration structure 有权
标题翻译：综合应力消除模式和注册结构
公开(公告)号：US07378720B2
公开(公告)日：2008-05-27
申请号：US11695665
申请日：2007-04-03
申请人： Chung-min Fu , Huang-Sheng Lin , Yu-Chyi Harn , Hsien-Wei Chen
发明人： Chung-min Fu , Huang-Sheng Lin , Yu-Chyi Harn , Hsien-Wei Chen
IPC分类号： H01L23/544 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/585 , H01L23/544 , H01L23/562 , H01L2223/5442 , H01L2223/5448 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.
摘要翻译：具有形成在基板中的集成电路区域的半导体管芯包括：靠近集成电路区域设置在基板中的至少一个管芯拐角电路禁止（DCCF）区域; 以及形成在所述至少一个DCCF区域内的至少一个配准特征。所述至少一个配准特征包括从由激光熔丝标记，对准标记和监视标记组成的组中选择的结构。

62. 发明授权

US07361972B2 Chip packaging structure for improving reliability 有权
标题翻译：芯片封装结构，提高可靠性
公开(公告)号：US07361972B2
公开(公告)日：2008-04-22
申请号：US11385920
申请日：2006-03-20
申请人： Hsien-Wei Chen
发明人： Hsien-Wei Chen
IPC分类号： H01L29/06
CPC分类号： H01L29/0657 , H01L23/367 , H01L23/42 , H01L24/81 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/73253 , H01L2224/8121 , H01L2224/81815 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/10158 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2224/05599
摘要： A novel chip packaging structure is disclosed. The chip packaging structure includes a flip chip having a chip backside, at least one concave stress-relieving structure provided in the chip backside, a carrier substrate bonded to the flip chip and an adhesive material interposed between the flip chip and the carrier substrate. During thermal testing and/or functioning of the flip chip, the stress-relieving structure reduces stresses between the flip chip and the carrier substrate and dissipates heat from the flip chip to reduce thermally-induced delamination stresses applied to the adhesive material and thereby enhances reliability of the flip chip.
摘要翻译：公开了一种新颖的芯片封装结构。芯片封装结构包括具有芯片背面的倒装芯片，设置在芯片背面中的至少一个凹陷应力消除结构，接合到倒装芯片的载体基板和插入在倒装芯片和载体基板之间的粘合材料。在倒装芯片的热测试和/或功能过程中，应力消除结构减小了倒装芯片和载体衬底之间的应力，并且从倒装芯片散发热量，以减少施加到粘合剂材料上的热诱导分层应力，从而增强了可靠性的倒装芯片。

63. 发明申请

US20080076258A1 METHOD FOR FABRICATING AIR GAP FOR SEMICONDUCTOR DEVICE 有权
标题翻译：用于制造半导体器件的空气隙的方法
公开(公告)号：US20080076258A1
公开(公告)日：2008-03-27
申请号：US11533809
申请日：2006-09-21
申请人： Hsien-Wei Chen , Hsueh-Chung Chen , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Hsueh-Chung Chen , Shin-Puu Jeng
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/7682 , H01L21/0206
摘要： A method for fabricating an interconnect structure in a semiconductor device. A masking layer is formed on a dielectric layer formed on a substrate, having at least one opening. The opening is transferred into the dielectric layer. A Plasma stripping process is performed to remove the masking layer, such that a damaged sidewall portion of the dielectric layer surrounding the opening therein is formed. The opening in the dielectric layer is filled with a conductive element. The damaged sidewall portion of the dielectric layer is removed to form a gap between the dielectric layer and the conductive element, wherein substances from removal of the damaged sidewall portion of the dielectric layer are formed on the conductive element. The substances are removed using a citric acid solution.
摘要翻译：一种在半导体器件中制造互连结构的方法。在形成在基板上的电介质层上形成有至少一个开口的掩模层。开口转移到电介质层中。进行等离子体剥离处理以去除掩模层，从而形成围绕其中的开口的电介质层的受损侧壁部分。电介质层中的开口填充有导电元件。去除电介质层损坏的侧壁部分，以形成电介质层和导电元件之间的间隙，其中去除导电元件上介质层损坏的侧壁部分的物质。使用柠檬酸溶液除去物质。

64. 发明申请

US20070257339A1 SHIELD STRUCTURES 审中-公开
标题翻译：屏蔽结构
公开(公告)号：US20070257339A1
公开(公告)日：2007-11-08
申请号：US11382202
申请日：2006-05-08
申请人： Hsien-Wei Chen , Victor Chang , Tzu-Jin Yeh , Shu-Ying Cho , Keh-Jeng Chang , Kwang-Leei Young
发明人： Hsien-Wei Chen , Victor Chang , Tzu-Jin Yeh , Shu-Ying Cho , Keh-Jeng Chang , Kwang-Leei Young
IPC分类号： H01L23/62
CPC分类号： H01L23/552 , H01L23/5225 , H01L2924/0002 , H01L2924/3011 , H05K1/0219 , H05K1/0298 , H05K2201/09236 , H05K2201/09618 , H01L2924/00
摘要： Shield structures are provided. A first and second shield lines are formed over a substrate and coupled with a first voltage. A conductive line is formed between the first and the second shield lines, and coupled with a second voltage. The first shield layer is formed over the substrate and coupled to the first and the second shield lines via at least one first conductive structure.
摘要翻译：提供盾构结构。第一和第二屏蔽线形成在衬底上并与第一电压耦合。在第一和第二屏蔽线之间形成导线，并与第二电压耦合。第一屏蔽层形成在衬底上并且经由至少一个第一导电结构耦合到第一屏蔽线和第二屏蔽线。

65. 发明申请

US20070166887A1 Semiconductor device structure and methods of manufacturing the same 有权
标题翻译：半导体器件结构及其制造方法
公开(公告)号：US20070166887A1
公开(公告)日：2007-07-19
申请号：US11333618
申请日：2006-01-17
申请人： Hsien-Wei Chen , Hsueh-Chung Chen , Yi-Lung Cheng , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Hsueh-Chung Chen , Yi-Lung Cheng , Shin-Puu Jeng
IPC分类号： H01L21/82
CPC分类号： H01L27/0203 , G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method of generating a layout for a semiconductor device array is provided. A first layout is provided, comprising an active conductive feature, a boundary area surrounding the active conductive feature, and an open area other than the active conductive feature and the boundary area. A plurality of dummy templates of different pattern densities are provided, each of which comprises a plurality of dummy seeds. A second layout is generated by adding the dummy seeds on the open area according to at least one of the dummy templates.
摘要翻译：提供了一种生成半导体器件阵列布局的方法。提供了第一布局，包括有源导电特征，围绕有源导电特征的边界区域以及除了有源导电特征和边界区域之外的开放区域。提供了多个不同图案密度的虚拟模板，每个虚拟模板包括多个虚拟种子。通过根据至少一个虚拟模板将假种子添加到开放区域来生成第二布局。

66. 发明授权

US07202550B2 Integrated stress relief pattern and registration structure 有权
标题翻译：综合应力消除模式和注册结构
公开(公告)号：US07202550B2
公开(公告)日：2007-04-10
申请号：US10983425
申请日：2004-11-08
申请人： Chung-min Fu , Huang-Sheng Lin , Yu-Chyi Harn , Hsien-Wei Chen
发明人： Chung-min Fu , Huang-Sheng Lin , Yu-Chyi Harn , Hsien-Wei Chen
IPC分类号： H01L23/544 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/585 , H01L23/544 , H01L23/562 , H01L2223/5442 , H01L2223/5448 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.
摘要翻译：具有形成在基板中的集成电路区域的半导体管芯包括：靠近集成电路区域设置在基板中的至少一个管芯拐角电路禁止（DCCF）区域; 以及形成在所述至少一个DCCF区域内的至少一个配准特征。所述至少一个配准特征包括从由激光熔丝标记，对准标记和监视标记组成的组中选择的结构。

67. 发明申请

US20060244133A1 Design structure for coupling noise prevention 有权
公开(公告)号：US20060244133A1
公开(公告)日：2006-11-02
申请号：US11119868
申请日：2005-05-02
申请人： Hsien-Wei Chen , Hsueh-Chung Chen
发明人： Hsien-Wei Chen , Hsueh-Chung Chen
IPC分类号： H01L23/34
CPC分类号： H01L23/5225 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure for preventing coupling noise in integrated circuits and a method of forming the same are provided. The semiconductor structure includes a signal-grounded seal ring. The seal ring includes a plurality of metal lines, each in a respective metal layer and surrounding a circuit region of the semiconductor chip, a plurality of vias connecting respective metal lines, and a plurality of dielectric layers isolating each metal layer from any other metal layers. The seal ring may further include additional seal rings formed inside or outside the seal ring. The semiconductor structure may include laser fuses and protective rings. The protective rings are preferably signal grounded. Cross talk between sub circuits in a chip can be reduced by forming a seal ring extension between the sub circuits.

68. 发明申请

US20050263855A1 Integrated stress relief pattern and registration structure 有权
标题翻译：综合应力消除模式和注册结构
公开(公告)号：US20050263855A1
公开(公告)日：2005-12-01
申请号：US10983425
申请日：2004-11-08
申请人： Chung-min Fu , Huang-Sheng Lin , Yu-Chyi Harn , Hsien-Wei Chen
发明人： Chung-min Fu , Huang-Sheng Lin , Yu-Chyi Harn , Hsien-Wei Chen
IPC分类号： H01L23/00 , H01L23/544 , H01L23/58 , H01R13/627
CPC分类号： H01L23/585 , H01L23/544 , H01L23/562 , H01L2223/5442 , H01L2223/5448 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.
摘要翻译：具有形成在基板中的集成电路区域的半导体管芯包括：靠近集成电路区域设置在基板中的至少一个管芯拐角电路禁止（DCCF）区域; 以及形成在所述至少一个DCCF区域内的至少一个配准特征。所述至少一个配准特征包括从由激光熔丝标记，对准标记和监视标记组成的组中选择的结构。

69. 发明申请

US20050205991A1 System and method of heat dissipation in semiconductor devices 有权
标题翻译：半导体器件散热系统和方法
公开(公告)号：US20050205991A1
公开(公告)日：2005-09-22
申请号：US10801475
申请日：2004-03-16
申请人： Hsien-Wei Chen , Jiun-Lin Yeh , Shin-Puu Jeng , Yi-Lung Cheng
发明人： Hsien-Wei Chen , Jiun-Lin Yeh , Shin-Puu Jeng , Yi-Lung Cheng
IPC分类号： H01L21/3205 , H01L21/44 , H01L21/768 , H01L21/82 , H01L23/34 , H01L23/433 , H01L23/52 , H01L23/528 , H01L27/04
CPC分类号： H01L23/528 , H01L21/76834 , H01L21/76837 , H01L23/4334 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method and system for heat dissipation in semiconductor devices. In one example, an integrated circuit semiconductor device includes a semiconductor substrate; one or more metallurgy layers connected to the semiconductor substrate, and each of the one or more metallurgy layers includes: one or more conductive lines; and one or more dummy structures between the one or more conductive lines and at least two of the one or more dummy structures are connected; and one or more dielectric layers between the one or more metallurgy layers.
摘要翻译：本公开提供了一种用于半导体器件中散热的方法和系统。在一个示例中，集成电路半导体器件包括半导体衬底; 连接到半导体衬底的一个或多个冶金层，并且所述一个或多个冶金层中的每一个包括：一个或多个导电线; 并且连接所述一个或多个导电线与所述一个或多个虚拟结构中的至少两个之间的一个或多个虚设结构; 以及一个或多个冶金层之间的一个或多个电介质层。

70. 发明授权

US09613914B2 Post-passivation interconnect structure 有权
公开(公告)号：US09613914B2
公开(公告)日：2017-04-04
申请号：US13313811
申请日：2011-12-07
申请人： Hsien-Wei Chen , Hao-Yi Tsai , Mirng-Ji Lii , Chen-Hua Yu
发明人： Hsien-Wei Chen , Hao-Yi Tsai , Mirng-Ji Lii , Chen-Hua Yu
IPC分类号： H01L23/00 , H01L23/31 , H01L23/522 , H01L23/525
CPC分类号： H01L23/562 , H01L23/3114 , H01L23/3192 , H01L23/522 , H01L23/525 , H01L24/05 , H01L24/13 , H01L2224/02235 , H01L2224/02255 , H01L2224/02375 , H01L2224/02377 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05552 , H01L2224/05572 , H01L2224/05647 , H01L2224/05655 , H01L2224/13022 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2924/00014 , H01L2924/12042 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/01013 , H01L2924/01024 , H01L2924/01028 , H01L2924/0105 , H01L2924/01079 , H01L2924/01047 , H01L2924/00
摘要： A semiconductor device includes a passivation layer overlying a semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer overlies the interconnect structure and includes a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region.

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