专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US07990754B2 Resistance variable memory apparatus 有权
标题翻译：电阻变量存储装置
公开(公告)号：US07990754B2
公开(公告)日：2011-08-02
申请号：US12602414
申请日：2008-05-15
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Satoru Fujii
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Satoru Fujii
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/009 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1625
摘要： A resistance variable memory apparatus (100) of the present invention includes a current suppressing element (116) which is connected in series with each resistance variable layer (114) and whose threshold voltage is VF, and is configured to apply a first voltage V1 to a first wire (WL) associated with a selected nonvolatile memory element, apply a second voltage V2 to a second wire (BL) associated with the selected nonvolatile memory element, apply a third voltage V3 to a first wire (WL) which is not associated with the selected nonvolatile memory element and apply a fourth voltage V4 to a second wire (BL) which is not associated with the selected memory element when writing data or reading data, wherein V2≦V3
摘要翻译：本发明的电阻可变存储装置（100）具有与各个电阻变化层（114）串联连接且阈值电压为VF的电流抑制元件（116），并且将第一电压V1 与所选择的非易失性存储器元件相关联的第一线（WL）将第二电压V2施加到与所选择的非易失性存储器元件相关联的第二线（BL），将第三电压V3施加到不相关联的第一线（WL）使用所选择的非易失性存储元件，并且在写入数据或读取数据时将第四电压V4施加到与所选择的存储器元件不相关联的第二电线（BL），其中V2＆nlE; V3

62. 发明申请

US20110182109A1 VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE AND PROGRAMMING METHOD FOR SAME 有权
标题翻译：可变电阻非易失性存储器件及其编程方法
公开(公告)号：US20110182109A1
公开(公告)日：2011-07-28
申请号：US13121262
申请日：2010-07-26
申请人： Yuichiro Ikeda , Kazuhiko Shimakawa , Yoshihiko Kanzawa , Shunsaku Muraoka , Yoshikazu Katoh
发明人： Yuichiro Ikeda , Kazuhiko Shimakawa , Yoshihiko Kanzawa , Shunsaku Muraoka , Yoshikazu Katoh
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C13/0069 , G11C2213/72 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1625
摘要： A variable resistance nonvolatile memory device (100) according to an aspect of the present invention includes: a plurality of memory cells (M11, M12, M21, M22) in each of which a variable resistance element (R11, R12, R21, R22) and a current steering element (D11, D12, D21, D22) having two terminals are connected in series; a current limit circuit (105b) which limits a first current flowing in a direction for changing the memory cells (M11, M12, M21, M22) to a low resistance state; and a boost circuit (105d) which increases, when one of the memory cells (M11, M12, M21, M22) changes to the low resistance state, the first current in a first period before the memory cell changes to the low resistance state.
摘要翻译：根据本发明的一个方面的可变电阻非易失性存储器件（100）包括：多个存储单元（M11，M12，M21，M22），其中可变电阻元件（R11，R12，R21，R22）并且具有两个端子的电流控制元件（D11，D12，D21，D22）串联连接; 电流限制电路（105b），限制在用于将存储单元（M11，M12，M21，M22）改变的方向上流动的第一电流为低电阻状态; 以及升压电路（105d），当存储单元（M11，M12，M21，M22）中的一个变为低电阻状态时，在存储单元变为低电阻状态之前的第一周期内增加第一电流。

63. 发明申请

US20110128773A1 NONVOLATILE VARIABLE RESISTANCE MEMORY ELEMENT WRITING METHOD, AND NONVOLATILE VARIABLE RESISTANCE MEMORY DEVICE 有权
标题翻译：非易失性可变电阻记忆元件写入方法和非易失性可变电阻存储器件
公开(公告)号：US20110128773A1
公开(公告)日：2011-06-02
申请号：US12999019
申请日：2010-04-27
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Shunsaku Muraoka , Ken Kawai
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Shunsaku Muraoka , Ken Kawai
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0007 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2013/0073 , G11C2013/0083 , G11C2013/009 , G11C2013/0092 , G11C2213/15 , G11C2213/32 , G11C2213/56 , G11C2213/79
摘要： To provide a variable resistance element writing method that, even when a variable resistance element has a possibility of becoming a half LR state, can ensure a maximum resistance change window by correcting the variable resistance element to a normal low resistance state. In a method of writing data to a variable resistance element (10a) that reversibly changes between a high resistance state and a low resistance state according to a polarity of an applied voltage, as a voltage applied to an upper electrode (11) with respect to a lower electrode (14t): a positive voltage is applied in a high resistance writing step (405) to set the variable resistance element (10a) to a high resistance state (401); a negative voltage is applied in a low resistance writing step (406, 408) to set the variable resistance element (10a) to a low resistance state (403, 402); and a positive voltage is applied in a low resistance stabilization writing step (404) after the negative voltage is applied in the low resistance writing step (408), thereby setting the variable resistance element (10a) through the low resistance state to the high resistance state (401).
摘要翻译：为了提供可变电阻元件写入方法，即使当可变电阻元件具有成为半LR状态的可能性时，通过将可变电阻元件校正为正常的低电阻状态来确保最大电阻变化窗口。在根据施加电压的极性将数据写入到可变电阻元件（10a）的方法中，可变电阻元件（10a）根据施加电压的极性在高电阻状态和低电阻状态之间可逆地变化，作为施加到上电极（11）的电压相对于下电极（14t）：在高电阻写入步骤（405）中施加正电压以将可变电阻元件（10a）设置为高电阻状态（401）; 在低电阻写入步骤（406,408）中施加负电压以将可变电阻元件（10a）设置为低电阻状态（403,402）; 并且在低电阻写入步骤（408）中施加负电压之后，在低电阻稳定写入步骤（404）中施加正电压，从而将可变电阻元件（10a）设置为低电阻状态为高电阻州（401）。

64. 发明授权

US07916516B2 Nonvolatile memory apparatus and method for writing data in nonvolatile memory apparatus 有权
标题翻译：非易失性存储装置和用于在非易失性存储装置中写入数据的方法
公开(公告)号：US07916516B2
公开(公告)日：2011-03-29
申请号：US12524313
申请日：2008-02-22
申请人： Zhiqiang Wei , Kazuhiko Shimakawa , Takeshi Takagi , Yoshikazu Katoh
发明人： Zhiqiang Wei , Kazuhiko Shimakawa , Takeshi Takagi , Yoshikazu Katoh
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/34 , G11C2213/72 , H01L27/1021
摘要： A nonvolatile memory apparatus comprises a memory array (102) including plural first electrode wires (WL) formed to extend in parallel with each other within a first plane; plural second electrode wires (BL) formed to extend in parallel with each other within a second plane parallel to the first plane and to three-dimensionally cross the plural first electrode wires; and nonvolatile memory elements (11) which are respectively provided at three-dimensional cross points between the first electrode wires and the second electrode wires, the elements each having a resistance variable layer whose resistance value changes reversibly in response to a current pulse supplied between an associated first electrode wire and an associated second electrode wire; and a first selecting device (13) for selecting the first electrode wires, and further comprises voltage restricting means (15) provided within or outside the memory array, the voltage restricting means being connected to the first electrode wires, for restricting a voltage applied to the first electrode wires to a predetermined upper limit value or less; wherein plural nonvolatile memory elements of the nonvolatile memory elements are connected to one first electrode wire connecting the first selecting device to the voltage restricting means.
摘要翻译：非易失性存储装置包括存储器阵列（102），其包括形成为在第一平面内彼此平行延伸的多个第一电极线（WL）多个第二电极线（BL），其形成为在与第一平面平行的第二平面内彼此平行延伸并且三维地交叉所述多个第一电极线; 和非易失性存储元件（11），其分别设置在第一电极线和第二电极线之间的三维交叉点处，每个元件具有电阻变化层，其电阻值响应于在相关联的第一电极线和相关联的第二电极线; 以及用于选择所述第一电极线的第一选择装置（13），并且还包括设置在所述存储器阵列内或外的电压限制装置（15），所述电压限制装置连接到所述第一电极线，用于限制施加到所述第一电极线达到预定的上限值以下; 其中所述非易失性存储元件的多个非易失性存储元件连接到将所述第一选择装置连接到所述电压限制装置的一个第一电极线。

65. 发明申请

US20100202185A1 NONVOLATILE MEMORY DEVICE AND METHOD OF WRITING DATA TO NONVOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件和将数据写入非易失性存储器件的方法
公开(公告)号：US20100202185A1
公开(公告)日：2010-08-12
申请号：US12677421
申请日：2008-08-25
申请人： Yoshikazu Katoh , Kazuhiko Shimakawa
发明人： Yoshikazu Katoh , Kazuhiko Shimakawa
IPC分类号： G11C11/00 , G11C7/22
CPC分类号： G11C13/00 , G11C13/0038 , G11C13/0069 , G11C2013/0078 , G11C2213/15 , G11C2213/79
摘要： A nonvolatile memory device (300) is provided, including a memory cell array having plural resistance variable elements which are switchable between plural resistance states in response to electric pulses with the same polarity. A series resistance setting unit (310) is provided between the memory cell array (70) and an electric pulse application unit (50). The series resistance setting unit is controlled to change a resistance value of a series current path with a predetermined range with time in at least one of a case where the selected resistance variable element is switched from a low-resistance state to a high-resistance state and a case where the selected resistance variable element is switched from the high-resistance state to the low-resistance state.
摘要翻译：提供了一种非易失性存储器件（300），包括具有多个电阻可变元件的存储单元阵列，该电阻可变元件可响应于具有相同极性的电脉冲在多个电阻状态之间切换。在存储单元阵列（70）和电脉冲施加单元（50）之间设置串联电阻设定单元（310）。串联电阻设定单元被控制为在所选择的电阻可变元件从低电阻状态切换到高电阻状态的情况中的至少一个中随时间改变具有预定范围的串联电流路径的电阻值以及所选择的电阻可变元件从高电阻状态切换到低电阻状态的情况。

66. 发明申请

US20100110767A1 RESISTANCE VARIABLE MEMORY APPARATUS 有权
标题翻译：电阻可变存储器
公开(公告)号：US20100110767A1
公开(公告)日：2010-05-06
申请号：US12529103
申请日：2008-03-12
申请人： Yoshikazu Katoh , Kazuhiko Shimakawa
发明人： Yoshikazu Katoh , Kazuhiko Shimakawa
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C13/003 , G11C8/08 , G11C13/0028 , G11C13/0038 , G11C13/0069 , G11C2013/009 , G11C2213/15 , G11C2213/74 , G11C2213/76 , G11C2213/79
摘要： A resistance variable memory apparatus (10) of the present invention comprises a resistance variable element (1) which is switched to a high-resistance state when a voltage exceeds a first voltage and is switched to a low-resistance state when the voltage exceeds a second voltage, a controller (4), a voltage restricting active element (2) which is connected in series with the resistance variable element (1); and a current restricting active element which is connected in series with the resistance variable element (1) via the voltage restricting active element (2), and the controller (4) is configured to control the current restricting active element (3) so that a product of a current and a first resistance value becomes a first voltage or larger and to control the voltage restricting active element (2) so that the voltage between electrodes becomes smaller than a second voltage when the element is switched to the high-resistance state, while the controller (4) is configured to control the current restricting active element (3) so that an absolute value of a product of the current and the second resistance value becomes the second voltage or larger and an absolute value of a product of the current and the first resistance value becomes smaller than the first voltage, when the element is switched to the low-resistance state.
摘要翻译：本发明的电阻可变存储装置（10）具有电阻可变元件（1），当电压超过第一电压时，电阻可变元件（1）被切换到高电阻状态，当电压超过第二电压，控制器（4），与电阻可变元件（1）串联连接的电压限制有源元件（2）; 和电流限制有源元件（1）经由电压限制有源元件（2）与电阻可变元件（1）串联连接的电流限制有源元件，并且控制器（4）被配置为控制电流限制有源元件（3），使得电流和第一电阻值的乘积变为第一电压或更大，并且当元件切换到高电阻状态时，控制电压限制有源元件（2）使得电极之间的电压变得小于第二电压，而控制器（4）被配置为控制电流限制有源元件（3），使得电流和第二电阻值的乘积的绝对值变为第二电压或更大，并且电流的乘积的绝对值并且当元件切换到低电阻状态时，第一电阻值变得小于第一电压。

67. 发明申请

US20100046273A1 RESISTANCE CHANGE NONVOLATILE MEMORY DEVICE 有权
标题翻译：电阻变化非易失性存储器件
公开(公告)号：US20100046273A1
公开(公告)日：2010-02-25
申请号：US12513914
申请日：2008-06-20
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Satoru Fujii , Yoshihiko Kanazawa
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Satoru Fujii , Yoshihiko Kanazawa
IPC分类号： G11C11/00 , G11C11/36 , H01L47/00
CPC分类号： G11C13/003 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/32 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/77 , H01L27/101 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： Memory cells (MC) are formed at intersections of bit lines (BL) extending in the X direction and word lines (WL) extending in the Y direction. A plurality of basic array planes sharing the word lines (WL), each formed for a group of bit lines (BL) aligned in the Z direction, are arranged side by side in the Y direction. In each basic array plane, bit lines in even layers and bit lines in odd layers are individually connected in common. Each of selection switch elements (101 to 104) controls switching of electrical connection/non-connection between the common-connected even layer bit line and a global bit line (GBL), and each of selection switch elements (111 to 114) control switching of connection/non-connection between the common-connected odd layer bit line and the global bit line (GBL).
摘要翻译：存储单元（MC）形成在沿X方向延伸的位线（BL）和在Y方向上延伸的字线（WL）的交点处。在Y方向并排配置有分别形成为在Z方向排列的一组位线（BL）的字线（WL）的多个基本阵列平面。在每个基本阵列平面中，偶数层中的位线和奇数层中的位线共同单独连接。每个选择开关元件（101至104）控制共用连接偶数层位线与全局位线（GBL）之间的电连接/非连接的切换，并且每个选择开关元件（111至114）控制切换共同连接的奇数位位线和全局位线（GBL）之间的连接/非连接。

68. 发明授权

US06198671B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06198671B1
公开(公告)日：2001-03-06
申请号：US09506102
申请日：2000-02-17
申请人： Yasuhiro Aoyama , Kazuhiko Shimakawa , Kiyoto Ohta , Masanobu Hirose
发明人： Yasuhiro Aoyama , Kazuhiko Shimakawa , Kiyoto Ohta , Masanobu Hirose
IPC分类号： G11C700
CPC分类号： G11C5/14
摘要： The semiconductor memory device formed on a semiconductor substrate includes: a memory cell array having a plurality of memory cells formed at intersections between a plurality of word lines and a plurality of bit line pairs; a plurality of sense amplifiers each formed to correspond to each of the plurality of bit line pairs for amplifying a potential difference read on the bit line pair; and a low-level potential generation section for generating a low-level potential out of high-level and low-level potentials to be applied to the memory cells, the bit line pairs, and the sense amplifiers. The low-level potential generation section has: a ground potential generation part having a ground potential generation semiconductor element for generating as the low-level potential a first potential substantially equal to a ground potential; a threshold potential generation part having a threshold potential generation semiconductor element for generating as the low-level potential a second potential substantially equal to a threshold potential, and operating when a potential exceeding the threshold potential is applied; and a ground potential control part for controlling operation of the ground potential generation semiconductor element.
摘要翻译：形成在半导体衬底上的半导体存储器件包括：存储单元阵列，具有形成在多个字线和多个位线对之间的交叉处的多个存储单元; 多个读出放大器，每个形成为对应于多个位线对中的每一个，用于放大位线对上读取的电位差; 以及用于在施加到存储单元，位线对和读出放大器的高电平和低电平电位之间产生低电平电位的低电平电位产生部分。低电平电位产生部分具有：具有接地电位产生半导体元件的地电位产生部分，用于产生基本上等于地电势的第一电位作为低电位电位; 阈值电位产生部分，其具有用于产生基本上等于阈值电位的第二电位作为低电位电位的阈值电位产生半导体元件，并且当施加超过阈值电势的电位时操作; 以及用于控制地电位产生半导体元件的工作的接地电位控制部。

69. 发明授权

US06181633B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06181633B2
公开(公告)日：2001-01-30
申请号：US09433684
申请日：1999-11-04
申请人： Kazuhiko Shimakawa , Yuji Yamasaki
发明人： Kazuhiko Shimakawa , Yuji Yamasaki
IPC分类号： G11C800
CPC分类号： G11C8/10 , G11C7/18 , G11C11/4082 , G11C11/4087 , G11C11/409
摘要： A semiconductor device includes memory cells, each of which is a dynamic storage device, a memory cell array where the memory cells in a predetermined number are arranged in a matrix, the memory cells being connected to intersections of orthogonal word lines and bit lines; first sense amplifying circuits for amplifying electric potentials of the bit lines; main bit lines arranged in parallel to the bit lines; a memory block array formed such that a plurality of memory blocks including switching circuits share the main bit lines, the switching circuits controlling conductivity between outputs of the first sense amplifying circuits and the main bit lines; first selecting means for selecting the word lines and the first sense amplifying circuits belonging to at least one memory block of the plurality of memory blocks; second selecting means for selecting the switching circuits belonging to one memory block of the plurality of memory blocks; a control signal generating circuit for controlling the second selecting means. The semiconductor device includes a program circuit for programmably selecting either one of: acquiring addresses that specify positions of the memory cells as addresses for rows at a first timing; and acquiring addresses that specify positions of the memory cells as addresses for columns at a second timing that is different from the first timing.
摘要翻译：半导体器件包括存储单元，每个存储器单元是动态存储器件，存储单元阵列，其中预定数量的存储器单元以矩阵形式排列，存储器单元连接到正交字线和位线的交点; 用于放大位线的电位的第一感测放大电路; 与位线平行布置的主位线; 存储块阵列，其形成为包括切换电路的多个存储块共享主位线，切换电路控制第一读出放大电路的输出与主位线之间的导通性; 第一选择装置，用于选择属于多个存储块的至少一个存储块的字线和第一读出放大电路; 第二选择装置，用于选择属于多个存储块的一个存储块的切换电路; 用于控制第二选择装置的控制信号发生电路。半导体器件包括用于可编程地选择以下任一个的程序电路：将指定存储器单元的位置的地址作为第一定时的行的地址; 以及在与第一定时不同的第二定时处获取指定存储器单元的位置的地址作为列的地址。

70. 发明授权

US09378817B2 Variable resistance nonvolatile memory element writing method and variable resistance nonvolatile memory device 有权
标题翻译：可变电阻非易失性存储元件写入方法和可变电阻非易失性存储器件
公开(公告)号：US09378817B2
公开(公告)日：2016-06-28
申请号：US13581925
申请日：2012-03-22
申请人： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh
发明人： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0064 , G11C2013/0073 , G11C2013/0083 , G11C2013/0092
摘要： A variable resistance nonvolatile memory element writing method of, by applying a voltage pulse to a memory cell including a variable resistance element, reversibly changing the variable resistance element between a first resistance state and a second resistance state according to a polarity of the applied voltage pulse is provided. The variable resistance nonvolatile memory element writing method includes applying a first preliminary voltage pulse and subsequently applying the first voltage pulse to the variable resistance element to change the variable resistance element from the second resistance state to the first resistance state, the first preliminary voltage pulse being smaller in voltage absolute value than the second threshold voltage and different in polarity from the first voltage pulse.
摘要翻译：一种可变电阻非易失性存储元件写入方法，通过向包括可变电阻元件的存储单元施加电压脉冲，根据所施加的电压脉冲的极性可逆地改变第一电阻状态和第二电阻状态之间的可变电阻元件被提供。可变电阻非易失性存储元件写入方法包括施加第一初步电压脉冲，并随后将第一电压脉冲施加到可变电阻元件，以将可变电阻元件从第二电阻状态改变到第一电阻状态，第一初步电压脉冲为电压绝对值比第二阈值电压小，并且极性与第一电压脉冲不同。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式