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    • 61. 发明授权
    • Packet relaying apparatus and high speed multicast system
    • 分组中继设备和高速组播系统
    • US06778532B1
    • 2004-08-17
    • US09389301
    • 1999-09-02
    • Shinichi AkahaneKazuo SugaiTakeshi AimotoNobuhito MatsuyamaYoshihito SakoHiroshi Sekino
    • Shinichi AkahaneKazuo SugaiTakeshi AimotoNobuhito MatsuyamaYoshihito SakoHiroshi Sekino
    • H04J110
    • H04L45/742H04L12/18H04L12/46H04L45/00H04L45/16
    • In a high speed multicast route searching method of searching information of a transmission port to which a received multicast packet is next transferred: a route address is formed by coupling a receiver address and a sender address in this order; one p-th power-of-2-branch tree node is configured by a collection of one two-branch tree node and two-branch tree nodes of p−1 stages totalling ((p-th power of 2)−1) nodes just under the one two-branch tree node to form a p-th power-of-2-branch tree which is stored in a memory; not one bit but consecutive p bits of the route address coupling the receiver address and sender address in a received multicast packet in this order are checked at the same time; and in accordance with the values of the consecutive bits, a search tree stored in the memory is searched. In this manner, a search process can be completed by tracing nodes (the number of bits of a search key divided by p) times at a maximum, independently from the number of entries.
    • 在高速多播路由搜索方法中,搜索接收到的多播分组的下一个传输的传输端口的信息:通过按照该顺序耦合接收机地址和发送方地址来形成路由地址; 一个p个2分支树状节点由一个两分支树节点和总共((p-th功率为2)-1)个节点的p-1级的两分支树节点的集合来配置 恰好在一个双分支树节点之下,以形成存储在存储器中的第p个2分支树枝; 不是一个位,而是同时检查在接收到的组播数据包中按顺序耦合接收器地址和发送方地址的路由地址的连续p位; 并且根据连续比特的值,搜索存储在存储器中的搜索树。 以这种方式,可以独立于条目的数量,通过跟踪节点(搜索关键字的比特数除以p)乘以最大值来完成搜索处理。
    • 63. 发明授权
    • Data processing system having subsystems connected by busses
    • 具有通过总线连接的子系统的数据处理系统
    • US5584004A
    • 1996-12-10
    • US855091
    • 1992-03-20
    • Takeshi AimotoAkira IshiyamaHidenori KosugiMasabumi Shibata
    • Takeshi AimotoAkira IshiyamaHidenori KosugiMasabumi Shibata
    • G06F12/06G06F13/36G06F15/17G06F12/02
    • G06F12/0692
    • A data processing system is provided which includes a plurality of subsystems each including at least one instruction processor, at least one input/output device and at least one main storage device connected by local bus. The subsystems are connected to one another through bus extenders and inter-subsystem transfer lines. Each of the main storage devices is assigned for a partial address space as a part of the system address space. When an instruction processor or an input/output processor on each of the subsystems makes access to a main storage device, the operation of the system is as follows. If the address of access is in the address space limit of a main storage device on an inner subsystem, access to the main storage device on the inner subsystem is made. If the address of access is out of the address space limit of the main storage device on the inner subsystem and in the system address space assigned to the system, access to a main storage device on one of outer subsystems is made through a bus extender on the inner subsystem, inter-subsystem transfer lines and another bus extender on the one outer subsystems.
    • 提供了一种数据处理系统,其包括多个子系统,每个子系统包括至少一个指令处理器,至少一个输入/输出设备以及通过本地总线连接的至少一个主存储设备。 子系统通过总线扩展器和子系统间传输线相互连接。 每个主存储设备被分配为部分地址空间作为系统地址空间的一部分。 当每个子系统上的指令处理器或输入/输出处理器访问主存储设备时,系统的操作如下。 如果访问地址在内部子系统上的主存储设备的地址空间限制内,则进入内部子系统上的主存储设备。 如果访问地址超出内部子系统上的主存储设备的地址空间限制,以及分配给系统的系统地址空间,则通过总线扩展器访问外部子系统之一的主存储设备 内部子系统,子系统间传输线路和一个外部子系统上的另一个总线扩展器。
    • 66. 发明授权
    • Packet switch and switching method for switching variable length packets
    • 用于切换可变长度分组的分组交换和切换方法
    • US07602783B2
    • 2009-10-13
    • US10197464
    • 2002-07-18
    • Takeshi Aimoto
    • Takeshi Aimoto
    • H04L12/28
    • H04L47/528H04L47/10H04L47/2441H04L47/50H04L47/521H04L47/525H04L49/205H04L49/3009H04L49/3027H04L49/90H04L49/9063
    • A packet switch for switching variable length packets, where each output port interface includes a buffer memory for storing transmission packets, a transmission priority controller for classifying, based on a predetermined algorithm, transmission packets passed from a packet switching unit into a plurality of queue groups to which individual bandwidths are assigned respectively, and queuing the transmission packets in the buffer memory so as to form a plurality of queues according to transmission priority in each of the queue groups and a packet read-out controller for reading out the transmission packets from each of the queue groups in the buffer memory according to the order of transmission priority of the packets while guaranteeing the bandwidth assigned to the queue group.
    • 一种用于切换可变长度分组的分组交换机,其中每个输出端口接口包括用于存储传输分组的缓冲存储器;传输优先级控制器,用于基于预定算法将从分组交换单元传递到多个队列组中的传输分组 分别分配给哪个单独的带宽,并且将缓冲存储器中的传输分组排队,以根据每个队列组中的传输优先级形成多个队列,以及分组读出控制器,用于从每个队列组读出传输分组 根据分组的传输优先级顺序,在保证分配给队列组的带宽的同时,缓冲存储器中的队列组。