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61. 发明申请

US20130069195A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130069195A1
公开(公告)日：2013-03-21
申请号：US13419882
申请日：2012-03-14
申请人： Kyoichi Suguro
发明人： Kyoichi Suguro
IPC分类号： H01L21/762 , H01L29/12
CPC分类号： H01L21/76254
摘要： According to one embodiment, a fabrication method for a semiconductor device includes: injecting an ion into a first substrate; joining the first substrate and a second substrate; irradiating a microwave to agglomerate the ion in a planar state in a desired position in the first substrate and form an agglomeration region spreading in a planar state; separating the second substrate provided with a part of the first substrate from the rest of the first substrate by exfoliating the joined first substrate from the second substrate in the agglomeration region; and grinding a part of the second substrate on a back surface opposite to an exfoliated surface in the second substrate provided with a part of the first substrate.
摘要翻译：根据一个实施例，一种用于半导体器件的制造方法包括：将离子注入第一衬底; 接合第一基板和第二基板; 照射微波以使平面状态的离子在第一基板中的期望位置聚集，并形成在平面状态下扩散的聚集区域; 通过将结合的第一基板从附聚区域中的第二基板剥离而将设置有第一基板的一部分的第二基板与第一基板的其余部分分离; 以及在设置有所述第一基板的一部分的所述第二基板中的与所述剥离表面相对的背面上研磨所述第二基板的一部分。

62. 发明申请

US20090206379A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090206379A1
公开(公告)日：2009-08-20
申请号：US12389266
申请日：2009-02-19
申请人： Soichirou Kitazaki , Hideaki Aochi , Kyoichi Suguro
发明人： Soichirou Kitazaki , Hideaki Aochi , Kyoichi Suguro
IPC分类号： H01L25/00 , H01L21/00 , H01L29/66 , H01L21/336
CPC分类号： H01L21/76831 , G11C11/22 , H01G4/1245 , H01G4/1254 , H01G4/33 , H01L21/31612 , H01L21/3162 , H01L21/31691 , H01L21/3185 , H01L23/485 , H01L23/5226 , H01L27/11507 , H01L28/55 , H01L28/65 , H01L29/665 , H01L29/66575 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device which can prevent the degradation of contact yield even when subjected to a high-temperature and long-time thermal process, and a manufacturing method thereof are provided. The semiconductor device includes: a first semiconductor circuit formed on a semiconductor substrate; a second semiconductor circuit formed above the first semiconductor circuit; an interlayer insulating film formed between the first semiconductor circuit and the second semiconductor circuit; and a contact plug formed in a state of penetrating the interlayer insulating film, the contact plug including a contact plug body made up of a conductor, and a contact plug coating which is insulating and which covers at least a portion of a side face of the contact plug body in contact with the interlayer insulating film.
摘要翻译：提供即使经受高温长时间热处理也能够防止接触性降低的半导体装置及其制造方法。半导体器件包括：形成在半导体衬底上的第一半导体电路; 形成在所述第一半导体电路之上的第二半导体电路; 形成在所述第一半导体电路和所述第二半导体电路之间的层间绝缘膜; 以及以穿透层间绝缘膜的状态形成的接触塞，所述接触插塞包括由导体构成的接触插塞体和绝缘的接触塞涂层，并且覆盖所述接触插塞的侧面的至少一部分接触插塞体与层间绝缘膜接触。

63. 发明授权

US07557040B2 Method of manufacture of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US07557040B2
公开(公告)日：2009-07-07
申请号：US11644887
申请日：2006-12-26
申请人： Hiroshi Itokawa , Yoshimasa Kawase , Toshihiko Iinuma , Haruko Akutsu , Kyoichi Suguro
发明人： Hiroshi Itokawa , Yoshimasa Kawase , Toshihiko Iinuma , Haruko Akutsu , Kyoichi Suguro
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： A semiconductor device manufacturing method is disclosed. A silicon-containing gate electrode is first formed above the surface of a silicon-containing semiconductor substrate. Then, a sidewall insulating film is formed on the sidewall of the gate electrode and a film of metal is formed on the semiconductor substrate to cover the gate electrode and the sidewall insulating film. The front and back sides of the semiconductor substrate are heated through heat conduction by an ambient gas. Thereby, the metal is caused to react with silicon contained in the semiconductor substrate and the gate electrode to form a metal silicide film.
摘要翻译：公开了半导体器件制造方法。首先在含硅半导体衬底的表面上形成含硅栅电极。然后，在栅电极的侧壁上形成侧壁绝缘膜，并且在半导体衬底上形成金属膜以覆盖栅电极和侧壁绝缘膜。通过环境气体的热传导来加热半导体衬底的正面和背面。由此，使金属与包含在半导体衬底和栅电极中的硅反应，形成金属硅化物膜。

64. 发明授权

US07495293B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07495293B2
公开(公告)日：2009-02-24
申请号：US11512187
申请日：2006-08-30
申请人： Toshihiko Iinuma , Haruko Akutsu , Kyoichi Suguro
发明人： Toshihiko Iinuma , Haruko Akutsu , Kyoichi Suguro
IPC分类号： H01L27/088 , H01L21/28
CPC分类号： H01L21/28518 , H01L21/28052 , H01L29/495 , H01L29/4966 , H01L29/665 , H01L29/66795 , H01L29/785 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a silicon region including Si, and a silicide film provided on the silicon region, the silicide film comprising a compound of Si with Ni, Co, Pd, or Pt and including Er.
摘要翻译：半导体器件包括包含Si的硅区域和设置在硅区域上的硅化物膜，该硅化物膜包含Si与Ni，Co，Pd或Pt的化合物并包括Er的化合物。

65. 发明授权

US07144794B2 Ion source, ion implanting device, and manufacturing method of semiconductor devices 失效
标题翻译：离子源，离子注入装置以及半导体装置的制造方法
公开(公告)号：US07144794B2
公开(公告)日：2006-12-05
申请号：US10969025
申请日：2004-10-21
申请人： Kyoichi Suguro
发明人： Kyoichi Suguro
IPC分类号： H01L21/425
CPC分类号： H01J27/14 , H01J37/08 , H01J2237/31701
摘要： This ion source includes a chamber having an internal wall surface and an external wall surface, and also includes a cathode, which is provided to be insulated from the chamber, capable of emitting thermal electrons into the chamber, and has a cathode cap protruding into the chamber from an external side of an opening part which is formed to pass through from the external wall surface to the internal wall surface of the chamber and a filament disposed inside the cathode cap, the cathode cap and/or the filament being an alloy containing tungsten (W) as a major component and a predetermined metal element as a minor component.
摘要翻译：该离子源包括具有内壁表面和外壁表面的室，并且还包括阴极，该阴极被提供以与室绝缘，能够将热电子发射到室中，并且具有突出到阴极盖中的阴极帽腔室，其从形成为从外壁表面通过的开口部分的外侧延伸到腔室的内壁表面;以及细丝，其设置在阴极帽内部，阴极帽和/或细丝为含有钨的合金（W）作为主要成分，预定的金属元素作为次要成分。

66. 发明申请

US20060263704A1 Semiconductor device manufacturing method and semiconductor manufacturing apparatus 失效
标题翻译：半导体装置的制造方法和半导体制造装置
公开(公告)号：US20060263704A1
公开(公告)日：2006-11-23
申请号：US11488849
申请日：2006-07-19
申请人： Takeshi Shibata , Hisanori Misawa , Kyoichi Suguro
发明人： Takeshi Shibata , Hisanori Misawa , Kyoichi Suguro
IPC分类号： G03F1/00 , H01L21/00 , H01L21/22
CPC分类号： H01L21/266
摘要： A method of manufacturing a semiconductor device is disclosed, which comprises setting a stencil mask above a substrate to be processed in confronting to the substrate, the stencil mask having an opening, and irradiating the substrate with charged particles through the opening of the stencil mask, while adjusting a potential difference between the stencil mask and the substrate depending on a value of a current flowing between the substrate and the stencil mask.
摘要翻译：公开了一种制造半导体器件的方法，其包括将待加工衬底上的模版掩模设置在与衬底相对的位置上，所述模板掩模具有开口，并且通过所述模板掩模的开口对所述衬底照射带电粒子，同时根据在基板和模板掩模之间流动的电流的值调节模板掩模和基板之间的电位差。

67. 发明授权

US07098120B2 Method of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07098120B2
公开(公告)日：2006-08-29
申请号：US10770520
申请日：2004-02-04
申请人： Tomohiro Saito , Kyoichi Suguro
发明人： Tomohiro Saito , Kyoichi Suguro
IPC分类号： H01L21/425
CPC分类号： H01L29/66545 , H01L21/265 , H01L21/28097 , H01L21/324 , H01L21/823835 , H01L21/823842 , H01L21/823878 , H01L29/4975
摘要： A method of manufacturing semiconductor devices includes forming element isolation regions in a semiconductor substrate, a gate insulation film in an element region surrounded by the element isolation regions and an impurity doped metal silicide film on the gate insulation film; irradiating energy beams to heat the silicide film; forming a gate electrode film by patterning the silicide film; and forming source and drain regions by doping an impurity into said element region by using at least the gate electrode film as a mask.
摘要翻译：半导体器件的制造方法包括在半导体衬底中形成元件隔离区域，在元件隔离区域包围的元件区域中的栅极绝缘膜和栅极绝缘膜上的杂质掺杂金属硅化物膜; 照射能量束以加热硅化物膜; 通过图案化硅化物膜形成栅电极膜; 以及通过至少使用栅电极膜作为掩模，将杂质掺杂到所述元件区域中来形成源区和漏区。

68. 发明授权

US07078776B2 Low threshold voltage semiconductor device 失效
标题翻译：低阈值电压半导体器件
公开(公告)号：US07078776B2
公开(公告)日：2006-07-18
申请号：US10867797
申请日：2004-06-16
申请人： Kazumi Nishinohara , Yasushi Akasaka , Kyoichi Suguro
发明人： Kazumi Nishinohara , Yasushi Akasaka , Kyoichi Suguro
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66583 , H01L21/823807 , H01L27/092 , H01L29/105 , H01L29/66537 , H01L29/66545 , H01L29/66628
摘要： A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities, whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region. This semiconductor device is capable of suppressing net impurity concentration variations as well as threshold voltage variations to be caused by a short channel effect or manufacturing variations.
摘要翻译：半导体器件具有形成在半导体衬底中并且由于第一半导体区域中包含的第一导电型有源杂质而具有第一导电类型的第一半导体区域，以及形成在第一半导体区域和第一半导体区域之间的第二半导体区域并且由于第二半导体区域中包含的第二导电型有源杂质而具有第二导电类型。第二半导体区域包含第一导电型有源杂质，其浓度为零或小于第二半导体区域中所含的第二导电型有源杂质浓度的四分之一。绝缘膜和导体形成在第二半导体区域上。在与第二半导体区域的侧面接触的半导体表面处形成第二导电类型的第三和第四半导体区域。该半导体器件能够抑制净杂质浓度变化以及由短沟道效应或制造变化引起的阈值电压变化。

69. 发明申请

US20060131676A1 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060131676A1
公开(公告)日：2006-06-22
申请号：US11289694
申请日：2005-11-30
申请人： Tomohiro Saito , Kyoichi Suguro
发明人： Tomohiro Saito , Kyoichi Suguro
IPC分类号： H01L29/94 , H01L21/3205
CPC分类号： H01L21/823842 , H01L21/823835
摘要： A semiconductor device includes: a substrate having a silicon layer on at least a surface thereof; an insulating film formed on the silicon layer; a first electrode formed on the insulating film and including a first metal thin film and a film having silicon formed on the first metal thin film; and a second electrode formed on the insulating film and including a metal silicide which is an alloy of the first metal and silicon, and a film having silicon formed on the metal silicide, wherein the first electrode is formed on a surface of the first metal thin film, and further includes a compound which controls a reaction of the first metal and the silicon.
摘要翻译：半导体器件包括：至少在其表面上具有硅层的衬底; 形成在硅层上的绝缘膜; 在所述绝缘膜上形成的第一电极，其具有形成在所述第一金属薄膜上的第一金属薄膜和具有硅的膜; 以及形成在所述绝缘膜上并且包括作为所述第一金属和硅的合金的金属硅化物的第二电极和形成在所述金属硅化物上的具有硅的膜，其中所述第一电极形成在所述第一金属薄层的表面上并且还包括控制第一金属和硅的反应的化合物。

70. 发明授权

US06939787B2 Method for fabricating semiconductor device having gate electrode with polymetal structure of polycrystalline silicon film and metal film 有权
标题翻译：具有多晶硅膜和金属膜多金属结构的栅电极的半导体器件的制造方法
公开(公告)号：US06939787B2
公开(公告)日：2005-09-06
申请号：US10962504
申请日：2004-10-13
申请人： Fumio Ohtake , Yasushi Akasaka , Atsushi Murakoshi , Kyoichi Suguro
发明人： Fumio Ohtake , Yasushi Akasaka , Atsushi Murakoshi , Kyoichi Suguro
IPC分类号： H01L29/78 , H01L21/28 , H01L29/49 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/6656 , H01L21/28061 , H01L21/28247 , H01L29/4941
摘要： The semiconductor device comprises a pair of impurity diffused regions formed in a silicon substrate 10, spaced from each other, and a gate electrode 26 formed above the silicon substrate 10 between the pair of impurity diffused regions 38 intervening a gate insulation film 12 therebetween. The gate electrode 26 is formed of a polycrystalline silicon film 16 formed on the gate insulation film 12, a polycrystalline silicon film 30 formed on the polycrystalline silicon film 16 and having crystal grain boundaries discontinuous to the polycrystalline silicon film 16, a metal nitride film 20 formed on the polycrystalline silicon film 30, and a metal film 22 formed on the barrier metal film 20. Whereby diffusion of the boron from the first polycrystalline silicon film 16 toward the metal nitride film 20 can be decreased. Thus, depletion of the gate electrode 26 can be suppressed.
摘要翻译：半导体器件包括彼此间隔开的形成在硅衬底10中的一对杂质扩散区域，以及在栅极绝缘膜12之间形成的一对杂质扩散区域38之间形成在硅衬底10上方的栅电极26。栅电极26由形成在栅极绝缘膜12上的多晶硅膜16，形成在多晶硅膜16上并具有与多晶硅膜16不连续的晶粒边界的多晶硅膜30，金属氮化物膜20 形成在多晶硅膜30上，金属膜22形成在阻挡金属膜20上。由此可以减少硼从第一多晶硅膜16朝向金属氮化物膜20的扩散。因此，能够抑制栅电极26的耗尽。

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