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61. 发明授权

US06478688B1 Device and method for golf club face alignment 失效
标题翻译：高尔夫球杆面对齐的装置和方法
公开(公告)号：US06478688B1
公开(公告)日：2002-11-12
申请号：US09454207
申请日：1999-12-09
申请人： Masahiro Fukui
发明人： Masahiro Fukui
IPC分类号： A63B5304
CPC分类号： A63B69/3614 , A63B67/02 , A63B69/3676 , A63B2071/0694 , A63B2225/12
摘要： A facing direction confirming device for a head of a golf club to shoot a golf ball accurately in an intended direction, a method of forming an index of the facing direction of the club head. and a golf club having a club head with the index are disclosed. The confirming device includes a mat, a light source mounted on a first end of the mat for emitting a light beam, a reflecting mirror mounted on an opposite, second end for confining the direction of the light beam, a ball target interposed close to the light source between the light source and the reflecting mirror, and a transparent plate interposed between the light source and the ball target for detecting a light spot reflected from the reflecting mirror. The method of forming an index includes the steps of determining a reference light spot by a reference light on a transparent plate, addressing the head of the golf club on the end facing the reflecting mirror between the light source and the reflecting mirror, calculating a deviation angle to be made between the reference light and a reflected light, and forming an index on the club head for correcting the deviation angle. The golf club includes a club head having an index formed at a position of a crest of the head on the end opposite the face of the head and has an angular difference from the face line formed by the face.
摘要翻译：一种用于高尔夫球杆头部的朝向确认装置，用于在预期方向上精确地射出高尔夫球，形成球杆头的朝向方向的指标的方法。并且公开了具有该指标的球杆头的高尔夫球杆。确认装置包括垫，安装在垫的第一端上用于发射光束的光源，安装在相对的第二端用于限制光束的方向的反射镜，靠近光源和反射镜之间的光源，以及插入在光源和球目标之间的透明板，用于检测从反射镜反射的光点。形成索引的方法包括以下步骤：通过透明板上的参考光确定参考光点，在与光反射镜之间面对反射镜的一端上对高尔夫球杆的头部进行寻址，计算偏差在参考光和反射光之间形成角度，并且在球杆头上形成用于校正偏离角的折射率。高尔夫球杆包括具有形成在与头部相对的端部的头部的顶部的位置处的折痕的球杆头，并且与由面部形成的面线具有角度差。

62. 发明授权

US06292926B1 Functional module model, pipelined circuit synthesis and pipelined circuit device 失效
标题翻译：功能模块模型，流水线电路合成和流水线电路设备
公开(公告)号：US06292926B1
公开(公告)日：2001-09-18
申请号：US09109042
申请日：1998-07-02
申请人： Masahiro Fukui , Masakazu Tanaka , Toshiro Akino , Masaharu Imai , Yoshinori Takeuchi
发明人： Masahiro Fukui , Masakazu Tanaka , Toshiro Akino , Masaharu Imai , Yoshinori Takeuchi
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F7/5312 , G06F7/5443 , G06F2207/3884
摘要： The invention provides a functional module model for realizing optimal pipelining. The functional module model includes division line data representing division lines corresponding to positions where pipeline registers can be inserted and delay/area data representing the trade-off relationship between the delay and the area of each division area partitioned by the division lines. By using this functional module model, a pipeline register insertion position is selected among the division lines represented by the division line data, and the delay and the area of each division area are set on the basis of the trade-off relationship represented by the delay/area data. Thus, a pipelined circuit with a minimized area can be synthesized.
摘要翻译：本发明提供了一种实现最佳流水线功能的模块模型。功能模块模型包括表示对应于可以插入流水线寄存器的位置的分割线的分割线数据，以及表示延迟与由分割线划分的每个分割区域的区域之间的权衡关系的延迟/面积数据。通过使用该功能模块模型，在由分割线数据表示的分割线之间选择流水线寄存器插入位置，并且基于由延迟表示的权衡关系来设置每个划分区域的延迟和面积 /区域数据。因此，可以合成具有最小面积的流水线电路。

63. 发明授权

US5943486A Compaction method, compaction apparatus, routing method and routing apparatus 失效
标题翻译：压实方法，压实装置，路由方法和路由装置
公开(公告)号：US5943486A
公开(公告)日：1999-08-24
申请号：US752413
申请日：1996-11-19
申请人： Masahiro Fukui , Noriko Shinomiya
发明人： Masahiro Fukui , Noriko Shinomiya
IPC分类号： G06F17/50 , H01L21/98
CPC分类号： G06F17/5077 , G06F17/5081
摘要： Elements such as a transistor having a terminal corresponding to a wire junction are abstracted by using rectangles, and a spit penetrating these rectangles is introduced in a layout area where the rectangles are disposed. On the spit, a wire junction for allocating a wire is provided. The terminals of the rectangles corresponding to the wire junctions and the wire junctions on the spit are set as net targets, and connection information on these net targets is generated. A scan line for scanning the layout area from its left end to its right end and a front for tracing the net targets are introduced. While conducting rightward scanning by the scan line, the front is proceeded from one net target to the other net target. The trace of the front is provided as a wire element.
摘要翻译：通过使用矩形来抽出具有对应于线结的端子的晶体管的元件，并且在布置有矩形的布局区域中引入穿透这些矩形的吐丝。在吐痰中，提供用于分配电线的电线接头。对应于线路连接处的矩形端子和吐丝上的电线接头被设置为净目标，并且生成关于这些网络目标的连接信息。介绍了用于从左端到右端扫描布局区域的扫描线和用于跟踪网目标的前端。在扫描线进行向右扫描时，前方从一个净目标进入另一个目标。前面的痕迹作为线元件提供。

64. 发明授权

US5677249A Semiconductor apparatus and production method for the same 失效
标题翻译：半导体装置及其制作方法相同
公开(公告)号：US5677249A
公开(公告)日：1997-10-14
申请号：US670927
申请日：1996-06-26
申请人： Masahiro Fukui , Mizuki Segawa , Toshiro Akino , Michikazu Matsumoto
发明人： Masahiro Fukui , Mizuki Segawa , Toshiro Akino , Michikazu Matsumoto
IPC分类号： H01L23/522 , H01L21/28 , H01L21/336 , H01L21/768 , H01L21/82 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L27/118 , H01L29/78 , H01L21/265
CPC分类号： H01L21/28 , H01L27/11807
摘要： A gate wire is formed so as to extend from an active area to a separation, and an impurity diffused area is formed on each side of the gate electrode located on the active area. A contact member for connecting the gate wire to a first layer aluminum interconnection formed in an upper layer of the gate wire is in contact with the gate wire at a portion located on the active area. The utilization ratio of the active area is thus improved, and hence, the width of the separation can be minimized. In addition, by eliminating a mask alignment margin from the gate wire and suppressing the width of the gate wire not to exceed the width of the contact member, the occupied area of a semiconductor apparatus can be reduced.
摘要翻译：栅极线形成为从有源区域延伸到分离，并且在位于有源区域上的栅电极的每一侧上形成杂质扩散区域。用于将栅极线连接到形成在栅极线的上层中的第一层铝互连的接触构件在位于有源区上的部分处与栅极线接触。有效面积的利用率因此提高，因此可以使分离宽度最小化。此外，通过从栅极线去除掩模对准余量并且抑制栅极线的宽度不超过接触构件的宽度，可以减小半导体装置的占用面积。

65. 发明授权

US5602753A Method and apparatus for estimating power dissipation and method and apparatus of determining layout/routing 失效
标题翻译：估计功耗的方法和装置，确定布局/路由的方法和装置
公开(公告)号：US5602753A
公开(公告)日：1997-02-11
申请号：US423844
申请日：1995-04-18
申请人： Masahiro Fukui
发明人： Masahiro Fukui
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： This invention discloses a method of estimating power dissipation in an electrical circuit formed by a plurality of elements and a plurality of signal lines for input/output transfer. The probability that an output signal makes a transition in response to a change in an input signal is found. Based on this, a formula is found which expresses the output signal transition probability as a function of the input signal transition probability. This method has the following steps. An input signal transition probability is given. By making use of the formula, an output signal transition probability is found in relation to an input signal having the given signal transition probability. Estimation of power dissipation is performed by summing products obtained by multiplying each transition probability by each signal line's load. Computation of the signal transition probability starts at the input side. As a result of such arrangement, power dissipation can be estimated from each signal transition probability.
摘要翻译：本发明公开了一种估计由多个元件和用于输入/输出传输的多个信号线形成的电路中的功耗的方法。发现输出信号响应于输入信号的变化而转变的概率。基于此，找到表示作为输入信号转换概率的函数的输出信号转换概率的公式。该方法具有以下步骤。给出输入信号转换概率。通过使用公式，可以发现与具有给定信号转换概率的输入信号相关的输出信号转换概率。通过将每个转换概率乘以每个信号线的负载获得的乘积求和来执行功耗的估计。信号转换概率的计算从输入侧开始。作为这种布置的结果，可以从每个信号转换概率估计功率消耗。

66. 发明授权

US5062054A Layout pattern generation and geometric processing system for LSI circuits 失效
标题翻译： LSI电路布图图案生成和几何处理系统
公开(公告)号：US5062054A
公开(公告)日：1991-10-29
申请号：US322322
申请日：1989-03-10
申请人： Yoshiyuki Kawakami , Masahiro Fukui , Ichiro Shigemoto , Chie Iwasaki
发明人： Yoshiyuki Kawakami , Masahiro Fukui , Ichiro Shigemoto , Chie Iwasaki
IPC分类号： G06F17/50 , H05K3/00
CPC分类号： G06F17/5081 , H05K3/0005
摘要： A printed circuit layout system using two or more of the following sub-systems: a pattern processing subsystem, a pattern design rule check subsystem, and a pattern connectivity verification characterizes any circuit pattern by a set of rectangles, each rectangle identified by a potential number and a layer, number and coordinates, and identifies terminals by potential number, layer number, and terminal names. The system eliminates the need to perform pattern OR processing and electrical connectivity search, as required by conventional schemes. The reforming and checking processes for the layout patterns are executed by a simple high speed method, making use of the features of the layout data. The system includes efficient methods for notch elimination, design rule checking, and connectivity checking.
摘要翻译：使用以下子系统中的两个或更多个的印刷电路布局系统：图案处理子系统，图案设计规则检查子系统和图案连接验证通过一组矩形表征任何电路图案，每个矩形由潜在数字以及一个层，数字和坐标，并根据潜在的号码，层号和终端名称识别终端。该系统消除了按照常规方案的要求执行模式OR处理和电连接搜索的需要。通过简单的高速方法，利用布局数据的特征，执行布局图案的重整和检查过程。该系统包括有效的消除方法，设计规则检查和连通性检查。

67. 发明授权

US4875139A Building block LSI 失效
标题翻译：建筑块LSI
公开(公告)号：US4875139A
公开(公告)日：1989-10-17
申请号：US131006
申请日：1987-12-10
申请人： Masahiro Fukui
发明人： Masahiro Fukui
IPC分类号： H01L21/82 , H01L21/3205 , H01L23/52 , H01L25/065 , H01L25/18 , H01L27/02
CPC分类号： H01L25/18 , H01L25/0655 , H01L27/0207 , H01L2924/0002
摘要： A building block LSI includes a plurality of circuit blocks and an L-shaped channel formed between adjacent circuit blocks. The L-shaped channel extends in two directions at a first angle. A first set of wires is disposed in the L-shaped channel, extending in a direction parallel to the L-shaped channel. A second set of wires extends at a second angle from the circuit blocks into the L-shaped channel. The second angle is half that of the first angle. The two sets of wires are connected by through-holes such that the circuit blocks are interconnected electrically.
摘要翻译：构建块LSI包括形成在相邻电路块之间的多个电路块和L形沟道。 L形通道在第一角度沿两个方向延伸。第一组电线设置在L形通道中，沿与L形通道平行的方向延伸。第二组线从电路块以第二角度延伸到L形通道中。第二个角度是第一个角度的一半。两组电线通过通孔连接，使得电路块电连接。

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