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61. 发明授权

US09564448B2 Flash memory structure 有权
标题翻译：闪存结构
公开(公告)号：US09564448B2
公开(公告)日：2017-02-07
申请号：US14718171
申请日：2015-05-21
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Fu-Ting Sung , Chung-Chiang Min , Wei-Hang Huang , Shih-Chang Liu , Chia-Shiung Tsai
IPC分类号： H01L29/788 , H01L21/283 , H01L27/115 , H01L29/78 , H01L21/28 , H01L29/34 , H01L29/423 , H01L29/66 , H01L23/528 , H01L29/49
CPC分类号： H01L27/11568 , H01L21/28 , H01L21/28273 , H01L21/28282 , H01L21/76805 , H01L23/528 , H01L27/11521 , H01L29/34 , H01L29/42324 , H01L29/4234 , H01L29/4916 , H01L29/66825 , H01L29/7831 , H01L29/788 , H01L29/7881 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a control gate formed over the substrate. The semiconductor device structure further includes a memory gate formed over the substrate and a first spacer formed on a sidewall of the memory gate. The semiconductor device structure further includes a contact formed over the memory gate, wherein a portion of the contact extends into the first spacer.
摘要翻译：提供半导体器件结构。半导体器件结构包括衬底和形成在衬底上的控制栅极。半导体器件结构还包括形成在衬底上的存储器栅极和形成在存储器栅极的侧壁上的第一间隔物。半导体器件结构还包括形成在存储器栅极上的触点，其中触点的一部分延伸到第一间隔物中。

62. 发明申请

US20160336217A1 Method for Filling the Trenches of Shallow Trench Isolation (STI) Regions 有权
标题翻译：填充浅沟槽隔离（STI）区域的方法
公开(公告)号：US20160336217A1
公开(公告)日：2016-11-17
申请号：US14713425
申请日：2015-05-15
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yao-Wen Chang , Chia-Shiung Tsai , Cheng-Yuan Tsai
IPC分类号： H01L21/762 , H01L21/311 , H01L29/06 , H01L21/3115 , H01L21/265 , H01L21/02 , H01L21/3105
CPC分类号： H01L21/76224 , H01L21/02164 , H01L21/02321 , H01L21/02323 , H01L21/02337 , H01L21/02348 , H01L21/26586 , H01L21/31051 , H01L21/31111 , H01L21/31144 , H01L21/31155 , H01L21/6708 , H01L21/67115 , H01L29/0649
摘要： A method for manufacturing a shallow trench isolation (STI) region with a high aspect ratio is provided. A semiconductor substrate is provided with a trench. A first dielectric layer is formed lining the trench. A second dielectric layer is formed filling the trench over the first dielectric layer. In some embodiments, before forming the second dielectric layer, ions are implanted into an implant region of the first dielectric layer that extends along and is limited to a lower region of the trench. In alternative embodiments, after forming the second dielectric layer, an ultraviolet curing process is performed to the second dielectric layer. With the second dielectric layer formed and, in some embodiments, the ultraviolet curing process completed, an annealing process is performed to the second dielectric layer. A semiconductor structure for a STI region is also provided.
摘要翻译：提供了一种制造具有高纵横比的浅沟槽隔离（STI）区域的方法。半导体衬底设置有沟槽。在沟槽内形成第一介电层。形成第二电介质层，填充第一电介质层上的沟槽。在一些实施例中，在形成第二电介质层之前，将离子注入到第一电介质层的注入区域中，该注入区域沿着沟槽的下部区域延伸并且被限制在下部区域。在替代实施例中，在形成第二介电层之后，对第二电介质层进行紫外线固化处理。在形成第二电介质层的情况下，在一些实施方案中，紫外线固化过程完成，对第二电介质层进行退火处理。还提供了用于STI区域的半导体结构。

63. 发明申请

US20160318757A1 STRUCTURE TO REDUCE BACKSIDE SILICON DAMAGE 有权
标题翻译：结构减少背面的硅损坏
公开(公告)号：US20160318757A1
公开(公告)日：2016-11-03
申请号：US14699094
申请日：2015-04-29
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chung-Yen Chou , Chih-Jen Chan , Chia-Shiung Tsai , Ru-Liang Lee , Yuan-Chih Hsieh
IPC分类号： B81C1/00 , B81B7/00
CPC分类号： B81C1/00595 , B81B7/007 , B81B2201/0235 , B81B2201/0242 , B81B2201/0264 , B81B2201/0271 , B81B2201/0292 , B81B2203/0109 , B81C1/00357 , B81C1/00801 , B81C2201/0132
摘要： A method of forming an IC (integrated circuit) device is provided. The method includes receiving a first wafer including a first substrate and including a plasma-reflecting layer disposed on an upper surface thereof. The plasma-reflecting layer is configured to reflect a plasma therefrom. A dielectric protection layer is formed on a lower surface of a second wafer, wherein the second wafer includes a second substrate. The second wafer is bonded to the first wafer, such that a cavity is formed between the plasma-reflecting layer and the dielectric protection layer. An etch process is performed with the plasma to form an opening extending from an upper surface of the second wafer and through the dielectric protection layer into the cavity. A resulting structure of the above method is also provided.
摘要翻译：提供一种形成IC（集成电路）装置的方法。该方法包括接收包括第一基板的第一晶片，并且包括设置在其上表面上的等离子体反射层。等离子体反射层被配置为从其反射等离子体。介电保护层形成在第二晶片的下表面上，其中第二晶片包括第二基板。第二晶片被接合到第一晶片，使得在等离子体反射层和介电保护层之间形成空腔。用等离子体进行蚀刻工艺以形成从第二晶片的上表面延伸并通过介电保护层进入空腔的开口。还提供了上述方法的结果。

64. 发明授权

US09431609B2 Oxide film scheme for RRAM structure 有权
标题翻译： RRAM结构的氧化膜方案
公开(公告)号：US09431609B2
公开(公告)日：2016-08-30
申请号：US14459361
申请日：2014-08-14
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Trinh Hai Dang , Hsing-Lien Lin , Cheng-Yuan Tsai , Chia-Shiung Tsai , Ru-Liang Lee
IPC分类号： H01L21/00 , H01L45/00
CPC分类号： H01L45/1616 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： The present disclosure relates to a method of forming an RRAM cell having a dielectric data layer that provides good performance, device yield, and data retention, and an associated apparatus. In some embodiments, the method is performed by forming an RRAM film stack having a bottom electrode layer disposed over a semiconductor substrate, a top electrode layer, and a dielectric data storage layer disposed between the bottom electrode and the top electrode. The dielectric data storage layer has a performance enhancing layer with a hydrogen-doped oxide and a data retention layer having an aluminum oxide. The RRAM film stack is then patterned according to one or more masking layers to form a top electrode and a bottom electrode, and an upper metal interconnect layer is formed at a position electrically contacting the top electrode.
摘要翻译：本公开涉及一种形成具有提供良好性能，设备产量和数据保持的介质数据层的RRAM单元的方法以及相关联的设备。在一些实施例中，通过形成具有设置在半导体衬底上的底部电极层，顶部电极层和设置在底部电极和顶部电极之间的电介质数据存储层的RRAM膜堆栈来执行该方法。电介质数据存储层具有具有氢掺杂氧化物的性能增强层和具有氧化铝的数据保留层。然后根据一个或多个掩模层对RRAM膜堆叠进行构图以形成顶部电极和底部电极，并且在与顶部电极电接触的位置处形成上部金属互连层。

65. 发明申请

US20160111511A1 TRANSISTOR WITH PERFORMANCE BOOST BY EPITAXIAL LAYER 有权
标题翻译：具有通过外延层增强性能的晶体管
公开(公告)号：US20160111511A1
公开(公告)日：2016-04-21
申请号：US14980553
申请日：2015-12-28
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yu-Hung Cheng , Cheng-Ta Wu , Yeur-Luen Tu , Chia-Shiung Tsai , Ru-Liang Lee , Tung-I Lin , Wei-Li Chen
IPC分类号： H01L29/423 , H01L29/16 , H01L29/10 , H01L29/06
CPC分类号： H01L29/42364 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/02636 , H01L27/14614 , H01L27/14638 , H01L29/0649 , H01L29/0688 , H01L29/1037 , H01L29/105 , H01L29/1054 , H01L29/16 , H01L29/165 , H01L29/4236 , H01L29/66636 , H01L29/66651 , H01L29/66666 , H01L29/66795 , H01L29/785
摘要： The present disclosure relates to a transistor device. In some embodiments, the transistor device has an epitaxial layer disposed over a substrate. The epitaxial layer is arranged between a source region and a drain region separated along a first direction. Isolation structures are arranged on opposite sides of the epitaxial layer along a second direction, perpendicular to the first direction. A gate dielectric layer is disposed over the epitaxial layer, and a conductive gate electrode is disposed over the gate dielectric layer. The epitaxial layer overlying the substrate improves the surface roughness of the substrate, thereby improving transistor device performance.
摘要翻译：本公开涉及晶体管器件。在一些实施例中，晶体管器件具有设置在衬底上的外延层。外延层布置在沿着第一方向分离的源极区域和漏极区域之间。绝缘结构沿垂直于第一方向的第二方向布置在外延层的相对侧上。栅极电介质层设置在外延层上，并且导电栅电极设置在栅极介电层上。覆盖衬底的外延层改善了衬底的表面粗糙度，从而提高了晶体管器件的性能。

66. 发明授权

US09257498B1 Process to improve performance for metal-insulator-metal (MIM) capacitors 有权
标题翻译：提高金属绝缘体金属（MIM）电容器性能的工艺
公开(公告)号：US09257498B1
公开(公告)日：2016-02-09
申请号：US14450532
申请日：2014-08-04
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chern-Yow Hsu , Shih-Chang Liu , Ching-Sheng Chu , Chia-Shiung Tsai
IPC分类号： H01L27/108 , H01L29/94 , H01L49/02 , H01L21/3213 , H01L21/283 , H01L21/321
CPC分类号： H01L28/60 , H01L21/283 , H01L21/321 , H01L21/32133 , H01L28/90
摘要： Some embodiments relate to a metal-insulator-metal (MIM) capacitor, which includes a capacitor a capacitor bottom metal (CBM) electrode, a high k dielectric layer arranged over the CBM electrode, and a capacitor top metal (CTM) electrode arranged over the high k dielectric layer. In some embodiments, the MIM capacitor comprises CTM protective sidewall regions, which extend along vertical sidewall surfaces of the CTM electrode, and protect the CTM electrode from leakage, premature voltage breakdown, or burn out, due to metallic residue or etch damage formed on the sidewalls during one or more etch process(es) used to form the CTM electrode. In some embodiments, the MIM capacitor comprises CBM protective sidewall regions, which extend along vertical sidewall surfaces of the CBM electrode. In some embodiments, the MIM capacitor comprises both CBM and CTM protective sidewall regions.
摘要翻译：一些实施例涉及金属 - 绝缘体金属（MIM）电容器，其包括电容器底部电容（CBM）电极，布置在CBM电极上的高k电介质层和布置在电容器顶部金属（CTM）电极上的电容器顶部金属（CTM）电极）高k电介质层。在一些实施例中，MIM电容器包括沿着CTM电极的垂直侧壁表面延伸的CTM保护侧壁区域，并且由于金属残留物或蚀刻损伤上形成的金属残留物或蚀刻损伤而保护CTM电极免受泄漏，过早的电压击穿或烧坏在用于形成CTM电极的一个或多个蚀刻工艺期间的侧壁。在一些实施例中，MIM电容器包括沿着CBM电极的垂直侧壁表面延伸的CBM保护侧壁区域。在一些实施例中，MIM电容器包括CBM和CTM保护侧壁区域。

67. 发明申请

US20160035817A1 Process to Improve Performance for Metal-Insulator-Metal (MIM) Capacitors 有权
标题翻译：提高金属绝缘体（MIM）电容器性能的工艺
公开(公告)号：US20160035817A1
公开(公告)日：2016-02-04
申请号：US14450532
申请日：2014-08-04
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chern-Yow Hsu , Shih-Chang Liu , Ching-Sheng Chu , Chia-Shiung Tsai
IPC分类号： H01L49/02 , H01L21/283 , H01L21/321 , H01L21/3213
CPC分类号： H01L28/60 , H01L21/283 , H01L21/321 , H01L21/32133 , H01L28/90
摘要： Some embodiments relate to a metal-insulator-metal (MIM) capacitor, which includes a capacitor a capacitor bottom metal (CBM) electrode, a high k dielectric layer arranged over the CBM electrode, and a capacitor top metal (CTM) electrode arranged over the high k dielectric layer. In some embodiments, the MIM capacitor comprises CTM protective sidewall regions, which extend along vertical sidewall surfaces of the CTM electrode, and protect the CTM electrode from leakage, premature voltage breakdown, or burn out, due to metallic residue or etch damage formed on the sidewalls during one or more etch process(es) used to form the CTM electrode. In some embodiments, the MIM capacitor comprises CBM protective sidewall regions, which extend along vertical sidewall surfaces of the CBM electrode. In some embodiments, the MIM capacitor comprises both CBM and CTM protective sidewall regions.
摘要翻译：一些实施例涉及金属 - 绝缘体金属（MIM）电容器，其包括电容器底部电容（CBM）电极，布置在CBM电极上的高k电介质层和布置在电容器顶部金属（CTM）电极上的电容器顶部金属（CTM）电极）高k电介质层。在一些实施例中，MIM电容器包括沿着CTM电极的垂直侧壁表面延伸的CTM保护侧壁区域，并且由于金属残留物或蚀刻损伤上形成的金属残留物或蚀刻损伤而保护CTM电极免受泄漏，过早的电压击穿或烧坏在用于形成CTM电极的一个或多个蚀刻工艺期间的侧壁。在一些实施例中，MIM电容器包括沿着CBM电极的垂直侧壁表面延伸的CBM保护侧壁区域。在一些实施例中，MIM电容器包括CBM和CTM保护侧壁区域。

68. 发明授权

US09245974B2 Performance boost by silicon epitaxy 有权
标题翻译：硅外延的性能提升
公开(公告)号：US09245974B2
公开(公告)日：2016-01-26
申请号：US14187850
申请日：2014-02-24
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yu-Hung Cheng , Cheng-Ta Wu , Yeur-Luen Tu , Chia-Shiung Tsai , Ru-Liang Lee , Tung-I Lin , Wei-Li Chen
IPC分类号： H01L21/311 , H01L29/66
CPC分类号： H01L29/42364 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/02636 , H01L27/14614 , H01L27/14638 , H01L29/0649 , H01L29/0688 , H01L29/1037 , H01L29/105 , H01L29/1054 , H01L29/16 , H01L29/165 , H01L29/4236 , H01L29/66636 , H01L29/66651 , H01L29/66666 , H01L29/66795 , H01L29/785
摘要： The present disclosure relates to a method of generating a transistor device having an epitaxial layer disposed over a recessed active region. The epitaxial layer improves transistor device performance. In some embodiments, the method is performed by providing a semiconductor substrate. An epitaxial growth is performed to form an epitaxial layer onto the semiconductor substrate. An electrically insulating layer is then formed onto the epitaxial layer, and a gate structure is formed onto the electrically insulating layer. By forming the epitaxial layer over the semiconductor substrate the surface roughness of the semiconductor substrate is improved, thereby improving transistor device performance.
摘要翻译：本公开涉及一种生成具有设置在凹入的有源区上的外延层的晶体管器件的方法。外延层改善晶体管器件的性能。在一些实施例中，通过提供半导体衬底来执行该方法。进行外延生长以在半导体衬底上形成外延层。然后在外延层上形成电绝缘层，并且在电绝缘层上形成栅极结构。通过在半导体衬底上形成外延层，改善了半导体衬底的表面粗糙度，从而提高了晶体管器件的性能。

69. 发明申请

US20160020390A1 PROTECTIVE SIDEWALL TECHNIQUES FOR RRAM 有权
标题翻译： RRAM的保护性边界技术
公开(公告)号：US20160020390A1
公开(公告)日：2016-01-21
申请号：US14332577
申请日：2014-07-16
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yao-Wen Chang , Jian-Shiou Huang , Hsing-Lien Lin , Cheng-Yuan Tsai , Chia-Shiung Tsai
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/16
摘要： Some embodiments relate to a resistive random access memory (RRAM). The RRAM includes a RRAM bottom metal electrode, a variable resistance dielectric layer arranged over the RRAM bottom metal electrode, and a RRAM top metal electrode arranged over the variable resistance dielectric layer. A capping layer is arranged over the RRAM top metal electrode. A lower surface of the capping layer and an upper surface of the RRAM top metal electrode meet at an interface. Protective sidewalls are adjacent to outer sidewalls of the RRAM top metal electrode. The protective sidewalls have upper surfaces at least substantially aligned to the interface at which the upper surface of the RRAM top metal electrode meets the lower surface of the capping layer.
摘要翻译：一些实施例涉及电阻随机存取存储器（RRAM）。 RRAM包括RRAM底部金属电极，布置在RRAM底部金属电极上的可变电阻介电层和布置在可变电阻介电层上的RRAM顶部金属电极。在RRAM顶部金属电极上设置覆盖层。覆盖层的下表面和RRAM顶部金属电极的上表面在界面处相遇。保护侧壁与RRAM顶部金属电极的外侧壁相邻。保护侧壁的上表面至少基本上与RRAM顶部金属电极的上表面与覆盖层的下表面相接触的界面对齐。

70. 发明申请

US20150380477A1 MIM/RRAM Structure with Improved Capacitance and Reduced Leakage Current 有权
标题翻译：具有改善电容和降低泄漏电流的MIM / RRAM结构
公开(公告)号：US20150380477A1
公开(公告)日：2015-12-31
申请号：US14316910
申请日：2014-06-27
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Jian-Shiou Huang , Yao-Wen Chang , Hsing-Lien Lin , Cheng-Yuan Tsai , Chia-Shiung Tsai
IPC分类号： H01L49/02 , H01L21/02
CPC分类号： H01L28/40 , H01L21/02112 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02181 , H01L21/02266 , H01L23/5223 , H01L29/88 , H01L45/08 , H01L45/10
摘要： Some embodiments of the present disclosure provide an integrated circuit (IC) device including a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes a lower metal capacitor electrode, an upper metal capacitor electrode, and a capacitor dielectric separating the lower metal capacitor electrode from the upper metal capacitor electrode. The capacitor dielectric is made up of an amorphous oxide/nitride matrix and a plurality of metal or metal oxide/nitride nano-particles that are randomly distributed over the volume of amorphous oxide/nitride matrix.
摘要翻译：本公开的一些实施例提供了包括金属 - 绝缘体 - 金属（MIM）电容器结构的集成电路（IC）装置。 MIM电容器结构包括下金属电容器电极，上金属电容器电极和将下金属电容器电极与上金属电容器电极分离的电容器电介质。电容器电介质由无定形氧化物/氮化物基体和随机分布在无定形氧化物/氮化物基体的体积上的多个金属或金属氧化物/氮化物纳米颗粒构成。

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