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61. 发明授权

US06636313B2 Method of measuring photoresist and bump misalignment 有权
标题翻译：测量光刻胶和凸块未对准的方法
公开(公告)号：US06636313B2
公开(公告)日：2003-10-21
申请号：US10045413
申请日：2002-01-12
申请人： Yen-Ming Chen , Chia-Fu Lin , Kai-Ming Ching , Chao-Yuan Su , Hsin-Hui Lee , Li-Chih Chen
发明人： Yen-Ming Chen , Chia-Fu Lin , Kai-Ming Ching , Chao-Yuan Su , Hsin-Hui Lee , Li-Chih Chen
IPC分类号： G01B1100
CPC分类号： G03F7/70633 , G01B11/272 , H01L24/11 , H01L2224/0224 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05093 , H01L2224/05572 , H01L2924/14 , H01L2924/00
摘要： A method including the acts of providing a semiconductor device having a plurality of misalignment ruler markers formed therein for measuring removable layer opening misalignment in the X and Y directions, a bond pad and the passivation layer with an opening therein down to the bond pad. A removable layer is formed over the semiconductor device and includes an opening therein down to the bond pad. Preferably this action includes depositing, patterning and developing a dry photoresist film layer over the semiconductor device with an opening therein down to the bond pad. The next act includes measuring the misalignment of the opening in the passivation layer by counting the number of misalignment ruler markers visibly exposed by the opening in the X-direction and also the Y-direction.
摘要翻译：一种方法，包括提供半导体器件的动作，所述半导体器件具有形成在其中的多个不对准标尺标记，用于测量在X和Y方向上的可移除层开口未对准，接合焊盘和钝化层，其中开口向下到接合焊盘。可移除层形成在半导体器件上方并且包括其中向下到达接合焊盘的开口。优选地，该动作包括在半导体器件上沉积，图案化和显影干的光致抗蚀剂膜层，其中开口向下到接合焊盘。下一个动作包括通过计数由X方向和Y方向上的开口可见地露出的未对准标尺标记的数量来测量钝化层中的开口的未对准。

62. 发明申请

US20160313746A1 Proactive Pressure Stabilizing System and Method 有权
标题翻译：主动压力稳定系统和方法
公开(公告)号：US20160313746A1
公开(公告)日：2016-10-27
申请号：US15101912
申请日：2015-07-16
申请人： Chunyu WU , Hsin-Hui LEE
发明人： Hsin-Hui Lee
IPC分类号： G05D16/20
CPC分类号： G05D16/2066 , F17D1/02 , F17D1/04 , F17D1/20 , F17D3/01
摘要： System and method for gas pressure stabilization. The system comprises a pressure stabilizer which is divided into a receiving chamber and a pressure chamber by a flexible membrane, a booster device, a gas divider, and a control driver that can sense movement of the flexible membrane and control the gas divider accordingly. A pressure pilot is used to set the desired pressure in the pressure chamber. The pressure of the receiving chamber will stabilize to be the same with that of the pressure chamber regardless of the gas flow change or gas pressure change at the gas source, or the pressure fluctuation in the downstream system. The gas passing the system can eventually be recycled to a recycling system in the downstream without harming the environment.
摘要翻译：气压稳定系统及方法。该系统包括压力稳定器，其通过柔性膜分为接收室和压力室，增压装置，气体分配器和控制驱动器，其可以感测柔性膜的运动并相应地控制气体分配器。使用压力导向器来设定压力室中的所需压力。接收室的压力将稳定为与压力室的压力相同，而与气源的气体流量变化或气体压力变化或下游系统中的压力波动无关。通过系统的气体最终可以循环利用到下游的回收系统，而不会影响环境。

63. 发明授权

US08497584B2 Method to improve bump reliability for flip chip device 有权
标题翻译：提高倒装芯片器件的突发可靠性的方法
公开(公告)号：US08497584B2
公开(公告)日：2013-07-30
申请号：US10810965
申请日：2004-03-26
申请人： Yen-Ming Chen , Chia-Fu Lin , Shun-Liang Hsu , Kai-Ming Ching , Hsin-Hui Lee , Chao-Yuan Su , Li-Chih Chen
发明人： Yen-Ming Chen , Chia-Fu Lin , Shun-Liang Hsu , Kai-Ming Ching , Hsin-Hui Lee , Chao-Yuan Su , Li-Chih Chen
IPC分类号： H01L23/48
CPC分类号： H01L24/13 , H01L24/11 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05171 , H01L2224/05572 , H01L2224/05644 , H01L2224/1147 , H01L2224/11472 , H01L2224/11912 , H01L2224/13006 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/15787 , H01L2924/30107 , H01L2924/351 , H01L2224/05552 , H01L2924/00 , H01L2924/00014
摘要： A new method is provided for the creation of a solder bump. Conventional methods are initially followed, creating a patterned layer of Under Bump Metal over the surface of a contact pad. A layer of photoresist is next deposited, this layer of photoresist is patterned and developed creating a resist mask having a T-shape opening aligned with the contact pad. This T-shaped opening is filled with a solder compound, creating a T-shaped layer of solder compound on the surface of the layer of UBM. The layer of photoresist is removed, exposing the created T-shaped layer of solder compound, further exposing the layer of UBM. The layer of UBM is etched using the T-shaped layer of solder compound as a mask. Reflow of the solder compound results in creating a solder ball.
摘要翻译：提供了一种创建焊料凸块的新方法。最初遵循常规方法，在接触垫的表面上形成凹凸金属图案层。随后沉积一层光致抗蚀剂，该光致抗蚀剂层被图案化和显影，产生具有与接触焊盘对准的T形开口的抗蚀剂掩模。该T形开口填充有焊料化合物，在UBM层的表面上形成T形焊料化合物层。去除光致抗蚀剂层，暴露所生成的T形焊料化合物层，进一步暴露UBM层。使用焊料化合物的T形层作为掩模蚀刻UBM层。焊料复合物的回流导致产生焊球。

64. 发明授权

US07256071B2 Underfilling efficiency by modifying the substrate design of flip chips 有权
标题翻译：通过修改倒装芯片的衬底设计，填充效率不足
公开(公告)号：US07256071B2
公开(公告)日：2007-08-14
申请号：US11420822
申请日：2006-05-30
申请人： Hsin-Hui Lee , Chao-Yuan Su
发明人： Hsin-Hui Lee , Chao-Yuan Su
IPC分类号： H01L21/00
CPC分类号： H01L21/563 , H01L23/13 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00
摘要： A substrate structure comprising a substrate; a solder mask is formed over the substrate; and a metal trace structure formed within the solder mask. The metal trace structure including a channel therein for the receipt of underfill. The metal trace structure further including a central portion with arms radiating outwardly therefrom, dividing the solder mask into separate areas. A method of underfilling a chip wherein a chip having a pattern of solder bumps formed on the underside of the chip is placed underside first onto the metal trace structure of the present invention. The solder bump pattern including openings over the metal trace structure. Underfill is introduced into the metal trace structure so that the underfill flows from the metal trace structure and between the solder bumps to underfill the chip.
摘要翻译：一种衬底结构，包括衬底; 在衬底上形成焊料掩模; 以及形成在焊接掩模内的金属迹线结构。金属迹线结构包括用于接收底部填充物的通道。金属轨迹结构还包括具有从其向外辐射的臂的中心部分，将焊接掩模分成不同的区域。一种底部填充芯片的方法，其中具有形成在芯片的下侧上的焊料凸块图案的芯片首先放置在本发明的金属迹线结构上。焊料凸块图案包括在金属迹线结构上的开口。底部填充物被引入到金属迹线结构中，使得底部填充物从金属迹线结构和焊料凸块之间流动，从而在芯片下面填充。

65. 发明授权

US07148560B2 IC chip package structure and underfill process 有权
标题翻译： IC芯片封装结构和底部填充工艺
公开(公告)号：US07148560B2
公开(公告)日：2006-12-12
申请号：US11043602
申请日：2005-01-25
申请人： Hsin-Hui Lee , Chien-Hsiun Lee
发明人： Hsin-Hui Lee , Chien-Hsiun Lee
IPC分类号： H01L23/495 , H01L23/48
CPC分类号： H01L21/563 , H01L24/29 , H01L2224/0554 , H01L2224/05567 , H01L2224/05573 , H01L2224/16225 , H01L2224/26175 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/83102 , H01L2224/92125 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01019 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01082 , H01L2924/14 , H01L2924/3025 , H01L2924/00 , H01L2924/3512 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A novel integrated circuit (IC) chip package structure and underfill process which reduces stress applied to corners of a flip chip in an IC package structure during the application of an adhesive material between the flip chip and a carrier substrate is disclosed. The process includes providing a dam structure on a carrier substrate; attaching solder bumps of an inverted flip chip to the carrier substrate; injecting an adhesive material between the flip chip and the carrier substrate at multiple injection points located along adjacent edges of the flip chip; and injecting a sealant material around the adhesive material. During application of the adhesive material and the sealant material to the IC package structure in the underfill process, the dam structure reduces stress applied to the corners of the flip chip. This prevents or at least reduces de-lamination of dielectric layers on the flip chip.
摘要翻译：公开了一种新颖的集成电路（IC）芯片封装结构和底部填充工艺，其在将倒装芯片和载体衬底之间的粘合剂材料应用期间减小施加于IC封装结构中的倒装芯片的拐角的应力。该方法包括在载体基底上提供坝结构; 将反向倒装芯片的焊料凸块连接到载体衬底; 在位于倒装芯片的相邻边缘的多个注入点处，在所述倒装芯片和所述载体基板之间注入粘合材料; 以及在粘合剂材料周围注入密封材料。在底部填充工艺中将粘合剂材料和密封剂材料施加到IC封装结构时，坝结构减小了施加到倒装芯片的角部的应力。这防止或至少减少倒装芯片上的介电层的去叠层。

66. 发明授权

US07134199B2 Fluxless bumping process 有权
标题翻译：无通风碰撞过程
公开(公告)号：US07134199B2
公开(公告)日：2006-11-14
申请号：US10170745
申请日：2002-06-13
申请人： Chao-Yuan Su , Chia-Fu Lin , Hsin-Hui Lee , Yen-Ming Chen , Kai-Ming Ching , Li-Chih Chen , Wen-Chang Kuo , Yue-Ying Jian
发明人： Chao-Yuan Su , Chia-Fu Lin , Hsin-Hui Lee , Yen-Ming Chen , Kai-Ming Ching , Li-Chih Chen , Wen-Chang Kuo , Yue-Ying Jian
IPC分类号： H01R9/00 , H05K3/00
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/1147 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2924/0001 , H01L2924/01006 , H01L2924/01013 , H01L2924/01016 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , Y10T29/49144 , Y10T29/49146 , Y10T29/49147 , Y10T29/49149 , Y10T29/49179 , H01L2924/00014 , H01L2924/00
摘要： A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4 and SF6, and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.
摘要翻译：一种方法，包括提供包括接合焊盘的半导体器件和覆盖在焊盘上的凸块下金属。在凸块下冶金上形成焊料结构，其中焊料结构包括包含氧化锡的外层。从CF 4和SF 6 6中的至少一个生成等离子体，并将焊料结构暴露于等离子体。加热焊料结构并对其进行冷却以在半导体器件上提供焊料凸块。

67. 发明授权

US07126225B2 Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling 有权
标题翻译：用于制造具有减少的分层和剥离的半导体晶片的装置和方法
公开(公告)号：US07126225B2
公开(公告)日：2006-10-24
申请号：US10675862
申请日：2003-09-30
申请人： Chao-Yuan Su , Pei-Haw Tsao , Hsin-Hui Lee , Chender Huang , Shang Y. Hou , Shin Puu Jeng , Hao-Yi Tsai , Chenming Hu
发明人： Chao-Yuan Su , Pei-Haw Tsao , Hsin-Hui Lee , Chender Huang , Shang Y. Hou , Shin Puu Jeng , Hao-Yi Tsai , Chenming Hu
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A multi-layered semiconductor structure with free areas limiting the placement of test keys. First and second scribe lines intersect to define one corner point of a die. The first and second scribe lines are part of the multilayered structure and at least one layer of the multi-layer structure is a low-k dielectric layer. Free area A1 is defined on the first scribe line and is defined by the equation A1=D1×S1, where D1 is the distance from the corner point of the die toward the main area of the die, and S1 is the width of the first scribe line. Free area AS is defined at the intersection of the first scribe line and the second scribe line adjacent the die and is defined by the equation AS=S1×S2, where S2 is the width of the second scribe line.
摘要翻译：具有限制测试键放置的自由区域的多层半导体结构。第一和第二划线相交以定义模具的一个角点。第一和第二划痕线是多层结构的一部分，多层结构的至少一层是低k电介质层。自由区域A 1 <1>在第一划线上被定义并且由等式1定义1 D 1 1 ，其中D <1> 是从模具的角点到模具的主要区域的距离，S 1是第一划线的宽度。在第一划线和与模具相邻的第二划线之间的交叉点处限定自由区域A＆S，并且由公式A S S = 其中S 2 <2>是第二划线的宽度。

68. 发明申请

US20060170114A1 Novel method for copper wafer wire bonding 审中-公开
标题翻译：铜晶片引线接合的新方法
公开(公告)号：US20060170114A1
公开(公告)日：2006-08-03
申请号：US11047060
申请日：2005-01-31
申请人： Chao-Yuan Su , Chen-Der Huang , Chien-Hsiun Lee , Hsin-Hui Lee
发明人： Chao-Yuan Su , Chen-Der Huang , Chien-Hsiun Lee , Hsin-Hui Lee
IPC分类号： H01L23/52
CPC分类号： H01L21/288 , H01L21/76843 , H01L21/7685 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/78 , H01L24/85 , H01L2224/02166 , H01L2224/04042 , H01L2224/05022 , H01L2224/05073 , H01L2224/05571 , H01L2224/05647 , H01L2224/05655 , H01L2224/45015 , H01L2224/45144 , H01L2224/484 , H01L2224/48647 , H01L2224/48655 , H01L2224/78301 , H01L2224/85375 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/05042 , H01L2924/20752 , H01L2924/20753 , H01L2924/00014 , H01L2924/01024 , H01L2924/00 , H01L2224/05552
摘要： A method of bonding a conductive wire on copper pad is presented. A passivation layer is formed on a copper pad. The passivation layer has an opening through which at least a portion of the copper pad is exposed. A nickel-copper-phosphorous (Ni—Cu—P) layer is formed on the copper pad by electroless plating. A conductive wire is bonded through the Ni—Cu—P layer and to the copper pad. The Ni—Cu—P layer protects the underline copper pads from oxidation so that a better bonding can be formed between the conductive wire and the copper pad.
摘要翻译：提出了一种将导线接合在铜垫上的方法。钝化层形成在铜垫上。钝化层具有开口，至少一部分铜焊盘露出。通过化学镀在铜焊盘上形成镍 - 铜 - 磷（Ni-Cu-P）层。导线通过Ni-Cu-P层和铜垫结合。 Ni-Cu-P层保护底线铜焊盘不被氧化，从而可以在导线和铜焊盘之间形成更好的接合。

69. 发明申请

US20060163749A1 IC chip package structure and underfill process 有权
公开(公告)号：US20060163749A1
公开(公告)日：2006-07-27
申请号：US11043602
申请日：2005-01-25
申请人： Hsin-Hui Lee , Chien-Hsiun Lee
发明人： Hsin-Hui Lee , Chien-Hsiun Lee
IPC分类号： H01L23/48
CPC分类号： H01L21/563 , H01L24/29 , H01L2224/0554 , H01L2224/05567 , H01L2224/05573 , H01L2224/16225 , H01L2224/26175 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/83102 , H01L2224/92125 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01019 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01082 , H01L2924/14 , H01L2924/3025 , H01L2924/00 , H01L2924/3512 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A novel integrated circuit (IC) chip package structure and underfill process which reduces stress applied to corners of a flip chip in an IC package structure during the application of an adhesive material between the flip chip and a carrier substrate is disclosed. The process includes providing a dam structure on a carrier substrate; attaching solder bumps of an inverted flip chip to the carrier substrate; injecting an adhesive material between the flip chip and the carrier substrate at multiple injection points located along adjacent edges of the flip chip; and injecting a sealant material around the adhesive material. During application of the adhesive material and the sealant material to the IC package structure in the underfill process, the dam structure reduces stress applied to the corners of the flip chip. This prevents or at least reduces de-lamination of dielectric layers on the flip chip.

70. 发明申请

US20060091562A1 Flip chip BGA process and package with stiffener ring 审中-公开
标题翻译：倒装芯片BGA工艺和带加强环的封装
公开(公告)号：US20060091562A1
公开(公告)日：2006-05-04
申请号：US10978008
申请日：2004-10-29
申请人： Hsin-Hui Lee
发明人： Hsin-Hui Lee
IPC分类号： H01L23/48
CPC分类号： H01L23/3675 , H01L23/49816 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2924/00011 , H01L2924/00014 , H01L2924/15311 , H01L2924/00012 , H01L2924/00 , H01L2224/0401
摘要： An assembly comprises a substrate, a ring structure bonded to a first side of the substrate; and a die flip-chip-bonded to a second side of the substrate opposite the first side.
摘要翻译：组件包括基底，结合到基底的第一侧的环形结构; 以及与所述基板的与所述第一侧相反的第二侧倒装芯片的芯片。

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