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61. 发明申请

US20090219657A1 Trenched mosfets with improved gate-drain (GD) clamp diodes 失效
标题翻译：具有改进的栅极 - 漏极（GD）钳位二极管的沟槽MOSFET
公开(公告)号：US20090219657A1
公开(公告)日：2009-09-03
申请号：US12383247
申请日：2009-03-19
申请人： Fwu-Iuan Hshieh
发明人： Fwu-Iuan Hshieh
IPC分类号： H02H9/00
CPC分类号： H01L27/0814 , H01L27/0255 , H01L27/0629
摘要： A method for operating a semiconductor power device by in a forward conducting mode instead of an avalanche mode during a voltage fly-back during an inductive switch operation for absorbing a transient energy with less stress. The method includes a step of clamping the semiconductor power device with a Zener diode connected between a gate metal and a drain metal of the semiconductor power device to function as a gate-drain (GD) clamp diode with the GD clamp diode having an avalanche voltage lower than a source/drain avalanche voltage of the semiconductor power device whereby as the voltage fly-back inducing a drain voltage increase rapidly reaching the avalanche voltage of the GD clamp diode for generating the forward conducting mode.
摘要翻译：一种用于在感应开关操作期间在电压回扫期间以正向传导模式而不是雪崩模式操作半导体功率器件的方法，用于以较小的应力吸收瞬态能量。该方法包括用连接在半导体功率器件的栅极金属和漏极金属之间的齐纳二极管钳位半导体功率器件的步骤，用作具有雪崩电压的GD钳位二极管的栅极 - 漏极（GD）钳位二极管低于半导体功率器件的源极/漏极雪崩电压，由此当感应漏极电压的电压反复迅速增加达到GD钳位二极管的雪崩电压以产生正向导通模式时。

62. 发明申请

US20080303081A1 Device configuration and method to manufacture trench mosfet with solderable front metal 失效
标题翻译：具有可焊接前金属制造沟槽MOSFET的器件配置和方法
公开(公告)号：US20080303081A1
公开(公告)日：2008-12-11
申请号：US11810327
申请日：2007-06-05
申请人： Fwu-Iuan Hshieh
发明人： Fwu-Iuan Hshieh
IPC分类号： H01L29/78 , H01L21/02
CPC分类号： H01L29/7811 , H01L21/743 , H01L24/05 , H01L24/06 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/91 , H01L29/456 , H01L29/4941 , H01L29/66727 , H01L29/66734 , H01L29/7813 , H01L2224/0347 , H01L2224/04042 , H01L2224/05082 , H01L2224/05166 , H01L2224/05184 , H01L2224/05187 , H01L2224/05624 , H01L2224/05647 , H01L2224/0603 , H01L2224/37147 , H01L2224/40245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48247 , H01L2224/4847 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/48847 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49175 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01059 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/30105 , H01L2924/00014 , H01L2924/01007 , H01L2924/04941 , H01L2924/04953 , H01L2924/00 , H01L2224/48824
摘要： A vertical semiconductor power device includes a plurality of semiconductor power cells connected to a bottom electric terminal disposed on a bottom surface of a semiconductor substrate and at least a top electrical terminal disposed on a top surface of the substrate and connected to the semiconductor power cells. The top electrical terminal further includes a solderable front metal for soldering to a conductor for providing an electric connection therefrom. In an exemplary embodiment, the conductor soldering to the solderable front metal includes a conductor of a high-heat-conductivity metal plate. In another exemplary embodiment, the conductor soldering to the solderable front metal includes a copper plate. In another exemplary embodiment, the solderable front metal includes a Ti/Ni/Au front metal. In another exemplary embodiment, the solderable front metal includes a Ti/Ni/Ag front metal.
摘要翻译：垂直半导体功率器件包括连接到设置在半导体衬底的底表面上的底部电端子和至少设置在衬底的顶表面上并连接到半导体功率单元的顶部电气端子的多个半导体功率单元。顶部电气端子还包括用于焊接到导体的可焊接前金属，用于从其提供电连接。在示例性实施例中，焊接到可焊接前金属的导体包括高导热性金属板的导体。在另一示例性实施例中，焊接到可焊接前金属的导体包括铜板。在另一示例性实施例中，可焊接前金属包括Ti / Ni / Au前金属。在另一示例性实施例中，可焊接的前金属包括Ti / Ni / Ag前金属。

63. 发明申请

US20080290442A1 PROCESS FOR HIGH VOLTAGE SUPERJUNCTION TERMINATION 审中-公开
公开(公告)号：US20080290442A1
公开(公告)日：2008-11-27
申请号：US12104131
申请日：2008-04-16
申请人： Fwu-Iuan Hshieh , Brian D. Pratt
发明人： Fwu-Iuan Hshieh , Brian D. Pratt
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L29/66712 , H01L21/26586 , H01L21/76251 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.

64. 发明申请

US20080258224A1 Trenched MOSFETs with improved gate-drain (GD) clamp diodes 失效
标题翻译：具有改进的栅极 - 漏极（GD）钳位二极管的沟槽MOSFET
公开(公告)号：US20080258224A1
公开(公告)日：2008-10-23
申请号：US11788497
申请日：2007-04-20
申请人： Fwu-Iuan Hshieh
发明人： Fwu-Iuan Hshieh
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L27/0814 , H01L27/0255 , H01L27/0629
摘要： A MOSFET device that includes a first Zener diode connected between a gate metal and a drain metal of said semiconductor power device for functioning as a gate-drain (GD) clamp diode. The GD clamp diode includes multiple back-to-back doped regions in a polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on an insulation layer above the MOSFET device, having an avalanche voltage lower than a source/drain avalanche voltage of the MOSFET device wherein the Zener diode is insulated from a doped region of the MOSFET device for preventing a channeling effect. The MOSFET device further includes a second Zener diode connected between a gate metal and a source metal of the MOSFET device for functioning as a gate-source (GS) clamp diode, wherein the GD clamp diode includes multiple back-to-back doped regions in the polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on the insulation layer above the MOSFET device having a lower breakdown voltage than a gate oxide rupture voltage of the MOSFET device.
摘要翻译： MOSFET器件，其包括连接在所述半导体功率器件的栅极金属和漏极金属之间的第一齐纳二极管，用作栅极 - 漏极（GD）钳位二极管。 GD钳位二极管包括在掺杂有第一导电类型的掺杂剂离子的多个背对背掺杂区域中，该第一导电类型的掺杂离子位于设置在MOSFET器件上方的绝缘层上的第二导电类型，具有低于源极的雪崩电压 /漏极雪崩电压，其中齐纳二极管与MOSFET器件的掺杂区域绝缘，以防止沟道效应。 MOSFET器件还包括连接在MOSFET器件的栅极金属和源极金属之间的第二齐纳二极管，用作栅极源（GS）钳位二极管，其中GD钳位二极管包括多个背对背掺杂区域掺杂有第一导电类型的掺杂剂离子的多晶硅层设置在具有比MOSFET器件的栅极氧化物破裂电压低的击穿电压的MOSFET器件上方的绝缘层上的第二导电类型。

65. 发明授权

US07439583B2 Tungsten plug drain extension 失效
标题翻译：钨插头排水延长
公开(公告)号：US07439583B2
公开(公告)日：2008-10-21
申请号：US11318988
申请日：2005-12-27
申请人： Fwu-Iuan Hshieh
发明人： Fwu-Iuan Hshieh
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L29/04 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/0878 , H01L29/41 , H01L29/42368 , H01L29/4925 , H01L29/7811 , H01L29/7813
摘要： A power metal-oxide-semiconductor field effect transistor (MOSFET) cell includes a semiconductor substrate. A first electrode is disposed on the semiconductor substrate. A voltage sustaining layer is formed on the semiconductor substrate. A highly doped active zone of a first conductivity type is formed in the voltage sustaining layer opposite the semiconductor substrate. The highly doped active zone has a central aperture and a channel region that is generally centrally located within the central aperture. A terminal region of the second conductivity type is disposed in the voltage sustaining layer proximate the highly doped active zone. The terminal region has a central aperture with an opening dimension generally greater than an opening dimension of the central aperture of the highly doped zone. An extension region is disposed in the voltage sustaining region within the central aperture of the highly doped active zone.
摘要翻译：功率金属氧化物半导体场效应晶体管（MOSFET）单元包括半导体衬底。第一电极设置在半导体衬底上。在半导体衬底上形成电压维持层。在与半导体衬底相对的电压维持层中形成第一导电类型的高掺杂有源区。高度掺杂的有源区具有中心孔和通常位于中心孔内的通道区。第二导电类型的端子区域设置在靠近高掺杂活性区的电压维持层中。端子区具有中心孔，开口尺寸通常大于高掺杂区的中心孔的开口尺寸。延伸区域设置在高掺杂活性区域的中心孔内的电压维持区域中。

66. 发明申请

US20070238251A1 Method of forming sub-100nm narrow trenches in semiconductor substrates 审中-公开
标题翻译：在半导体衬底中形成亚100nm窄沟槽的方法
公开(公告)号：US20070238251A1
公开(公告)日：2007-10-11
申请号：US11399046
申请日：2006-04-05
申请人： Chu Liau , Patsda Ai Liew , Fwu-Iuan Hshieh
发明人： Chu Liau , Patsda Ai Liew , Fwu-Iuan Hshieh
IPC分类号： H01L21/336
CPC分类号： H01L29/66704 , H01L29/66689
摘要： A method to form a narrow trench within a semiconductor substrate includes exemplary steps of: (a) A CVD layer such as SiO2 represented as “CVD1” is deposited on top of a semiconductor surface followed by a different type of CVD layer such as SiON or Si3N4 (represented by “CVD2” deposited on top of “CVD1”. (b) A 0.2 um trench is formed by partially etching a trench in the CVD deposited layers with a substantial “CVD1” thickness left in order to act as a hard mask layer in the later stage. (c) A thin layer of polysilicon is then deposited in the trench such that the polysilicon covers conformally on the trench wall, trench bottom and on top of the “CVD2” layer. (d) The polysilicon at the trench bottom is then blanket etched to expose the “CVD1” substrate again. (e) The remaining “CVD1” substrate, which is exposed now at the trench bottom, will go through a “CVD1” etching process with good selectivity to Polysilicon and “CVD2” in order to expose the semiconductor substrate at trench bottom. (f) The narrow “CVD1” trench, which is now formed, will go through another etching process to etch the semiconductor substrate with the narrow “CVD1” trench acting as a hard mask. In preferred embodiments, the method of the present invention is used to manufacture trenched MOSFET device.
摘要翻译：在半导体衬底内形成窄沟槽的方法包括以下示例性步骤：（a）将表示为“CVD1”的诸如SiO 2的CVD层沉积在半导体表面之上，随后是不同的类型的CVD层，例如SiON或Si 3 N 4（由“CVD1”顶部沉积的“CVD2”表示）（b）0.2μm沟槽由部分蚀刻留下了大量“CVD1”厚度的CVD沉积层中的沟槽，以便在后期阶段充当硬掩模层。（c）然后在沟槽中沉积薄层多晶硅，使得多晶硅覆盖（d）沟槽底部的多晶硅然后进行全面蚀刻以再次暴露“CVD1”衬底;（e）剩余的“CVD1”衬底，它现在在沟槽底部暴露，将通过“CVD1”蚀刻工艺，对多晶硅和“CVD2”具有良好的选择性，以暴露半导体沟槽底部的电感基板。（f）现在形成的窄的“CVD1”沟槽将经过另一蚀刻工艺以用作为硬掩模的窄“CVD1”沟槽蚀刻半导体衬底。在优选实施例中，本发明的方法用于制造沟槽MOSFET器件。

67. 发明申请

US20060231915A1 Process for high voltage superjunction termination 失效
公开(公告)号：US20060231915A1
公开(公告)日：2006-10-19
申请号：US11318873
申请日：2005-12-27
申请人： Fwu-Iuan Hshieh , Brian Pratt
发明人： Fwu-Iuan Hshieh , Brian Pratt
IPC分类号： H01L23/58
CPC分类号： H01L29/66712 , H01L21/26586 , H01L21/76251 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.

68. 发明授权

US07109110B2 Method of manufacturing a superjunction device 失效
标题翻译：制造超结装置的方法
公开(公告)号：US07109110B2
公开(公告)日：2006-09-19
申请号：US11015519
申请日：2004-12-17
申请人： Fwu-Iuan Hshieh
发明人： Fwu-Iuan Hshieh
IPC分类号： H01L29/06
CPC分类号： H01L29/66712 , H01L21/266 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/7811
摘要： A partially manufactured semiconductor device includes a semiconductor substrate. The device includes a first oxide layer formed on the substrate, with a mask placed over the oxide-covered substrate, a plurality of first trenches and at least one second trench etched through the oxide layer forming mesas. The at least one second trench is deeper and wider than each of the first trenches. The device includes a second oxide layer that is disposed over an area of mesas and the plurality of first trenches. The device includes a layer of masking material that is deposited over a an area of an edge termination region adjacent to an active region. The area of mesas and first trenches not covered by the masking layer is etched to remove the oxidant seal. The device includes an overhang area that is formed by a wet process etch.
摘要翻译：部分制造的半导体器件包括半导体衬底。该器件包括形成在衬底上的第一氧化物层，掩模放置在氧化物覆盖的衬底上，多个第一沟槽和至少一个第二沟槽，蚀刻通过形成台面的氧化物层。所述至少一个第二沟槽比每个所述第一沟槽更深和更宽。该装置包括设置在台面的区域和多个第一沟槽上的第二氧化物层。该器件包括一层掩模材料，其被沉积在邻近有源区域的边缘终端区域的一个区域上。蚀刻没有被掩蔽层覆盖的台面和第一沟槽的区域以除去氧化剂密封。该装置包括通过湿法蚀刻形成的悬垂区域。

69. 发明授权

US07019360B2 High voltage power mosfet having a voltage sustaining region that includes doped columns formed by trench etching using an etchant gas that is also a doping source 失效
标题翻译：具有电压维持区域的高压电源MOSFET包括使用也是掺杂源的蚀刻剂气体通过沟槽蚀刻形成的掺杂色谱柱
公开(公告)号：US07019360B2
公开(公告)日：2006-03-28
申请号：US10784516
申请日：2004-02-23
申请人： Richard A. Blanchard , Fwu-Iuan Hshieh
发明人： Richard A. Blanchard , Fwu-Iuan Hshieh
IPC分类号： H01L21/336
CPC分类号： H01L29/7802 , H01L21/223 , H01L29/0634 , H01L29/0649 , H01L29/66712
摘要： A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. At least one doped column having a dopant of a second conductivity type is located in the epitaxial layer, adjacent a sidewall of the trench. The trench is etched using an etchant gas that also serves as a dopant source for the formation of the doped column. For example, if a p-type dopant such as boron is desired, BCl3 may be used as the etchant gas. Alternatively, if an n-type dopant such as phosphorus is required, PH3 may be used as the etchant gas. The dopant present in the gas is incorporated into the silicon defining the surfaces of the trench. This dopant is subsequently diffused to form the doped column surrounding the trench. The trench is filled with an insulating material such as silicon dioxide, silicon nitride, polysilicon, or a combination of such materials. The step of filling the trench may be performed before or after the dopant is diffused to form the doped column. Finally, at least one region of the second conductivity type is formed over the voltage sustaining region to define a junction therebetween.
摘要翻译：提供了形成功率半导体器件的方法。该方法开始于提供第一导电类型的衬底，然后在衬底上形成电压维持区域。通过在衬底上沉积第一导电类型的外延层并在外延层中形成至少一个沟槽来形成电压维持区。具有第二导电类型的掺杂剂的至少一个掺杂的柱位于沟槽的侧壁附近的外延层中。使用也用作形成掺杂柱的掺杂剂源的蚀刻剂气体蚀刻沟槽。例如，如果需要诸如硼的p型掺杂剂，则可以使用BCl 3作为蚀刻剂气体。或者，如果需要诸如磷的n型掺杂剂，则可以使用PH 3作为蚀刻剂气体。存在于气体中的掺杂剂被结合到限定沟槽表面的硅中。随后该掺杂剂扩散以形成围绕沟槽的掺杂柱。沟槽填充有诸如二氧化硅，氮化硅，多晶硅或这些材料的组合的绝缘材料。可以在掺杂剂扩散之前或之后进行填充沟槽的步骤以形成掺杂的柱。最后，在电压维持区域上形成第二导电类型的至少一个区域以限定它们之间的接合。

70. 发明授权

US06979621B2 Trench MOSFET having low gate charge 有权
标题翻译：沟槽MOSFET栅极电荷低
公开(公告)号：US06979621B2
公开(公告)日：2005-12-27
申请号：US10751687
申请日：2004-01-05
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/51 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/28185 , H01L21/28194 , H01L29/42368 , H01L29/4925 , H01L29/4933 , H01L29/511 , H01L29/513
摘要： A trench MOSFET device comprising: (a) a silicon substrate of a first conductivity type (preferably N-type conductivity); (b) a silicon epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a body region of a second conductivity type (preferably P-type conductivity) within an upper portion of the epitaxial layer; (d) a trench having trench sidewalls and a trench bottom, which extends into the epitaxial layer from an upper surface of the epitaxial layer and through the body region of the device; (f) an oxide region lining the trench, which comprises a lower segment covering at least the trench bottom and upper segments covering at least upper regions of the trench sidewalls; (g) a conductive region within the trench adjacent the oxide region; and (h) a source region of the first conductivity type within an upper portion of the body region and adjacent the trench. The lower segment of the oxide region is thicker than the upper segments of the oxide region in this embodiment.
摘要翻译：一种沟槽MOSFET器件，包括：（a）第一导电类型（优选N型导电性）的硅衬底; （b）在衬底上的第一导电类型的硅外延层，所述外延层具有比衬底更低的载流子浓度; （c）在所述外延层的上部内具有第二导电类型（优选P型导电性）的体区; （d）具有沟槽侧壁和沟槽底部的沟槽，其从外延层的上表面延伸到外延层并穿过器件的本体区域; （f）衬在所述沟槽上的氧化物区域，其包括覆盖至少所述沟槽底部的下部段和覆盖所述沟槽侧壁的至少上部区域的上段; （g）邻近氧化物区域的沟槽内的导电区域; 和（h）第一导电类型的源极区域，位于主体区域的上部并且与沟槽相邻。在本实施例中，氧化物区域的下段比氧化物区域的上部段更厚。

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