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61. 发明授权

US08344367B2 Molecular devices and methods of manufacturing the same 有权
标题翻译：分子装置及其制造方法
公开(公告)号：US08344367B2
公开(公告)日：2013-01-01
申请号：US12929118
申请日：2011-01-03
申请人： Dong-Won Kim , Dong-Gun Park , Sung-Young Lee , Yang-Kyu Choi , Lee-Eun Yu
发明人： Dong-Won Kim , Dong-Gun Park , Sung-Young Lee , Yang-Kyu Choi , Lee-Eun Yu
IPC分类号： H01L29/08
CPC分类号： H01L51/0595 , B82Y10/00 , G11C13/0014 , H01L51/102 , Y10T428/24
摘要： Molecular devices and methods of manufacturing the molecular device are provided. The molecular device may include a lower electrode on a substrate and a self-assembled monolayer on the lower electrode. After an upper electrode is formed on the self-assembled monolayer, the self-assembled monolayer may be removed to form a gap between the lower electrode and the upper electrode. A functional molecule having a functional group may be injected into the gap.
摘要翻译：提供了制造分子装置的分子装置和方法。分子器件可以包括在基底上的下电极和下电极上的自组装单层。在自组装单层上形成上电极之后，可以去除自组装单层以在下电极和上电极之间形成间隙。可以将具有官能团的功能性分子注入到间隙中。

62. 发明申请

US20050224889A1 Surrounded-channel transistors with directionally etched gate or insulator formation regions and methods of fabrication therefor 有权
标题翻译：具有定向蚀刻的栅极或绝缘体形成区域的周围通道晶体管及其制造方法
公开(公告)号：US20050224889A1
公开(公告)日：2005-10-13
申请号：US11095969
申请日：2005-03-31
申请人： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Sung-Young Lee
发明人： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Sung-Young Lee
IPC分类号： H01L21/336 , H01L29/423 , H01L29/76 , H01L29/786
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/42392 , H01L29/66545 , H01L29/66795 , H01L29/78645 , Y10S438/924
摘要： An elongate stacked semiconductor structure is formed on a substrate. The stacked semiconductor structure includes a second semiconductor material region disposed on a first semiconductor material region. The first semiconductor material region is selectively doped to produce spaced-apart impurity-doped first semiconductor material regions and a lower dopant concentration first semiconductor material region therebetween. Etching exposes a portion of the second semiconductor material region between the impurity-doped first semiconductor material regions. The etching removes at least a portion of the lower dopant concentration first semiconductor material region to form a hollow between the substrate and the portion of the second semiconductor material region between the impurity-doped first semiconductor material regions. An insulation layer that surrounds the exposed portion of the second semiconductor material region between the impurity-doped first semiconductor material regions is formed. The hollow may be filled with a gate electrode that completely surrounds the exposed portion of the second semiconductor material region, or the gate electrode may partially surround the exposed portion of the second semiconductor material region and an insulation region may be formed in the hollow.
摘要翻译：在衬底上形成细长的堆叠半导体结构。层叠的半导体结构包括设置在第一半导体材料区域上的第二半导体材料区域。第一半导体材料区域被选择性地掺杂以产生间隔杂质掺杂的第一半导体材料区域和其间的较低掺杂浓度的第一半导体材料区域。蚀刻使杂质掺杂的第一半导体材料区域之间的第二半导体材料区域的一部分暴露。蚀刻去除下掺杂剂浓度的第一半导体材料区域的至少一部分，以在衬底与掺杂杂质的第一半导体材料区域之间的第二半导体材料区域的部分之间形成中空。形成了在杂质掺杂的第一半导体材料区域之间围绕第二半导体材料区域的暴露部分的绝缘层。中空部可以填充有完全围绕第二半导体材料区域的暴露部分的栅电极，或者栅电极可以部分地围绕第二半导体材料区域的暴露部分，并且可以在中空部中形成绝缘区域。

63. 发明授权

US08211322B2 Method of forming a metal layer pattern having a nanogap and method of manufacturing a molecule-sized device using the same 有权
标题翻译：形成具有纳米凹槽的金属层图案的方法和使用其制造分子尺寸的装置的方法
公开(公告)号：US08211322B2
公开(公告)日：2012-07-03
申请号：US12149388
申请日：2008-04-30
申请人： Dong-Gun Park , Dong-Won Kim , Sung-Young Lee , Yang-Kyu Choi , Chang-Hoon Kim , Ju-Hyun Kim
发明人： Dong-Gun Park , Dong-Won Kim , Sung-Young Lee , Yang-Kyu Choi , Chang-Hoon Kim , Ju-Hyun Kim
IPC分类号： C23F1/00
CPC分类号： H01L21/32131 , H01L29/0649 , H01L29/78 , Y10T428/11
摘要： A method of patterning a metal layer includes forming a first mask on a surface of the metal layer, the first mask having an opening through the first mask that exposes the metal layer, and forming a nanogap in the exposed metal layer using an ion beam directed through the opening. The first mask limits a lateral extent of the ion beam, and the nanogap has a width that is less than a width of the opening.
摘要翻译：图案化金属层的方法包括在金属层的表面上形成第一掩模，第一掩模具有通过暴露金属层的第一掩模的开口，并且在暴露的金属层中使用定向的离子束形成纳米隙通过开放。第一掩模限制离子束的横向范围，并且纳米隙具有小于开口宽度的宽度。

64. 发明申请

US20080193705A1 Molecular devices and methods of manufacturing the same 有权
标题翻译：分子装置及其制造方法
公开(公告)号：US20080193705A1
公开(公告)日：2008-08-14
申请号：US12068765
申请日：2008-02-12
申请人： Dong-Won Kim , Dong-Gun Park , Sung-Young Lee , Yang-Kyu Choi , Lee-Eun Yu
发明人： Dong-Won Kim , Dong-Gun Park , Sung-Young Lee , Yang-Kyu Choi , Lee-Eun Yu
IPC分类号： B32B5/00 , B05D5/12
CPC分类号： H01L51/0595 , B82Y10/00 , G11C13/0014 , H01L51/102 , Y10T428/24
摘要： Molecular devices and methods of manufacturing the molecular device are provided. The molecular device may include a lower electrode on a substrate and a self-assembled monolayer on the lower electrode. After an upper electrode is formed on the self-assembled monolayer, the self-assembled monolayer may be removed to form a gap between the lower electrode and the upper electrode. A functional molecule having a functional group may be injected into the gap.
摘要翻译：提供了制造分子装置的分子装置和方法。分子器件可以包括在基底上的下电极和下电极上的自组装单层。在自组装单层上形成上电极之后，可以去除自组装单层以在下电极和上电极之间形成间隙。可以将具有官能团的功能性分子注入到间隙中。

65. 发明授权

US07396726B2 Methods of fabricating surrounded-channel transistors with directionally etched gate or insulator formation regions 有权
标题翻译：用定向蚀刻的栅极或绝缘体形成区域制造环绕晶体管的方法
公开(公告)号：US07396726B2
公开(公告)日：2008-07-08
申请号：US11095969
申请日：2005-03-31
申请人： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Sung-Young Lee
发明人： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Sung-Young Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/42392 , H01L29/66545 , H01L29/66795 , H01L29/78645 , Y10S438/924
摘要： An elongate stacked semiconductor structure is formed on a substrate. The stacked semiconductor structure includes a second semiconductor material region disposed on a first semiconductor material region. The first semiconductor material region is selectively doped to produce spaced-apart impurity-doped first semiconductor material regions and a lower dopant concentration first semiconductor material region therebetween. Etching exposes a portion of the second semiconductor material region between the impurity-doped first semiconductor material regions. The etching removes at least a portion of the lower dopant concentration first semiconductor material region to form a hollow between the substrate and the portion of the second semiconductor material region between the impurity-doped first semiconductor material regions. An insulation layer that surrounds the exposed portion of the second semiconductor material region between the impurity-doped first semiconductor material regions is formed. The hollow may be filled with a gate electrode that completely surrounds the exposed portion of the second semiconductor material region, or the gate electrode may partially surround the exposed portion of the second semiconductor material region and an insulation region may be formed in the hollow.
摘要翻译：在衬底上形成细长的堆叠半导体结构。层叠的半导体结构包括设置在第一半导体材料区域上的第二半导体材料区域。第一半导体材料区域被选择性地掺杂以产生间隔杂质掺杂的第一半导体材料区域和其间的较低掺杂浓度的第一半导体材料区域。蚀刻使杂质掺杂的第一半导体材料区域之间的第二半导体材料区域的一部分暴露。蚀刻去除下掺杂剂浓度的第一半导体材料区域的至少一部分，以在衬底与掺杂杂质的第一半导体材料区域之间的第二半导体材料区域的部分之间形成中空。形成了在杂质掺杂的第一半导体材料区域之间围绕第二半导体材料区域的暴露部分的绝缘层。中空部可以填充有完全围绕第二半导体材料区域的暴露部分的栅电极，或者栅电极可以部分地围绕第二半导体材料区域的暴露部分，并且可以在中空部中形成绝缘区域。

66. 发明申请

US20080194065A1 INTEGRATED CIRCUIT DEVICES HAVING AN EPITAXIAL PATTERN WITH A VOID REGION FORMED THEREIN AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：具有形成有空位区域的外延图案的集成电路装置及其形成方法
公开(公告)号：US20080194065A1
公开(公告)日：2008-08-14
申请号：US12107468
申请日：2008-04-22
申请人： Sung-Young Lee , Sung-Min Kim , Dong-Gun Park , Kyoung-Hwan Yeo
发明人： Sung-Young Lee , Sung-Min Kim , Dong-Gun Park , Kyoung-Hwan Yeo
IPC分类号： H01L21/02
CPC分类号： H01L29/66651 , H01L21/76224 , H01L21/76289 , H01L21/764 , H01L29/0649 , H01L29/66795 , H01L29/785 , H01L29/78603 , H01L29/802
摘要： An integrated circuit device includes a substrate. An epitaxial pattern is on the substrate and has a pair of impurity diffusion regions formed therein and a pair of void regions formed therein that are disposed between the pair of impurity diffusion regions and the substrate. Respective ones of the pair of impurity diffusion regions at least partially overlap respective ones of the pair of void regions. A gate electrode is on the epitaxial pattern between respective ones of the pair of impurity diffusion regions.
摘要翻译：集成电路器件包括衬底。外延图案位于基板上，并且在其间形成有一对杂质扩散区域和形成在其中的一对空隙区域，其设置在该对杂质扩散区域和基板之间。该对杂质扩散区域中的各一个至少部分地重叠该对空隙区域中的相应的一个。栅极电极位于一对杂质扩散区域中的各自之间的外延图案上。

67. 发明授权

US07575964B2 Semiconductor device employing buried insulating layer and method of fabricating the same 失效
标题翻译：采用埋层绝缘层的半导体器件及其制造方法
公开(公告)号：US07575964B2
公开(公告)日：2009-08-18
申请号：US11944260
申请日：2007-11-21
申请人： Chang-Woo Oh , Dong-Gun Park , Jeong-Dong Choe , Kyoung-Hwan Yeo
发明人： Chang-Woo Oh , Dong-Gun Park , Jeong-Dong Choe , Kyoung-Hwan Yeo
IPC分类号： H01L21/337
CPC分类号： H01L29/66651 , H01L27/10873 , H01L29/0653 , H01L29/66659
摘要： A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silicon pattern includes a channel region, and a source region and a drain region spaced apart from each other by the channel region. A gate electrode is electrically insulated from the upper silicon pattern and intersects over the channel region. A bit line and a cell capacitor are electrically connected to the source region and the drain region, respectively. A buried insulating layer is interposed between the drain region and the lower semiconductor substrate. The buried insulating layer has an extension portion partially interposed between the channel region and the lower semiconductor substrate.
摘要翻译：半导体器件采用非对称埋层绝缘层及其制造方法。半导体器件包括下半导体衬底。上硅图案位于下半导体衬底上。上部硅图案包括通道区域以及由沟道区域彼此间隔开的源极区域和漏极区域。栅电极与上硅图案电绝缘，并且在沟道区域上相交。位线和单元电容器分别电连接到源极区域和漏极区域。掩埋绝缘层插入在漏区和下半导体衬底之间。掩埋绝缘层具有部分插入在沟道区域和下半导体衬底之间的延伸部分。

68. 发明授权

US06951785B2 Methods of forming field effect transistors including raised source/drain regions 有权
标题翻译：形成包括升高的源极/漏极区域的场效应晶体管的方法
公开(公告)号：US06951785B2
公开(公告)日：2005-10-04
申请号：US10832080
申请日：2004-04-26
申请人： Chang-Woo Oh , Dong-Gun Park , Jeong-Dong Choe , Chang-Sub Lee
发明人： Chang-Woo Oh , Dong-Gun Park , Jeong-Dong Choe , Chang-Sub Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L29/66537 , H01L29/66553
摘要： A method of forming a field effect transistor may include forming a doped layer at a surface of a semiconductor substrate, and forming a groove through the doped layer at the surface of the semiconductor substrate while maintaining portions of the doped layer on opposite sides of the groove. A gate insulating layer may be formed on a surface of the groove, and a gate electrode may be formed on the gate insulating layer in the groove.
摘要翻译：形成场效应晶体管的方法可以包括在半导体衬底的表面上形成掺杂层，并且在半导体衬底的表面上形成通过掺杂层的沟槽，同时保持掺杂层在槽的相对侧上的部分。可以在沟槽的表面上形成栅极绝缘层，并且可以在沟槽中的栅极绝缘层上形成栅电极。

69. 发明申请

US20100109087A1 Multichannel Metal Oxide Semiconductor (MOS) Transistors 审中-公开
标题翻译：多通道金属氧化物半导体（MOS）晶体管
公开(公告)号：US20100109087A1
公开(公告)日：2010-05-06
申请号：US12687613
申请日：2010-01-14
申请人： Kyoung-Hwan Yeo , Dong-Gun Park , Jeong-Dong Choe
发明人： Kyoung-Hwan Yeo , Dong-Gun Park , Jeong-Dong Choe
IPC分类号： H01L29/78
CPC分类号： H01L29/66484 , H01L21/8221 , H01L21/823412 , H01L27/0688 , H01L29/7831
摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate an a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is positioned between the source region and the drain region. A horizontal channel is provided between the source and drain regions. The horizontal channel includes at least two spaced apart horizontal channel regions. Related methods of fabricating MOS transistors are also provided.
摘要翻译：提供金属氧化物半导体（MOS）晶体管的单元电池，其包括集成电路基板和集成电路基板上的MOS晶体管。 MOS晶体管包括源极区，漏极区和栅极。栅极位于源极区域和漏极区域之间。在源区和漏区之间提供水平通道。水平通道包括至少两个间隔开的水平通道区域。还提供了制造MOS晶体管的相关方法。

70. 发明授权

US07670912B2 Methods of fabricating multichannel metal oxide semiconductor (MOS) transistors 有权
标题翻译：制造多通道金属氧化物半导体（MOS）晶体管的方法
公开(公告)号：US07670912B2
公开(公告)日：2010-03-02
申请号：US10797463
申请日：2004-03-10
申请人： Kyoung-Hwan Yeo , Dong-Gun Park , Jeong-Dong Choe
发明人： Kyoung-Hwan Yeo , Dong-Gun Park , Jeong-Dong Choe
IPC分类号： H01L21/336
CPC分类号： H01L29/66484 , H01L21/8221 , H01L21/823412 , H01L27/0688 , H01L29/7831
摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate an a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is positioned between the source region and the drain region. A horizontal channel is provided between the source and drain regions. The horizontal channel includes at least two spaced apart horizontal channel regions. Related methods of fabricating MOS transistors are also provided.
摘要翻译：提供金属氧化物半导体（MOS）晶体管的单元电池，其包括集成电路基板和集成电路基板上的MOS晶体管。 MOS晶体管包括源极区，漏极区和栅极。栅极位于源极区域和漏极区域之间。在源区和漏区之间提供水平通道。水平通道包括至少两个间隔开的水平通道区域。还提供了制造MOS晶体管的相关方法。

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