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61. 发明授权

US08586440B2 Methods for fabricating integrated circuits using non-oxidizing resist removal 有权
标题翻译：使用非氧化抗蚀剂去除制造集成电路的方法
公开(公告)号：US08586440B2
公开(公告)日：2013-11-19
申请号：US13192332
申请日：2011-07-27
申请人： Stefan Flachowsky , Steven Langdon , Thomas Feudel
发明人： Stefan Flachowsky , Steven Langdon , Thomas Feudel
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/26513 , H01L21/26586 , H01L21/28167 , H01L21/31138 , H01L21/324 , H01L21/823814 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7848
摘要： Methods are provided for fabricating integrated circuits using non-oxidizing resist removal. In accordance with one embodiment the method includes forming a gate electrode structure overlying a semiconductor substrate and applying and patterning a layer of resist to expose a portion of the semiconductor substrate adjacent the gate electrode structure. Conductivity determining ions are implanted into the semiconductor substrate using the gate electrode structure and the layer of resist as an implant mask. The layer of resist is removed in a non-oxidizing ambient and the implanted conductivity determining ions are activated by thermal annealing.
摘要翻译：提供了使用非氧化抗蚀剂去除制造集成电路的方法。根据一个实施例，该方法包括形成覆盖在半导体衬底上的栅电极结构，并施加和构图抗蚀剂层以暴露与栅电极结构相邻的半导体衬底的一部分。使用栅电极结构和抗蚀剂层作为植入掩模将电导率确定离子注入到半导体衬底中。在非氧化环境中去除抗蚀剂层，并且通过热退火来激活注入的电导率确定离子。

62. 发明申请

US20130244388A1 METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH REDUCED ELECTRICAL PARAMETER VARIATION 审中-公开
标题翻译：用减少电气参数变化制造集成电路的方法
公开(公告)号：US20130244388A1
公开(公告)日：2013-09-19
申请号：US13421604
申请日：2012-03-15
申请人： Thilo Scheiper , Stefan Flachowsky , Shesh Mani Pandey
发明人： Thilo Scheiper , Stefan Flachowsky , Shesh Mani Pandey
IPC分类号： H01L21/336
CPC分类号： H01L21/823412 , H01L21/26586 , H01L21/823418 , H01L29/1045 , H01L29/1083 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a gate stack on a semiconductor substrate. In the method, a first halo implantation is performed on the semiconductor substrate with a first dose of dopant ions to form first halo regions therein. A second halo spacer is formed around the gate stack. Then a second halo implantation is performed on the semiconductor substrate with a second dose of dopant ions to form second halo regions therein.
摘要翻译：提供了制造集成电路的方法。在一个实施例中，一种用于制造集成电路的方法包括在半导体衬底上形成栅叠层。在该方法中，在第一剂量的掺杂剂离子的半导体衬底上进行第一晕圈注入，以在其中形成第一晕圈。在栅堆叠周围形成第二晕环。然后在第二剂量的掺杂剂离子的半导体衬底上进行第二晕圈注入，以在其中形成第二晕圈。

63. 发明授权

US08508001B2 Semiconductor device with work function adjusting layer having varied thickness in a gate width direction and methods of making same 有权
标题翻译：具有在栅极宽度方向上具有不同厚度的功函数调节层的半导体器件及其制造方法
公开(公告)号：US08508001B2
公开(公告)日：2013-08-13
申请号：US13217792
申请日：2011-08-25
申请人： Steven Langdon , Stefan Flachowsky , Thilo Scheiper
发明人： Steven Langdon , Stefan Flachowsky , Thilo Scheiper
IPC分类号： H01L29/45 , H01L29/49 , H01L29/78 , H01L27/14 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/823412 , H01L21/823807 , H01L21/84 , H01L29/1037 , H01L29/1054 , H01L29/165 , H01L29/6659 , H01L29/66772 , H01L29/7834 , H01L29/78654
摘要： Disclosed herein is a semiconductor device that includes a semiconducting substrate and a work-function adjusting layer positioned at least partially in the semiconducting substrate, the work-function adjusting layer having a middle section, opposing ends and an end region located proximate each of said opposing ends and a gate electrode positioned above the work-function adjusting layer. Each of the end regions has a maximum thickness that is at least 25% greater than an average thickness of the middle section of the work-function adjusting layer.
摘要翻译：本文公开了一种半导体器件，其包括半导体衬底和至少部分地位于半导体衬底中的功函数调整层，所述功函数调整层具有中间部分，相对端部和靠近所述相对的每一个的端部区域端部和位于功函调整层上方的栅电极。每个端部区域的最大厚度比工作功能调节层的中间部分的平均厚度大至少25％。

64. 发明申请

US20130183817A1 Methods of Reducing Gate Leakage 有权
标题翻译：减少闸门泄漏的方法
公开(公告)号：US20130183817A1
公开(公告)日：2013-07-18
申请号：US13350891
申请日：2012-01-16
申请人： Ricardo P. Mikalo , Stefan Flachowsky
发明人： Ricardo P. Mikalo , Stefan Flachowsky
IPC分类号： H01L21/425
CPC分类号： H01L21/26586 , H01L21/26506 , H01L21/2686 , H01L21/28176 , H01L21/31155 , H01L29/512 , H01L29/66545
摘要： Disclosed herein are various methods of reducing gate leakage in semiconductor devices such as transistors. In one example, a method disclosed herein includes performing an etching process to define a gate insulation layer of a transistor, wherein the gate insulation layer has an etched edge, performing an angled ion implantation process to implant ions into the gate insulation layer proximate the etched edge of the gate insulation layer and, after performing the angled ion implantation process, performing an anneal process.
摘要翻译：这里公开了减少诸如晶体管的半导体器件中的栅极泄漏的各种方法。在一个示例中，本文公开的方法包括执行蚀刻工艺以限定晶体管的栅极绝缘层，其中栅极绝缘层具有蚀刻边缘，执行成角度的离子注入工艺以将离子注入靠近蚀刻的栅极绝缘层并且在进行成角度的离子注入工艺之后进行退火处理。

65. 发明授权

US08466018B2 Methods of forming a PMOS device with in situ doped epitaxial source/drain regions 有权
标题翻译：用原位掺杂的外延源/漏区形成PMOS器件的方法
公开(公告)号：US08466018B2
公开(公告)日：2013-06-18
申请号：US13190940
申请日：2011-07-26
申请人： Ralf Illgen , Stefan Flachowsky , Ina Ostermay
发明人： Ralf Illgen , Stefan Flachowsky , Ina Ostermay
IPC分类号： H01L21/8238 , H01L21/70
CPC分类号： H01L21/823814 , H01L21/823807
摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method includes forming extension implant regions in a PMOS region and a NMOS region of a semiconducting substrate for a PMOS device and a NMOS device, respectively and, after forming the extension implant regions, performing a first heating process. The method further includes forming a plurality of cavities in the PMOS region of the substrate, performing at least one epitaxial deposition process to form a plurality of in-situ doped semiconductor layers that are positioned in or above each of said cavities, and forming a masking layer that exposes the NMOS region and covers the PMOS region. The method concludes with the steps of forming source/drain implant regions in the NMOS region of the substrate for the NMOS device and performing a second heating process.
摘要翻译：本文公开了形成半导体器件的方法。在一个示例中，该方法包括分别在用于PMOS器件和NMOS器件的PMOS区域和半导体衬底的NMOS区域中形成扩展注入区域，并且在形成扩展注入区域之后，执行第一加热过程。该方法还包括在衬底的PMOS区域中形成多个空腔，执行至少一个外延沉积工艺以形成位于每个所述空腔中或上方的多个原位掺杂半导体层，并形成掩模暴露NMOS区并覆盖PMOS区的层。该方法的结论是在用于NMOS器件的衬底的NMOS区域中形成源极/漏极注入区域并执行第二加热过程的步骤。

66. 发明申请

US20120261725A1 Stabilized Metal Silicides in Silicon-Germanium Regions of Transistor Elements 有权
标题翻译：晶体管元素硅锗区稳定金属硅化物
公开(公告)号：US20120261725A1
公开(公告)日：2012-10-18
申请号：US13086516
申请日：2011-04-14
申请人： Stefan Flachowsky , Clemens Fitz , Tom Herrmann
发明人： Stefan Flachowsky , Clemens Fitz , Tom Herrmann
IPC分类号： H01L29/772 , H01L21/265
CPC分类号： H01L29/7833 , H01L21/26506 , H01L21/28518 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： Generally, the present disclosure is directed to methods of stabilizing metal silicide contact regions formed in a silicon-germanium active area of a semiconductor device, and devices comprising stabilized metal silicides. One illustrative method disclosed herein includes performing an activation anneal to activate dopants implanted in an active area of a semiconductor device, wherein the active area comprises germanium. Additionally, the method includes, among other things, performing an ion implantation process to implant ions into the active area after performing the activation anneal, forming a metal silicide contact region in the active area, and forming a conductive contact element to the metal silicide contact region.
摘要翻译：通常，本公开涉及稳定在半导体器件的硅 - 锗有源区域中形成的金属硅化物接触区域的稳定化方法，以及包括稳定的金属硅化物的器件。本文公开的一种说明性方法包括执行激活退火以激活植入半导体器件的有源区域中的掺杂剂，其中所述有源区域包括锗。另外，该方法尤其包括执行离子注入工艺以在进行激活退火之后将离子注入到有源区域中，在有源区域中形成金属硅化物接触区域，并在金属硅化物接触部分形成导电接触元件地区。

67. 发明授权

US09012277B2 In situ doping and diffusionless annealing of embedded stressor regions in PMOS and NMOS devices 有权
标题翻译：在PMOS和NMOS器件中嵌入的应力区域的原位掺杂和无扩散退火
公开(公告)号：US09012277B2
公开(公告)日：2015-04-21
申请号：US13346043
申请日：2012-01-09
申请人： Stefan Flachowsky , Ralf Illgen
发明人： Stefan Flachowsky , Ralf Illgen
IPC分类号： H01L21/70 , H01L21/8238 , H01L21/36 , H01L21/268 , H01L29/49 , H01L29/51 , H01L29/66
CPC分类号： H01L21/823807 , H01L21/268 , H01L21/2686 , H01L21/823814 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： Generally, the present disclosure is directed to methods for forming dual embedded stressor regions in semiconductor devices such as transistor elements and the like, using in situ doping and substantially diffusionless annealing techniques. One illustrative method disclosed herein includes forming first and second cavities in PMOS and NMOS device regions, respectively, of a semiconductor substrate, and thereafter performing first and second epitaxial deposition processes to form in situ doped first and second embedded material regions in the first and second cavities, respectively. The method further includes, among other things, performing a single heat treating process to activate dopants in the in situ doped first and second embedded material regions.
摘要翻译：通常，本公开涉及使用原位掺杂和基本上无扩散退火技术在诸如晶体管元件等的半导体器件中形成双嵌入应力源区域的方法。本文公开的一种说明性方法包括分别在半导体衬底的PMOS和NMOS器件区域中形成第一和第二空腔，然后执行第一和第二外延沉积工艺，以在第一和第二外延材料区域中形成第一和第二外延材料区域腔。该方法还包括执行单一热处理工艺以激活原位掺杂的第一和第二嵌入材料区域中的掺杂剂。

68. 发明授权

US08859408B2 Stabilized metal silicides in silicon-germanium regions of transistor elements 有权
标题翻译：稳定的金属硅化物在晶体管元件的硅 - 锗区域
公开(公告)号：US08859408B2
公开(公告)日：2014-10-14
申请号：US13086516
申请日：2011-04-14
申请人： Stefan Flachowsky , Clemens Fitz , Tom Herrmann
发明人： Stefan Flachowsky , Clemens Fitz , Tom Herrmann
IPC分类号： H01L21/425 , H01L29/66 , H01L29/165 , H01L21/285 , H01L21/265 , H01L29/78
CPC分类号： H01L29/7833 , H01L21/26506 , H01L21/28518 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： Generally, the present disclosure is directed to methods of stabilizing metal silicide contact regions formed in a silicon-germanium active area of a semiconductor device, and devices comprising stabilized metal silicides. One illustrative method disclosed herein includes performing an activation anneal to activate dopants implanted in an active area of a semiconductor device, wherein the active area comprises germanium. Additionally, the method includes, among other things, performing an ion implantation process to implant ions into the active area after performing the activation anneal, forming a metal silicide contact region in the active area, and forming a conductive contact element to the metal silicide contact region.
摘要翻译：通常，本公开涉及稳定在半导体器件的硅 - 锗有源区域中形成的金属硅化物接触区域的稳定化方法，以及包括稳定的金属硅化物的器件。本文公开的一种说明性方法包括执行激活退火以激活植入半导体器件的有源区域中的掺杂剂，其中所述有源区域包括锗。另外，该方法尤其包括执行离子注入工艺以在进行激活退火之后将离子注入到有源区域中，在有源区域中形成金属硅化物接触区域，并在金属硅化物接触部分形成导电接触元件地区。

69. 发明授权

US08815736B2 Methods of forming metal silicide regions on semiconductor devices using different temperatures 有权
标题翻译：在使用不同温度的半导体器件上形成金属硅化物区域的方法
公开(公告)号：US08815736B2
公开(公告)日：2014-08-26
申请号：US13218089
申请日：2011-08-25
申请人： Thilo Scheiper , Peter Javorka , Stefan Flachowsky , Clemens Fitz
发明人： Thilo Scheiper , Peter Javorka , Stefan Flachowsky , Clemens Fitz
IPC分类号： H01L21/8238 , H01L21/44 , H01L21/285
CPC分类号： H01L21/28518 , H01L21/823814 , H01L21/823835
摘要： Disclosed herein are various methods of forming metal silicide regions on semiconductor devices by using different temperatures during the silicidation processes. In one example, the method includes forming a plurality of N-doped source/drain regions and a plurality of P-doped source/drain regions in a semiconducting substrate and performing a first heating process at a first temperature to initially form a first metal silicide region in each of the P-doped source/drain regions. The method further includes performing a second heating process at a second temperature to initially form a second metal silicide region in each of the N-doped source/drain regions, wherein the second temperature is less than the first temperature and performing a third heating process at a third temperature to complete the formation of the first and second metal silicide regions, wherein the third temperature is greater than the first temperature.
摘要翻译：本文公开了通过在硅化工艺期间使用不同温度在半导体器件上形成金属硅化物区域的各种方法。在一个示例中，该方法包括在半导体衬底中形成多个N掺杂源极/漏极区域和多个P掺杂的源极/漏极区域，并且在第一温度下执行第一加热过程以最初形成第一金属硅化物每个P掺杂源/漏区中的区域。该方法还包括在第二温度下执行第二加热处理，以在N掺杂源极/漏极区域中的每一个中初始形成第二金属硅化物区域，其中第二温度小于第一温度，并且在第三温度以完成所述第一和第二金属硅化物区域的形成，其中所述第三温度大于所述第一温度。

70. 发明授权

US08709902B2 Sacrificial spacer approach for differential source/drain implantation spacers in transistors comprising a high-k metal gate electrode structure 有权
标题翻译：在包含高k金属栅电极结构的晶体管中的差分源极/漏极注入间隔物的牺牲间隔法
公开(公告)号：US08709902B2
公开(公告)日：2014-04-29
申请号：US13192567
申请日：2011-07-28
申请人： Thilo Scheiper , Kerstin Ruttloff , Maciej Wiatr , Stefan Flachowsky
发明人： Thilo Scheiper , Kerstin Ruttloff , Maciej Wiatr , Stefan Flachowsky
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823864
摘要： In complex semiconductor devices, the profiling of the deep drain and source regions may be accomplished individually for N-channel transistors and P-channel transistors without requiring any additional process steps by using a sacrificial spacer element as an etch mask and as an implantation mask for incorporating the drain and source dopant species for deep drain and source areas for one type of transistor. On the other hand, the usual main spacer may be used for the incorporation of the deep drain and source regions of the other type of transistor.
摘要翻译：在复杂的半导体器件中，可以通过使用牺牲隔离元件作为蚀刻掩模而将N沟道晶体管和P沟道晶体管分别完成深漏极和源极区的分布，而不需要任何额外的工艺步骤，并且作为注入掩模结合用于一种类型晶体管的深漏极和源极区的漏极和源极掺杂物种类。另一方面，通常的主间隔物可以用于结合另一种晶体管的深漏极和源极区。

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