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61. 发明授权

US5619662A Memory reference tagging 失效
标题翻译：内存引用标记
公开(公告)号：US5619662A
公开(公告)日：1997-04-08
申请号：US289613
申请日：1994-08-12
申请人： Simon C. Steely, Jr. , David J. Sager , David B. Fite, Jr.
发明人： Simon C. Steely, Jr. , David J. Sager , David B. Fite, Jr.
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F9/3863 , G06F9/3012 , G06F9/30141 , G06F9/322 , G06F9/3802 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3848 , G06F9/3855 , G06F9/3857
摘要： A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from the instruction processor. The mapped register operand fields are associated with the corresponding instructions of the reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.
摘要翻译：流水线处理器包括指令盒，其包括寄存器映射器，映射一组指令的寄存器操作数字段和由该组指令馈送的指令调度器，以从指令处理器重新排序指令集的发布。映射的寄存器操作数字段在指令发布之前与重新排序的指令集的相应指令相关联。处理器还包括分支预测表，其将与分支指令相关联的过去历史的存储模式映射到分支指令的更可能的预测方向。处理器还包括与指令调度器相关联的存储器参考标记存储器，使得调度器可以在不知道由存储器参考指令寻址的实际存储器位置的情况下重新排序存储器参考指令。

62. 发明授权

US5564118A Past-history filtered branch prediction 失效
标题翻译：过去历史过滤分支预测
公开(公告)号：US5564118A
公开(公告)日：1996-10-08
申请号：US352291
申请日：1994-12-08
申请人： Simon C. Steely, Jr. , David J. Sager , William B. Noyce
发明人： Simon C. Steely, Jr. , David J. Sager , William B. Noyce
IPC分类号： G06F9/30 , G06F9/312 , G06F9/38 , G06F9/40
CPC分类号： G06F9/3806 , G06F9/30043 , G06F9/3012 , G06F9/30134 , G06F9/30141 , G06F9/3836 , G06F9/384 , G06F9/3848 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by said set of instructions, to reorder the issuance of said set of instructions from said instruction processor. The mapped register operand fields are associated with the corresponding instructions of said reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.
摘要翻译：流水线处理器包括指令盒，其包括寄存器映射器，映射一组指令的寄存器操作数字段和由所述指令组馈送的指令调度器，以从所述指令处理器重新排序所述指令集的发布。映射的寄存器操作数字段在指令发布之前与所述重新排序的指令集的相应指令相关联。处理器还包括分支预测表，其将与分支指令相关联的过去历史的存储模式映射到分支指令的更可能的预测方向。处理器还包括与指令调度器相关联的存储器参考标记存储器，使得调度器可以在不知道由存储器参考指令寻址的实际存储器位置的情况下重新排序存储器参考指令。

63. 发明授权

US5551048A Ring based distributed communication bus for a multiprocessor network 失效
标题翻译：用于多处理器网络的基于环的分布式通信总线
公开(公告)号：US5551048A
公开(公告)日：1996-08-27
申请号：US253474
申请日：1994-06-03
申请人： Simon C. Steely, Jr.
发明人： Simon C. Steely, Jr.
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0813 , G06F12/0815 , Y10S707/99952
摘要： A method for providing communication between a plurality of nodes coupled in a ring arrangement, wherein a plurality of the nodes comprise processors each having a cache memory for storing a subset of shared data. Each of the nodes on the ring deposits data into a data slot during a given time period. The data deposited by each node may comprise an address field and a node field. To ensure data coherency between the caches, each processor on the ring includes a queue for saving a plurality of received data representative of the latest bus data transmitted on the bus. As each processor receives new data, the new data is compared against the plurality of saved data in the queue to determine if the address field of the new data matches the address field of any of the saved data of the queue. In the event that the new data matches one of the plurality of saved data, it is determined whether the new data represents updated data from the memory device. If the new data represents updated data it is shifted into the queue. If it does not represent updated data, it is discarded.
摘要翻译：一种用于在以环形布置耦合的多个节点之间提供通信的方法，其中多个节点包括具有用于存储共享数据子集的高速缓存存储器的处理器。环中的每个节点在给定时间段内将数据存入数据时隙。由每个节点存储的数据可以包括地址字段和节点字段。为了确保高速缓存之间的数据一致性，环上的每个处理器包括用于保存表示在总线上发送的最新总线数据的多个接收数据的队列。当每个处理器接收新数据时，将新数据与队列中的多个保存的数据进行比较，以确定新数据的地址字段是否与队列中保存的任何数据的地址字段匹配。在新数据与多个保存数据中的一个匹配的情况下，确定新数据是否表示来自存储装置的更新数据。如果新的数据表示更新的数据，则它被转移到队列中。如果不表示已更新的数据，则会被丢弃。

64. 发明授权

US5519841A Multi instruction register mapper 失效
标题翻译：多指令寄存器映射器
公开(公告)号：US5519841A
公开(公告)日：1996-05-21
申请号：US974776
申请日：1992-11-12
申请人： David J. Sager , Simon C. Steely, Jr. , David B. Fite, Jr.
发明人： David J. Sager , Simon C. Steely, Jr. , David B. Fite, Jr.
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F9/34
CPC分类号： G06F9/3863 , G06F9/32 , G06F9/3806 , G06F9/3814 , G06F9/3836 , G06F9/384 , G06F9/3848 , G06F9/3855 , G06F9/3857
摘要： A pipelined processor includes an instruction unit including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from the processor. The mapped register operand fields are associated with the corresponding instructions of the reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.
摘要翻译：流水线处理器包括指令单元，其包括寄存器映射器，映射一组指令的寄存器操作数字段和由该组指令馈送的指令调度器，以从处理器重新排序指令集的发布。映射的寄存器操作数字段在指令发布之前与重新排序的指令集的相应指令相关联。处理器还包括分支预测表，其将与分支指令相关联的过去历史的存储模式映射到分支指令的更可能的预测方向。处理器还包括与指令调度器相关联的存储器参考标记存储器，使得调度器可以在不知道由存储器参考指令寻址的实际存储器位置的情况下重新排序存储器参考指令。

65. 发明授权

US5214770A System for flushing instruction-cache only when instruction-cache address and data-cache address are matched and the execution of a return-from-exception-or-interrupt command 失效
标题翻译：仅当指令高速缓存地址和数据高速缓存地址匹配并执行从异常或中断返回命令执行时，仅用于刷新指令缓存的系统
公开(公告)号：US5214770A
公开(公告)日：1993-05-25
申请号：US541485
申请日：1990-06-21
申请人： Raj K. Ramanujan , Peter J. Bannon , Simon C. Steely, Jr.
发明人： Raj K. Ramanujan , Peter J. Bannon , Simon C. Steely, Jr.
IPC分类号： G06F9/38
CPC分类号： G06F9/3812 , G06F9/3861
摘要： A method and apparatus for optimizing the performance of a multiple cache system computer having separate caches for data and instructions in which all writes to the data cache are monitored. If the address tag of the item being written matches one of a list of tags representing valid instructions currently stored in the instruction cache, a flag called I.sub.-- FLUSH.sub.-- ON.sub.-- REI is set. Until this flag is set, REI (Return from Exception or Interrupt) instructions will not flush the instruction cache. When the flag is set, an REI command will also flush or clear the instruction cache. Thus, the instruction cache is only flushed when an address referenced by an instruction is modified, so as to reduce the number of times the cache is flushed and optimize the computer's speed of operation.
摘要翻译：一种用于优化具有用于数据和指令的单独高速缓存的多高速缓存系统计算机的性能的方法和装置，其中监视对数据高速缓存的所有写入。如果正在写入的项目的地址标签与表示当前存储在指令高速缓冲存储器中的有效指令的标签列表中的一个匹配，则设置称为I-FLUSH-ON-REI的标志。在设置此标志之前，REI（从异常或中断返回）指令不会刷新指令高速缓存。当标志置位时，REI命令也将刷新或清除指令高速缓存。因此，当指令引用的地址被修改时，指令高速缓存仅被刷新，以便减少高速缓存刷新的次数并优化计算机的操作速度。

66. 发明授权

US5038278A Cache with at least two fill rates 失效
标题翻译：缓存至少有两个填充率
公开(公告)号：US5038278A
公开(公告)日：1991-08-06
申请号：US611337
申请日：1990-11-09
申请人： Simon C. Steely, Jr. , Raj K. Ramanujan , Peter J. Bannon , Walter A. Beach
发明人： Simon C. Steely, Jr. , Raj K. Ramanujan , Peter J. Bannon , Walter A. Beach
IPC分类号： G06F12/08
CPC分类号： G06F12/0842
摘要： During the operation of a computer system whose processor is supported by virtual cache memory, the cache must be cleared and refilled to allow the replacement of old data with more current data. The cache is filled with either P or N (N>P) blocks of data. Numerous methods for dynamically selecting N or P blocks of data are possible. For instance, immediately after the cache has been flushed, the miss is refilled with N blocks, moving data to the cache at high speed. Once the cache is mostly full, the miss tends to be refilled with P blocks. This maintains the currency of the data in the cache, while simultaneously avoiding writing-over of data already in the cache. The invention is useful in a multi-user/multi-tasking system where the program being run changes frequently, necessitating flushing and clearing the cache frequently.
摘要翻译：在处理器由虚拟高速缓冲存储器支持的计算机系统的操作期间，必须清除缓存并重新填充以允许用更多当前数据替换旧数据。高速缓存用P或N（N> P）数据块填充。用于动态选择N或P个数据块的许多方法是可能的。例如，在高速缓冲存储器被刷新之后，错误将被重新填充N个块，将数据高速移动到高速缓存。一旦缓存大部分已满，则错误将被重新填充P块。这将保持高速缓存中的数据的货币，同时避免缓存中已经存在的数据的写入。本发明在运行程序频繁变化的多用户/多任务系统中是有用的，需要频繁地刷新和清除缓存。

67. 发明授权

US5003459A Cache memory system 失效
标题翻译：缓存存储系统
公开(公告)号：US5003459A
公开(公告)日：1991-03-26
申请号：US176595
申请日：1988-04-01
申请人： Raj K. Ramanujan , Simon C. Steely, Jr. , Peter J. Bannon , David J. Sager
发明人： Raj K. Ramanujan , Simon C. Steely, Jr. , Peter J. Bannon , David J. Sager
IPC分类号： G06F12/10
CPC分类号： G06F12/1045
摘要： The invention is directed to a cache memory system in a data processor including a virtual cache memory, a physical cache memory, a virtual to physical translation buffer, a physical to virtual backmap, an Old-PA pointer and a lockout register. The backmap implements invalidates by clearing the valid flags in virtual cache memory. The Old-PA pointer indicates the backmap entry to be invalidated after a reference misses in the virtual cache. The physical address for data written to virtual cache memory is entered to Old-PA pointer by the translation buffer. The lockout register arrests all references to data which may have synonyms in virtual cache memory. The backmap is also used to invalidate any synonyms.
摘要翻译：本发明涉及包括虚拟高速缓冲存储器，物理高速缓冲存储器，虚拟到物理转换缓冲器，物理到虚拟背景图，旧PA指针和锁定寄存器的数据处理器中的高速缓冲存储器系统。反向映射通过清除虚拟高速缓存中的有效标志来实现无效。 Old-PA指针指示在虚拟缓存中的引用未命中之后，将无效的背景条目。写入虚拟高速缓冲存储器的数据的物理地址由转换缓冲区输入到旧PA指针。锁定寄存器阻止对虚拟高速缓冲存储器中可能具有同义词的数据的所有引用。背景图也用于使任何同义词无效。

68. 发明授权

US09146871B2 Retrieval of previously accessed data in a multi-core processor 有权
标题翻译：在多核处理器中检索以前访问过的数据
公开(公告)号：US09146871B2
公开(公告)日：2015-09-29
申请号：US13995283
申请日：2011-12-28
申请人： Simon C. Steely, Jr. , William C. Hasenplaugh , Joel S. Emer
发明人： Simon C. Steely, Jr. , William C. Hasenplaugh , Joel S. Emer
IPC分类号： G06F13/00 , G06F12/08 , G06F13/38 , G06F13/10
CPC分类号： G06F12/0822 , G06F12/0817 , G06F12/0846 , G06F13/00 , G06F13/10 , G06F13/385
摘要： A multi-core processing apparatus may provide a cache probe and data retrieval method. The method may comprise sending a memory request from a requester to a record keeping structure. The memory request may have a memory address of a memory that stores requested data. The method may further comprise determining a last accessor of the memory address, sending a cache probe to the last accessor, determining the last accessor no longer has a copy of the line; and sending a request for the previously accessed version of the line. The request may bypass the tag-directories and obtain the requested data from memory.
摘要翻译：多核处理装置可以提供高速缓存探针和数据检索方法。该方法可以包括将请求者的存储器请求发送到记录保存结构。存储器请求可以具有存储请求的数据的存储器的存储器地址。该方法还可以包括确定存储器地址的最后存取器，向最后一个存取器发送高速缓存探测器，确定最后一个访问器不再具有该行的副本; 并发送对先前访问版本的行的请求。该请求可以绕过标签目录并从存储器获取所请求的数据。

69. 发明授权

US09037804B2 Efficient support of sparse data structure access 有权
标题翻译：有效支持稀疏数据结构访问
公开(公告)号：US09037804B2
公开(公告)日：2015-05-19
申请号：US13995209
申请日：2011-12-29
申请人： Simon C. Steely, Jr. , William C. Hasenplaugh , Joel S. Emer
发明人： Simon C. Steely, Jr. , William C. Hasenplaugh , Joel S. Emer
IPC分类号： G06F13/00 , G06F12/08
CPC分类号： G06F12/0891 , G06F12/0895
摘要： Method and apparatus to efficiently organize data in caches by storing/accessing data of varying sizes in cache lines. A value may be assigned to a field indicating the size of usable data stored in a cache line. If the field indicating the size of the usable data in the cache line indicates a size less than the maximum storage size, a value may be assigned to a field in the cache line indicating which subset of the data in the field to store data is usable data. A cache request may determine whether the size of the usable data in a cache line is equal to the maximum data storage size. If the size of the usable data in the cache line is equal to the maximum data storage size the entire stored data in the cache line may be returned.
摘要翻译：通过在高速缓存行中存储/访问不同大小的数据来高效地组织高速缓存中的数据的方法和装置。可以将值分配给指示存储在高速缓存行中的可用数据的大小的字段。如果指示高速缓存行中的可用数据的大小的字段指示小于最大存储大小的大小，则可以将值分配给高速缓存行中的字段，指示字段中存储数据的数据的哪个子集是可用的数据。缓存请求可以确定高速缓存行中的可用数据的大小是否等于最大数据存储大小。如果高速缓存行中的可用数据的大小等于最大数据存储大小，则可以返回高速缓存行中的整个存储数据。

70. 发明授权

US08533422B2 Instruction prefetching using cache line history 有权
标题翻译：指令预取使用高速缓存行历史记录
公开(公告)号：US08533422B2
公开(公告)日：2013-09-10
申请号：US12895387
申请日：2010-09-30
申请人： Samantika Subramaniam , Aamer Jaleel , Simon C. Steely, Jr.
发明人： Samantika Subramaniam , Aamer Jaleel , Simon C. Steely, Jr.
IPC分类号： G06F12/06 , G06F12/08
CPC分类号： G06F12/0862 , G06F9/3816 , G06F2212/452 , G06F2212/6024 , Y02D10/13
摘要： An apparatus of an aspect includes a prefetch cache line address predictor to receive a cache line address and to predict a next cache line address to be prefetched. The next cache line address may indicate a cache line having at least 64-bytes of instructions. The prefetch cache line address predictor may have a cache line target history storage to store a cache line target history for each of multiple most recent corresponding cache lines. Each cache line target history may indicate whether the corresponding cache line had a sequential cache line target or a non-sequential cache line target. The cache line address predictor may also have a cache line target history predictor. The cache line target history predictor may predict whether the next cache line address is a sequential cache line address or a non-sequential cache line address, based on the cache line target history for the most recent cache lines.
摘要翻译：一方面的装置包括预取高速缓存行地址预测器，用于接收高速缓存行地址并预测要预取的下一个高速缓存行地址。下一个高速缓存行地址可以指示具有至少64字节指令的高速缓存行。预取高速缓存线地址预测器可以具有高速缓存行目标历史存储器，以存储多个最新对应的高速缓存行中的每一个的高速缓存行目标历史。每个高速缓存行目标历史可以指示对应的高速缓存线是否具有顺序高速缓存行目标或非顺序高速缓存行目标。高速缓存行地址预测器也可以具有高速缓存行目标历史预测器。高速缓存行目标历史预测器可以基于最近的高速缓存行的高速缓存行目标历史来预测下一个高速缓存行地址是顺序高速缓存行地址还是非顺序高速缓存行地址。

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