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    • 61. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20120145799A1
    • 2012-06-14
    • US13372877
    • 2012-02-14
    • Jun KOYAMAShunpei YAMAZAKI
    • Jun KOYAMAShunpei YAMAZAKI
    • G06K19/077
    • G06K19/0723G06K19/0719
    • A semiconductor device with improved reliability, in which increase in power consumption can be reduced. The semiconductor device includes an antenna for transmitting and receiving a wireless signal to/from a communication device and at least first and second functional circuits electrically connected to the antenna. The first functional circuit includes a power supply control circuit for controlling power supply voltage output from a power supply circuit in the second functional circuit. A power supply control circuit in the second functional circuit includes a transistor of which first terminal is electrically connected to an output terminal of the power supply circuit and second terminal is electrically connected to a ground line. A gate terminal of the transistor is electrically connected to the power supply control circuit included in one functional circuit.
    • 具有可靠性提高的能够降低功耗增加的半导体装置。 半导体器件包括用于向/从通信设备发送和接收无线信号的天线以及电连接到天线的至少第一和第二功能电路。 第一功能电路包括用于控制从第二功能电路中的电源电路输出的电源电压的电源控制电路。 第二功能电路中的电源控制电路包括晶体管,其第一端子电连接到电源电路的输出端子,并且第二端子电连接到接地线。 晶体管的栅极端子电连接到包括在一个功能电路中的电源控制电路。
    • 63. 发明申请
    • Light Emitting Element, Light Emitting Device and Electric Appliance Using the Same
    • 发光元件,发光元件及使用其的电器
    • US20120119252A1
    • 2012-05-17
    • US13294458
    • 2011-11-11
    • Kaoru KATOShunpei YAMAZAKI
    • Kaoru KATOShunpei YAMAZAKI
    • H01L33/62
    • H01L51/5048
    • It is an object of the present invention to provide a light emitting element with low drive voltage. In addition, it is another object to provide a light emitting device having the light emitting element. Further in addition, it is another object to provide an electric appliance which has a light emitting element with low drive voltage. A light emitting element of the present invention comprises a pair of electrodes, a layer containing a light emitting element and a layer containing a mixture material which contains a conductive material formed from an inorganic compound and an insulating material formed from an inorganic compound, which are interposed between the pair of electrodes, wherein the layer containing the mixture material has a resistivity of 50,000 to 1,000,000 ohm cm, preferably, 200,000 to 500,000 ohm cm. The drive voltage of the light emitting element can be lowered with the foregoing structure.
    • 本发明的目的是提供一种具有低驱动电压的发光元件。 另外,另一个目的是提供一种具有发光元件的发光器件。 此外,另一目的是提供一种具有低驱动电压的发光元件的电器。 本发明的发光元件包括一对电极,包含发光元件的层和含有由无机化合物形成的导电材料和由无机化合物形成的绝缘材料的混合材料的层,它们是 插入在该对电极之间,其中含有混合材料的层的电阻率为50,000至1,000,000欧姆厘米,优选为20万至50万欧姆厘米。 通过上述结构,能够降低发光元件的驱动电压。
    • 65. 发明申请
    • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    • 半导体器件及其制造方法
    • US20120104568A1
    • 2012-05-03
    • US13348097
    • 2012-01-11
    • Shunpei YAMAZAKI
    • Shunpei YAMAZAKI
    • H01L23/00
    • H01L27/1266H01L27/1214H01L29/66772H01L2924/0002H01L2924/00
    • To provide a method for manufacturing a large-area semiconductor device, to provide a method for manufacturing a semiconductor device with high efficiency, and to provide a highly-reliable semiconductor device in the case of using a large-area substrate including an impurity element. A plurality of single crystal semiconductor substrates are concurrently processed to manufacture an SOI substrate, so that an area of a semiconductor device can be increased and a semiconductor device can be manufactured with improved efficiency. In specific, a series of processes is performed using a tray with which a plurality of semiconductor substrates can be concurrently processed. Here, the tray is provided with at least one depression for holding single crystal semiconductor substrates. Further, deterioration of characteristics of a manufactured semiconductor element is prevented by providing an insulating layer serving as a barrier layer against an impurity element which may affect characteristics of the semiconductor element.
    • 为了提供一种制造大面积半导体器件的方法,提供一种高效率制造半导体器件的方法,并且在使用包括杂质元素的大面积衬底的情况下提供高可靠性的半导体器件。 同时处理多个单晶半导体衬底以制造SOI衬底,使得可以增加半导体器件的面积并且可以以更高的效率制造半导体器件。 具体而言,使用能够同时处理多个半导体基板的托盘进行一系列处理。 这里,托盘设置有用于保持单晶半导体衬底的至少一个凹部。 此外,通过为可能影响半导体元件的特性的杂质元素提供用作阻挡层的绝缘层来防止制造的半导体元件的特性劣化。
    • 67. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20120074418A1
    • 2012-03-29
    • US13298469
    • 2011-11-17
    • Shunpei YAMAZAKI
    • Shunpei YAMAZAKI
    • H01L27/12
    • H01L27/124H01L27/1214H01L27/127H01L29/42384H01L2029/7863
    • NTFT of the present invention has a channel forming region, n-type first, second, and third impurity regions in a semiconductor layer. The second impurity region is a low concentration impurity region that overlaps a tapered potion of a gate electrode with a gate insulating film interposed therebetween, and the impurity concentration of the second impurity region increases gradually from the channel forming region to the first impurity region. And, the third impurity region is a low concentration impurity region that does not overlap the gate electrode. Moreover, a plurality of NTFTs on the same substrate have different second impurity region lengths, respectively, according to difference of the operating voltages. That is, when the operating voltage of the second TFT is higher than the operating voltage of the first TFT, the length of the second impurity region is longer on the second TFT than on the first TFT.
    • 本发明的NTFT在半导体层中具有沟道形成区域,n型第一,第二和第三杂质区域。 第二杂质区域是与栅电极的锥形部分重叠的低浓度杂质区域,其间插入有栅极绝缘膜,并且第二杂质区域的杂质浓度从沟道形成区域逐渐增加到第一杂质区域。 并且,第三杂质区域是不与栅电极重叠的低浓度杂质区域。 此外,根据工作电压的差异,同一衬底上的多个NTFT分别具有不同的第二杂质区长度。 也就是说,当第二TFT的工作电压高于第一TFT的工作电压时,第二TFT上的第二杂质区域的长度比第一TFT长。
    • 69. 发明申请
    • METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    • 制造半导体器件的方法
    • US20120064677A1
    • 2012-03-15
    • US13225703
    • 2011-09-06
    • Hidekazu MIYAIRIKoji DAIRIKIShunpei YAMAZAKIRyo ARASAWA
    • Hidekazu MIYAIRIKoji DAIRIKIShunpei YAMAZAKIRyo ARASAWA
    • H01L21/336
    • H01L29/78678H01L29/66765H01L29/78606H01L29/78648H01L29/78669H01L29/78696
    • Provided is a method for manufacturing a semiconductor device with fewer masks and in a simple process. A gate electrode is formed. A gate insulating film, a semiconductor film, an impurity semiconductor film, and a conductive film are stacked in this order, covering the gate electrode. A source electrode and a drain electrode are formed by processing the conductive film. A source region, a drain region, and a semiconductor layer, an upper part of a portion of which does not overlap with the source region and the drain region is removed, are formed by processing the upper part of the semiconductor film, while the impurity semiconductor film is divided. A passivation film over the gate insulating film, the semiconductor layer, the source region, the drain region, the source electrode, and the drain electrode are formed. An etching mask is formed over the passivation film. At least the passivation film and the semiconductor layer are processed to have an island shape while an opening reaching the source electrode or the drain electrode is formed, with the use of the etching mask. The etching mask is removed. A pixel electrode is formed over the gate insulating film and the passivation film.
    • 提供一种用于制造具有较少掩模的半导体器件的方法,并且在简单的过程中。 形成栅电极。 依次层叠栅绝缘膜,半导体膜,杂质半导体膜和导电膜,覆盖栅电极。 通过处理导电膜形成源电极和漏电极。 通过处理半导体膜的上部,形成源区域,漏极区域和半导体层,其部分的上部不与源极区域和漏极区域重叠,而杂质 半导体薄膜被划分。 形成栅极绝缘膜,半导体层,源极区域,漏极区域,源极电极和漏极电极之后的钝化膜。 在钝化膜上形成蚀刻掩模。 通过使用蚀刻掩模,至少钝化膜和半导体层被加工成具有岛状,同时形成到达源电极或漏电极的开口。 去除蚀刻掩模。 在栅极绝缘膜和钝化膜上形成像素电极。