专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20090240871A1 MEMORY SYSTEM 失效
标题翻译：记忆系统
公开(公告)号：US20090240871A1
公开(公告)日：2009-09-24
申请号：US12396104
申请日：2009-03-02
申请人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda , Wataru Okamoto , Ryoichi Kato
发明人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda , Wataru Okamoto , Ryoichi Kato
IPC分类号： G06F12/00 , G06F12/02 , G06F12/08
CPC分类号： G06F12/0246 , G06F12/0866 , G06F2212/7203
摘要： A system includes: a first input buffer that functions as an input buffer for a third storing area; and a second input buffer that functions as an input buffer for the third storing area and that separately stores data with a high update frequency for the third storing area. In the system, a plurality of data written in a first storing area or a second storing area are flushed to the first input buffer in units of logical blocks. Also, a plurality of data written in the first input buffer are relocated to the third storing area in units of logical blocks.
摘要翻译：一种系统包括：用作第三存储区域的输入缓冲器的第一输入缓冲器; 以及第二输入缓冲器，其用作第三存储区域的输入缓冲器，并且分别存储具有用于第三存储区域的较高更新频率的数据。在系统中，以逻辑块为单位将写入第一存储区域或第二存储区域的多个数据刷新到第一输入缓冲器。此外，写入第一输入缓冲器的多个数据以逻辑块为单位重新定位到第三存储区域。

62. 发明申请

US20090235016A1 MEMORY SYSTEM 失效
标题翻译：记忆系统
公开(公告)号：US20090235016A1
公开(公告)日：2009-09-17
申请号：US12402994
申请日：2009-03-12
申请人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda
发明人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda
IPC分类号： G06F12/00 , G06F12/02 , G06F12/08
CPC分类号： G06F12/0246 , G06F2212/7202 , G06F2212/7203 , G11C2211/5641
摘要： A memory system includes a first storing area included in a volatile semiconductor memory, a second and a third storing area included in a nonvolatile semiconductor memory, a controller that allocates the storage area of the nonvolatile semiconductor memory to the second storing area and the third storing area in a logical block unit associated with one or more blocks. The second storing area is configured to be managed with a first management unit. The third storing area is configured to be managed with a second management unit, a size of the second management unit being larger than a size of the first management unit. When flushing of data from the first storing area to the second storing area or the third storing area is determined, the controller collects, from at least one of the first storing area, the second storing area and the third storing area, data other than the data determined to be flushed and controls the flushing of the data such that a total of the data is a natural number times as large as the block unit as much as possible.
摘要翻译：一种存储系统，包括易失性半导体存储器中包括的第一存储区域，包括在非易失性半导体存储器中的第二和第三存储区域，将非易失性半导体存储器的存储区域分配给第二存储区域和第三存储区域的控制器与一个或多个块相关联的逻辑块单元中的区域。第二存储区域被配置为由第一管理单元管理。第三存储区域被配置为由第二管理单元管理，第二管理单元的大小大于第一管理单元的大小。当从第一存储区域向第二存储区域或第三存储区域清空数据时，控制器从第一存储区域，第二存储区域和第三存储区域中的至少一个收集除了确定要刷新的数据并且控制数据的刷新，使得数据的总和是尽可能多的与块单元一样大的自然数。

63. 发明申请

US20090222616A1 MEMORY SYSTEM 失效
标题翻译：记忆系统
公开(公告)号：US20090222616A1
公开(公告)日：2009-09-03
申请号：US12394582
申请日：2009-02-27
申请人： Junji Yano , Kosuke Hatsuda , Hidenori Matsuzaki
发明人： Junji Yano , Kosuke Hatsuda , Hidenori Matsuzaki
IPC分类号： G06F12/00 , G06F12/02 , G06F12/08
CPC分类号： G06F12/0246 , G06F12/0804 , G06F12/0866 , G06F2212/7201
摘要： A controller includes an identification information management table that manages identification information indicating, for each of addresses in second-management unit, whether one or more data in first management unit belonging to the addresses is stored in the second or the third storing area. When the controller executes a process of flushing data from the first storing area to the second storing area or the third storing area, the controller updates the identification information in the identification information management table. The controller executes a process of reading data from the second storing area or the third storing area by referring to the identification information. As a result, the speed of searches conducted in the management table is increased.
摘要翻译：控制器包括：识别信息管理表，其管理对于第二管理单元中的每个地址，指示属于所述地址的第一管理单元中的一个或多个数据是否存储在所述第二或第三存储区域中的标识信息。当控制器执行将数据从第一存储区域刷新到第二存储区域或第三存储区域的处理时，控制器更新识别信息管理表中的识别信息。控制器通过参照识别信息执行从第二存储区域或第三存储区域读取数据的处理。结果，增加了在管理表中进行的搜索速度。

64. 发明授权

US5194764A Data output buffer circuit for semiconductor integrated circuit having output buffers with different delays 失效
标题翻译：具有不同延迟的输出缓冲器的半导体集成电路的数据输出缓冲电路
公开(公告)号：US5194764A
公开(公告)日：1993-03-16
申请号：US627058
申请日：1990-12-13
申请人： Junji Yano , Tsukasa Miyawaki , Masami Atoh , Masakazu Gotou , Masakazu Iwashita , Michio Kaji
发明人： Junji Yano , Tsukasa Miyawaki , Masami Atoh , Masakazu Gotou , Masakazu Iwashita , Michio Kaji
IPC分类号： G11C11/417 , G11C7/10 , G11C11/409 , H01L21/822 , H01L27/04 , H03K17/16 , H03K17/687 , H03K19/0948
CPC分类号： G11C7/1057 , G11C7/1051 , G11C2207/108
摘要： A data output buffer circuit for a semiconductor integrated circuit has a plurality of output buffer circuits. Each output buffer circuit has an input terminal for receiving input data and an output buffer having first and second switching circuits serially connected between two high and low power source terminals. Each of the first and second switching circuits has a control terminal for turning on and off each of the first and second switching circuits upon receipt of a control signal at the control terminals. A timing signal input terminal receives a timing signal with which the output buffer circuit operates in synchronism. A timing switch connects the next stage of the input terminal and is turned on by the timing signal. A delay signal is connected between the timing switch means and the control terminals of the first and second switching circuits and delays the input data from the input terminal and transmits the delayed input data to the control terminals of the first and second switching circuits. The delay time of the delay circuit of one of the output buffer circuits is different from the delay time of another of the output buffer circuits. An output terminal connects to the interconnection between the first and second switching circuits.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式