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1. 发明授权

US08108593B2 Memory system for flushing and relocating data 失效
标题翻译：用于冲洗和重新定位数据的内存系统
公开(公告)号：US08108593B2
公开(公告)日：2012-01-31
申请号：US12396104
申请日：2009-03-02
申请人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda , Wataru Okamoto , Ryoichi Kato
发明人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda , Wataru Okamoto , Ryoichi Kato
IPC分类号： G06F13/10
CPC分类号： G06F12/0246 , G06F12/0866 , G06F2212/7203
摘要： A system includes: a first input buffer that functions as an input buffer for a third storing area; and a second input buffer that functions as an input buffer for the third storing area and that separately stores data with a high update frequency for the third storing area. In the system, a plurality of data written in a first storing area or a second storing area are flushed to the first input buffer in units of logical blocks. Also, a plurality of data written in the first input buffer are relocated to the third storing area in units of logical blocks.
摘要翻译：一种系统包括：用作第三存储区域的输入缓冲器的第一输入缓冲器; 以及第二输入缓冲器，其用作第三存储区域的输入缓冲器，并且分别存储具有用于第三存储区域的较高更新频率的数据。在系统中，以逻辑块为单位将写入第一存储区域或第二存储区域的多个数据刷新到第一输入缓冲器。此外，写入第一输入缓冲器的多个数据以逻辑块为单位重新定位到第三存储区域。

2. 发明申请

US20090240871A1 MEMORY SYSTEM 失效
标题翻译：记忆系统
公开(公告)号：US20090240871A1
公开(公告)日：2009-09-24
申请号：US12396104
申请日：2009-03-02
申请人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda , Wataru Okamoto , Ryoichi Kato
发明人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda , Wataru Okamoto , Ryoichi Kato
IPC分类号： G06F12/00 , G06F12/02 , G06F12/08
CPC分类号： G06F12/0246 , G06F12/0866 , G06F2212/7203
摘要： A system includes: a first input buffer that functions as an input buffer for a third storing area; and a second input buffer that functions as an input buffer for the third storing area and that separately stores data with a high update frequency for the third storing area. In the system, a plurality of data written in a first storing area or a second storing area are flushed to the first input buffer in units of logical blocks. Also, a plurality of data written in the first input buffer are relocated to the third storing area in units of logical blocks.
摘要翻译：一种系统包括：用作第三存储区域的输入缓冲器的第一输入缓冲器; 以及第二输入缓冲器，其用作第三存储区域的输入缓冲器，并且分别存储具有用于第三存储区域的较高更新频率的数据。在系统中，以逻辑块为单位将写入第一存储区域或第二存储区域的多个数据刷新到第一输入缓冲器。此外，写入第一输入缓冲器的多个数据以逻辑块为单位重新定位到第三存储区域。

3. 发明申请

US20090248964A1 MEMORY SYSTEM AND METHOD FOR CONTROLLING A NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：用于控制非易失性半导体存储器的存储器系统和方法
公开(公告)号：US20090248964A1
公开(公告)日：2009-10-01
申请号：US12394632
申请日：2009-02-27
申请人： Junji Yano , Kosuke Hatsuda , Hidenori Matsuzaki , Wataru Okamoto
发明人： Junji Yano , Kosuke Hatsuda , Hidenori Matsuzaki , Wataru Okamoto
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F3/061 , G06F3/065 , G06F3/0661 , G06F3/0679 , G06F12/0246 , G06F2206/1014 , G06F2212/7203 , G06F2212/7205 , G11C11/5628 , G11C16/0483 , G11C16/102 , G11C2211/5643 , G11C2211/5646
摘要： A memory system includes a nonvolatile semiconductor memory having blocks, the block being data erasing unit; and a controller configured to execute; an update processing for; writing superseding data in a block, the superseding data being treated as valid data; and invalidating superseded data having the same logical address as the superseding data, the superseded data being treated as invalid data; and a compaction processing for; retrieving blocks having invalid data using a management tablet the management table managing blocks in a linked list format for each number of valid data included in the block; selecting a compaction source block having at least one valid data from the retrieved blocks; copying a plurality of valid data included in the compaction source blocks into a compaction target block; invalidating the plurality of valid data in the compaction source blocks; and releasing the compaction source blocks in which all data are invalidated.
摘要翻译：存储器系统包括具有块的非易失性半导体存储器，该块是数据擦除单元; 以及控制器，被配置为执行; 更新处理; 在块中写入替代数据，替代数据被视为有效数据; 并且使具有与取代数据相同的逻辑地址的替代数据无效，所取代的数据被视为无效数据; 和压实处理; 使用管理数据库检索具有无效数据的块，所述管理表管理所述块中包括的每个数量的有效数据的链接列表格式的块; 从所检索的块中选择具有至少一个有效数据的压缩源块; 将压缩源块中包括的多个有效数据复制到压缩目标块中; 使压缩源块中的多个有效数据无效; 并释放其中所有数据无效的压缩源块。

4. 发明授权

US08745313B2 Memory system and method for controlling a nonvolatile semiconductor memory 有权
标题翻译：用于控制非易失性半导体存储器的存储器系统和方法
公开(公告)号：US08745313B2
公开(公告)日：2014-06-03
申请号：US12394632
申请日：2009-02-27
申请人： Junji Yano , Kosuke Hatsuda , Hidenori Matsuzaki , Wataru Okamoto
发明人： Junji Yano , Kosuke Hatsuda , Hidenori Matsuzaki , Wataru Okamoto
IPC分类号： G06F12/00
CPC分类号： G06F3/061 , G06F3/065 , G06F3/0661 , G06F3/0679 , G06F12/0246 , G06F2206/1014 , G06F2212/7203 , G06F2212/7205 , G11C11/5628 , G11C16/0483 , G11C16/102 , G11C2211/5643 , G11C2211/5646
摘要： A memory system includes a nonvolatile semiconductor memory having blocks, the block being data erasing unit; and a controller configured to execute; an update processing for; writing superseding data in a block, the superseding data being treated as valid data; and invalidating superseded data having the same logical address as the superseding data, the superseded data being treated as invalid data; and a compaction processing for; retrieving blocks having invalid data using a management tablet the management table managing blocks in a linked list format for each number of valid data included in the block; selecting a compaction source block having at least one valid data from the retrieved blocks; copying a plurality of valid data included in the compaction source blocks into a compaction target block; invalidating the plurality of valid data in the compaction source blocks; and releasing the compaction source blocks in which all data are invalidated.
摘要翻译：存储器系统包括具有块的非易失性半导体存储器，该块是数据擦除单元; 以及控制器，被配置为执行; 更新处理; 在块中写入替代数据，替代数据被视为有效数据; 并且使具有与取代数据相同的逻辑地址的替代数据无效，所取代的数据被视为无效数据; 和压实处理; 使用管理数据库检索具有无效数据的块，所述管理表管理所述块中包括的每个数量的有效数据的链接列表格式的块; 从所检索的块中选择具有至少一个有效数据的压缩源块; 将压缩源块中包括的多个有效数据复制到压缩目标块中; 使压缩源块中的多个有效数据无效; 并释放其中所有数据无效的压缩源块。

5. 发明授权

US08938586B2 Memory system with flush processing from volatile memory to nonvolatile memory utilizing management tables and different management units 有权
标题翻译：使用管理表和不同管理单元从易失性存储器到非易失性存储器的闪存处理的存储器系统
公开(公告)号：US08938586B2
公开(公告)日：2015-01-20
申请号：US12529228
申请日：2009-02-10
申请人： Junji Yano , Kosuke Hatsuda , Hidenori Matsuzaki , Ryoichi Kato
发明人： Junji Yano , Kosuke Hatsuda , Hidenori Matsuzaki , Ryoichi Kato
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0246 , G06F2212/7207
摘要： A memory system includes: a cache memory, a nonvolatile semiconductor memory, and a controller. The controller includes a plurality of management tables that manage data stored in the cache memory and the nonvolatile semiconductor memory using a cluster unit and a track unit. The controller performs data flushing processing from the cache memory to the nonvolatile semiconductor memory when the number of track units registered in the cache memory exceeds a predetermined threshold. Data may be flushed to the nonvolatile memory in different size data units such as a cluster or a track. Data flushing processing may also be performed if a last free way is used when data writing processing is performed on the cache memory managed in a set associative system. The nonvolatile semiconductor memory can be a NAND flash memory.
摘要翻译：存储器系统包括：高速缓冲存储器，非易失性半导体存储器和控制器。控制器包括多个管理表，其管理存储在高速缓冲存储器中的数据和使用集群单元和轨道单元的非易失性半导体存储器。当登记在高速缓冲存储器中的轨道单元的数量超过预定阈值时，控制器执行从高速缓冲存储器到非易失性半导体存储器的数据刷新处理。可以将数据刷新到不同大小的数据单元（例如，群集或轨道）中的非易失性存储器。如果在对集合关联系统中管理的高速缓冲存储器上执行数据写入处理时，如果使用最后的自由方式，则也可以执行数据刷新处理。非易失性半导体存储器可以是NAND闪存。

6. 发明申请

US20110307667A1 MEMORY SYSTEM 有权
标题翻译：记忆系统
公开(公告)号：US20110307667A1
公开(公告)日：2011-12-15
申请号：US12529228
申请日：2009-02-10
申请人： Junji Yano , Kosuke Hatsuda , Hidenori Matsuzaki , Ryoichi Kato
发明人： Junji Yano , Kosuke Hatsuda , Hidenori Matsuzaki , Ryoichi Kato
IPC分类号： G06F12/08
CPC分类号： G06F12/0246 , G06F2212/7207
摘要： A memory system according to an embodiment of the present invention comprises: a first management table that manages addresses concerning the data written in a first storing area; and a second management table that manages, in an address unit of a second management unit, information indicating temporal order of the data stored in the first storing area and manages, for each of addresses in a second management unit, number-of-valid-data information indicating a number of data in the first management unit included in the addresses in the second management unit.
摘要翻译：根据本发明的实施例的存储器系统包括：第一管理表，其管理与第一存储区域中写入的数据有关的地址; 以及第二管理表，其在第二管理单元的地址单元中管理指示存储在第一存储区域中的数据的时间顺序的信息，并且对于第二管理单元中的每个地址管理有效 - 指示包括在第二管理单元中的地址中的第一管理单元中的数据的数量的数据信息。

7. 发明申请

US20100153626A1 MEMORY SYSTEM 失效
标题翻译：记忆系统
公开(公告)号：US20100153626A1
公开(公告)日：2010-06-17
申请号：US12529223
申请日：2009-02-10
申请人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda , Hiroki Matsudaira
发明人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda , Hiroki Matsudaira
IPC分类号： G06F12/00 , G06F12/16 , G06F12/02
CPC分类号： G06F11/1435 , G06F11/1441 , G06F11/1471 , G06F11/1474
摘要： To provide a memory system that can surely restore management information even when a program error occurs during data writing. After “log writing (1)” for a pre-log, when a program error occurs when data writing is being performed (a data writing error), the memory system performs the data writing again without acquiring a pre-log corresponding to data rewriting processing. After finishing the data writing, the memory system acquires, without generating a post-log, a snapshot instead of the post-log and finishes the processing.
摘要翻译：提供即使在数据写入过程中发生程序错误时也可以确保还原管理信息的存储系统。在“日志写入（1）”作为预登录之后，当执行数据写入时发生程序错误（数据写入错误）时，存储器系统再次执行数据写入，而不获取对应于数据重写的预记录处理。在完成数据写入之后，内存系统在不生成后记录的情况下获取快照而不是后记录，并完成处理。

8. 发明授权

US08171208B2 Memory system 有权
标题翻译：内存系统
公开(公告)号：US08171208B2
公开(公告)日：2012-05-01
申请号：US12529126
申请日：2009-02-10
申请人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda
发明人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda
IPC分类号： G06F12/00
CPC分类号： G06F12/0866 , G06F11/1068 , G06F12/0246 , G06F12/0804 , G06F2212/1032 , G06F2212/2022 , G06F2212/7203
摘要： A memory system includes a DRAM 20 that performs writing and readout in a unit equal to or smaller than a cluster, a NAND memory 10 that performs writing and readout in a page unit, and a management table group in which management information including storage locations of data stored in the DRAM 20 and the NAND memory 10 is stored. When a readout request is received from the outside, a data managing unit 120 notifies, when an unwritten logical address area is present in a storage area of the NAND memory to which a logical address area requested to be read out is mapped, fixed data stored in the DRAM 20 to the outside in association with the logical address area.
摘要翻译：存储器系统包括以等于或小于簇的单位执行写入和读出的DRAM 20，以页单元执行写入和读出的NAND存储器10以及管理表组，其中管理信息包括存储位置存储在DRAM 20和NAND存储器10中的数据被存储。当从外部接收到读出请求时，数据管理单元120在映射了要求读出的逻辑地址区域的NAND存储器的存储区域中存在未写入的逻辑地址区域时，通知存储的固定数据在DRAM 20中与逻辑地址区域相关联到外部。

9. 发明申请

US20110231734A1 MEMORY SYSTEM 失效
标题翻译：记忆系统
公开(公告)号：US20110231734A1
公开(公告)日：2011-09-22
申请号：US13152962
申请日：2011-06-03
申请人： Junji YANO , Hidenori Matsuzaki , Kosuke Hatsuda , Hiroki Matsudaira
发明人： Junji YANO , Hidenori Matsuzaki , Kosuke Hatsuda , Hiroki Matsudaira
IPC分类号： G06F11/16
CPC分类号： G06F11/1068 , G06F3/0619 , G06F3/0679 , G06F11/1072 , G11C16/06 , G11C29/52 , G11C29/78 , G11C2029/0411
摘要： A memory system includes a controlling unit that configured to control data transfer between the first and the second memory. The controlling unit executes copy processing for, after reading out data stored in a first page of the second memory to the first memory, writing the data in a second page of the second memory, determines, when executing the copy processing, whether the error correction processing for the data read out from the first page is successful, stores, when the error correction processing is successful, corrected data in the first memory and writes the corrected data in the second page, and reads out, when the error correction processing is unsuccessful, the data from the first page to the first memory and writes the data not subjected to the error correction processing in the second page.
摘要翻译：存储器系统包括控制单元，其被配置为控制第一和第二存储器之间的数据传输。控制单元执行复制处理，在将第二存储器的第一页中存储的数据读出到第一存储器之后，将数据写入第二存储器的第二页，在执行复制处理时确定纠错从第一页读出的数据的处理成功，当纠错处理成功时存储第一存储器中的校正数据并将修正数据写入第二页，并且当纠错处理失败时读出，从第一页到第一存储器的数据，并将未经过纠错处理的数据写入第二页。

10. 发明申请

US20110185108A1 MEMORY SYSTEM 有权
标题翻译：记忆系统
公开(公告)号：US20110185108A1
公开(公告)日：2011-07-28
申请号：US12529235
申请日：2009-02-10
申请人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda
发明人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda
IPC分类号： G06F12/00 , G06F12/16
CPC分类号： G11C16/102 , G06F11/141 , G06F11/1443 , G06F11/1471 , G11C11/5628 , G11C16/0483 , G11C16/105 , G11C29/00
摘要： A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which a plurality of memory cells that can store multi-value data are arranged, the memory cells having a plurality of pages, and a controller that performs data transfer between a host apparatus and the second storing unit via the first storing unit. The controller includes a save processing unit that backs up, when, before data is written in the second storing unit in a write-once manner, data is written in a lower order page of a memory cell same as that of a page in which the data is written, the data of the lower order page and a broken-information-restoration processing unit that restores, when the data in the lower order page is broken, the broken data using the backed-up data.
摘要翻译：存储器系统包括易失性第一存储单元，非易失性第二存储单元，其中排列可存储多值数据的多个存储器单元，存储单元具有多个页面，以及控制器，其执行数据传输主机设备和第二存储单元。控制器包括一个保存处理单元，其在一次写入数据被写入第二存储单元之后，当数据被写入到存储单元的低位页面中时写入数据，低位页的数据和破损信息恢复处理单元，当低位页中的数据被破坏时，使用备份数据恢复断开的数据。

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