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61. 发明授权

US08395419B2 Semiconductor device and display device 有权
公开(公告)号：US08395419B2
公开(公告)日：2013-03-12
申请号：US12734044
申请日：2008-08-26
申请人： Yuhichiroh Murakami , Yasushi Sasaki , Shige Furuta
发明人： Yuhichiroh Murakami , Yasushi Sasaki , Shige Furuta
IPC分类号： H03B1/00
摘要： A circuit is constituted by a plurality of n-channel-type transistors, the circuit including: among the plurality of transistors, a transistor including a drain terminal for receiving a voltage of VDD, a source terminal, and a gate terminal for receiving an input signal; among the plurality of transistors, a transistor including a drain terminal for receiving the voltage of VDD, a source terminal connected to an output terminal, and a gate terminal connected to the source terminal of the transistor; and a capacitor provided between a node and a clock terminal for receiving a clock signal. In at least one embodiment, the clock signal inputted into the clock terminal has a frequency higher than that of an output signal outputted from the output terminal. Therefore, it is possible to provide: a semiconductor device constituted by transistors of the same conductivity type, which semiconductor device can output a stable signal by preventing a reduction in electric potential level; and a display device including the semiconductor device.

62. 发明申请

US20120307959A1 SHIFT REGISTER 有权
标题翻译：移位寄存器
公开(公告)号：US20120307959A1
公开(公告)日：2012-12-06
申请号：US13571608
申请日：2012-08-10
申请人： Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Shinsaku Shimizu
发明人： Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Shinsaku Shimizu
IPC分类号： G11C19/00
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021
摘要： In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.
摘要翻译：在本发明的一个实施例中，移位寄存器的单元电路包括配置有晶体管T1，晶体管T2和电容器的晶体管T3，晶体管T4和复位信号产生电路的自举电路。通过使用两相时钟信号并且其高电平周期彼此不重叠，复位信号产生电路产生在正常状态下处于高电平的复位信号，并且当输入信号变为低电平时变为低电平进入高层。在复位信号为高电平的期间，晶体管T3，T4进行节点的放电，输出信号的下拉。因此，可以获得省电移位寄存器，其将正常状态下的输出信号固定在低电平，而不允许通流通过。

63. 发明授权

US08269714B2 Shift register 有权
标题翻译：移位寄存器
公开(公告)号：US08269714B2
公开(公告)日：2012-09-18
申请号：US12733119
申请日：2008-05-15
申请人： Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Shinsaku Shimizu
发明人： Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Shinsaku Shimizu
IPC分类号： G09G3/36
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021
摘要： In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a shift register which performs discharge of a node and pull-down of an output signal and achieves a small area and low power consumption without using an output signal from a subsequent circuit.
摘要翻译：在本发明的一个实施例中，移位寄存器的单元电路包括配置有晶体管T1，晶体管T2和电容器的晶体管T3，晶体管T4和复位信号产生电路的自举电路。通过使用高电平周期彼此不重叠的两相时钟信号，复位信号生成电路产生在正常状态下处于高电平的复位信号，并且当输入信号变为低电平时变为低电平高层次。在复位信号处于高电平的期间，晶体管执行节点的放电和输出信号的下拉。因此，可以获得执行节点放电和输出信号下拉的移位寄存器，并且在不使用来自后续电路的输出信号的情况下实现小面积和低功耗。

64. 发明申请

US20120092311A1 Shift Register, Display-Driving Circuit, Displaying Panel, And Displaying Device 有权
标题翻译：移位寄存器，显示驱动电路，显示面板和显示设备
公开(公告)号：US20120092311A1
公开(公告)日：2012-04-19
申请号：US13377855
申请日：2010-03-18
申请人： Hiroyuki Ohkawa , Yasushi Sasaki , Yuhichiroh Murakami , Shige Furuta , Makoto Yokoyama
发明人： Hiroyuki Ohkawa , Yasushi Sasaki , Yuhichiroh Murakami , Shige Furuta , Makoto Yokoyama
IPC分类号： G09G5/00 , G11C19/00
CPC分类号： G09G3/3677 , G09G3/3614 , G09G3/3655 , G09G2310/0245 , G09G2310/0286 , G09G2310/063 , G09G2320/0233 , G09G2330/026 , G09G2330/027 , G11C19/28 , H03K3/356182
摘要： Disclosed is a shift register for use in a display driving circuit that simultaneously selects signal lines, including, in a stage thereof: a flip-flop including an initialization terminal; and a signal generating circuit that receives a simultaneous selection signal and that generates an output signal of the stage by use of an output of the flip-flop, wherein: the output signal of the stage becomes active due to an activation of the simultaneous selection signal so as to be active during a period of the simultaneous selection; the output of the flip-flop is non-active while the initialization terminal, a set terminal, and a reset terminal of the flip-flop; and the initialization terminal of the flip-flop receives the simultaneous selection signal. This shift register makes it possible to downsize various drivers.
摘要翻译：公开了一种在显示驱动电路中使用的移位寄存器，其同时选择信号线，其中包括：其包括初始化端子的触发器; 以及信号发生电路，其接收同时选择信号，并且通过使用所述触发器的输出来产生所述级的输出信号，其中：所述级的输出信号由于同时选择信号的激活而变为有效以便在同时选择期间活跃; 触发器的输出在触发器的初始化端子，设定端子和复位端子处于非有效状态; 并且触发器的初始化端子接收同时选择信号。该移位寄存器使得可以减小各种驱动程序的尺寸。

65. 发明申请

US20120081346A1 SHIFT REGISTER, DISPLAY-DRIVING CIRCUIT, DISPLAYING PANEL, AND DISPLAYING DEVICE 有权
标题翻译：移位寄存器，显示驱动电路，显示面板和显示设备
公开(公告)号：US20120081346A1
公开(公告)日：2012-04-05
申请号：US13377838
申请日：2010-03-18
申请人： Shige Furuta , Makoto Yokoyama , Yasushi Sasaki , Yuhichiroh Murakami
发明人： Shige Furuta , Makoto Yokoyama , Yasushi Sasaki , Yuhichiroh Murakami
IPC分类号： G09G5/00 , G11C19/00
CPC分类号： G11C19/28 , G09G3/3677 , G09G2310/063
摘要： Provided is a shift register of a display-driving circuit which carries out simultaneous selection of a plurality of signal lines by using a simultaneous selection signal. A stage of the shift register includes (i) a set-reset type flip-flop and (ii) a signal generating circuit which generates an output signal of the stage by selectively outputting a signal in response to an output of the flip-flop. The output signal of the stage (i) becomes active due to an activation of the simultaneous selection signal and then (ii) remains active while the simultaneous selection is being performed, and the output from the flip-flop is inactive during a period in which a setting signal and a resetting signal are both being active. This makes it possible to quickly carry out the simultaneous selection of all the signal lines and the initialization of the shift register.
摘要翻译：提供了一种显示驱动电路的移位寄存器，其通过使用同时选择信号来执行多个信号线的同时选择。移位寄存器的一级包括（i）设置复位型触发器和（ii）信号发生电路，其通过响应于触发器的输出选择性地输出信号来产生该级的输出信号。由于同时选择信号的激活，阶段（i）的输出信号变为有效，然后（ii）在执行同时选择时保持有效，并且触发器的输出在其中设定信号和复位信号均处于活动状态。这使得可以快速地执行所有信号线的同时选择和移位寄存器的初始化。

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