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61. 发明授权

US08497201B2 Self-assembly pattern for semiconductor integrated circuit 有权
标题翻译：半导体集成电路的自组装模式
公开(公告)号：US08497201B2
公开(公告)日：2013-07-30
申请号：US13268191
申请日：2011-10-07
申请人： Tsung-Lin Lee , Clement Hsingjen Wann , Ching-Yu Chang
发明人： Tsung-Lin Lee , Clement Hsingjen Wann , Ching-Yu Chang
IPC分类号： H01L21/4763
CPC分类号： H01L21/0337 , H01L21/31144 , H01L21/76816
摘要： A method of fabricating a semiconductor device is provided which includes providing a substrate. A material layer is formed over the substrate. A polymer layer is formed over the material layer. A nano-sized feature is self-assembled using a portion of the polymer layer. The substrate is patterned using the nano-sized feature.
摘要翻译：提供一种制造半导体器件的方法，其包括提供衬底。材料层形成在衬底上。聚合物层形成在材料层上。使用聚合物层的一部分自组装纳米尺寸的特征。使用纳米尺寸的特征对衬底进行图案化。

62. 发明授权

US08338305B2 Multi-fin device by self-aligned castle fin formation 有权
标题翻译：多翅片装置通过自对准城堡鳍形成
公开(公告)号：US08338305B2
公开(公告)日：2012-12-25
申请号：US12907272
申请日：2010-10-19
申请人： Hsin-Chih Chen , Tsung-Lin Lee , Feng Yuan
发明人： Hsin-Chih Chen , Tsung-Lin Lee , Feng Yuan
IPC分类号： H01L21/311
CPC分类号： H01L29/772 , H01L21/3086 , H01L29/66795 , H01L29/785
摘要： The present disclosure provides a method includes forming a multi-fin device. The method includes forming a patterned mask layer on a semiconductor substrate. The patterned mask layer includes a first opening having a first width W1 and a second opening having a second width W2 less than the first width. The patterned mask layer defines a multi-fin device region and an inter-device region, wherein the inter-device region is aligned with the first opening; and the multi-fin device region includes at least one intra-device region being aligned with the second opening. The method further includes forming a material layer on the semiconductor substrate and the patterned mask layer, wherein the material layer substantially fills in the second opening; performing a first etching process self-aligned to remove the material layer within the first opening such that the semiconductor substrate within the first opening is exposed; performing a second etching process to etch the semiconductor substrate within the first opening, forming a first trench in the inter-device region; and thereafter performing a third etching process to remove the material layer in the second opening.
摘要翻译：本公开提供了一种包括形成多翅片装置的方法。该方法包括在半导体衬底上形成图案化掩模层。图案化掩模层包括具有第一宽度W1的第一开口和具有小于第一宽度的第二宽度W2的第二开口。图案化掩模层限定多鳍器件区域和器件间区域，其中器件间区域与第一开口对准; 并且所述多鳍片器件区域包括与所述第二开口对准的至少一个器件内区域。该方法还包括在半导体衬底和图案化掩模层上形成材料层，其中材料层基本上填充在第二开口中; 执行自对准的第一蚀刻工艺以去除第一开口内的材料层，使得第一开口内的半导体衬底被暴露; 执行第二蚀刻工艺以在所述第一开口内蚀刻所述半导体衬底，在所述器件间区域中形成第一沟槽; 然后执行第三蚀刻处理以去除第二开口中的材料层。

63. 发明申请

US20120319211A1 STRAINED CHANNEL FIELD EFFECT TRANSISTOR 有权
标题翻译：应变通道场效应晶体管
公开(公告)号：US20120319211A1
公开(公告)日：2012-12-20
申请号：US13161649
申请日：2011-06-16
申请人： Mark van Dal , Gerben Doornbos , Georgios Vellianitis , Tsung-Lin Lee , Feng Yuan
发明人： Mark van Dal , Gerben Doornbos , Georgios Vellianitis , Tsung-Lin Lee , Feng Yuan
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823821 , H01L27/0924 , H01L29/165 , H01L29/66795 , H01L29/785
摘要： The present disclosure provides a semiconductor device with a strained SiGe channel and a method for fabricating such a device. In an embodiment, a semiconductor device includes a substrate including at least two isolation features, a fin substrate disposed between and above the at least two isolation features, and an epitaxial layer disposed over exposed portions of the fin substrate. According to one aspect, the epitaxial layer may be disposed over a top surface and sidewalls of the fin substrate. According to another aspect, the fin substrate may be disposed substantially completely above the at least two isolation features.
摘要翻译：本公开提供了具有应变SiGe沟道的半导体器件和制造这种器件的方法。在一个实施例中，半导体器件包括包括至少两个隔离特征的衬底，设置在至少两个隔离特征之间和之上的散热片衬底以及设置在散热片衬底的暴露部分之上的外延层。根据一个方面，外延层可以设置在翅片衬底的顶表面和侧壁上。根据另一方面，翅片基板可以基本上完全设置在至少两个隔离特征之上。

64. 发明授权

US08110466B2 Cross OD FinFET patterning 有权
标题翻译：交叉OD FinFET图案化
公开(公告)号：US08110466B2
公开(公告)日：2012-02-07
申请号：US12843728
申请日：2010-07-26
申请人： Ming-Feng Shieh , Tsung-Lin Lee , Chang-Yun Chang
发明人： Ming-Feng Shieh , Tsung-Lin Lee , Chang-Yun Chang
IPC分类号： H01L21/428
CPC分类号： H01L21/823431 , H01L21/845
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; providing a first lithography mask, a second lithography mask, and a third lithography mask; forming a first mask layer over the semiconductor substrate, wherein a pattern of the first mask layer is defined using the first lithography mask; performing a first etch to the semiconductor substrate to define an active region using the first mask layer; forming a second mask layer having a plurality of mask strips over the semiconductor substrate and over the active region; forming a third mask layer over the second mask layer, wherein a middle portion of the plurality of mask strips is exposed through an opening in the third mask layer, and end portions of the plurality of mask strips are covered by the third mask layer; and performing a second etch to the semiconductor substrate through the opening.
摘要翻译：形成集成电路结构的方法包括提供半导体衬底; 提供第一光刻掩模，第二光刻掩模和第三光刻掩模; 在所述半导体衬底上形成第一掩模层，其中使用所述第一光刻掩模限定所述第一掩模层的图案; 对所述半导体衬底执行第一蚀刻以使用所述第一掩模层限定有源区; 在所述半导体衬底上并在所述有源区上形成具有多个掩模条的第二掩模层; 在所述第二掩模层上形成第三掩模层，其中所述多个掩模条的中间部分通过所述第三掩模层中的开口露出，并且所述多个掩模条的端部被所述第三掩模层覆盖; 以及通过所述开口对所述半导体衬底进行第二蚀刻。

65. 发明申请

US20120028477A1 Self-Assembly Pattern for Semiconductor Integrated Circuit 有权
标题翻译：半导体集成电路的自组装模式
公开(公告)号：US20120028477A1
公开(公告)日：2012-02-02
申请号：US13268191
申请日：2011-10-07
申请人： Tsung-Lin Lee , Clement Hsingjen Wann , Ching-Yu Chang
发明人： Tsung-Lin Lee , Clement Hsingjen Wann , Ching-Yu Chang
IPC分类号： H01L21/312
CPC分类号： H01L21/0337 , H01L21/31144 , H01L21/76816
摘要： A method of fabricating a semiconductor device is provided which includes providing a substrate. A material layer is formed over the substrate. A polymer layer is formed over the material layer. A nano-sized feature is self-assembled using a portion of the polymer layer. The substrate is patterned using the nano-sized feature.
摘要翻译：提供一种制造半导体器件的方法，其包括提供衬底。材料层形成在衬底上。聚合物层形成在材料层上。使用聚合物层的一部分自组装纳米尺寸的特征。使用纳米尺寸的特征对衬底进行图案化。

66. 发明申请

US20110097863A1 Cross OD FinFET Patterning 有权
标题翻译：交叉OD FinFET图案
公开(公告)号：US20110097863A1
公开(公告)日：2011-04-28
申请号：US12843728
申请日：2010-07-26
申请人： Ming-Feng Shieh , Tsung-Lin Lee , Chang-Yun Chang
发明人： Ming-Feng Shieh , Tsung-Lin Lee , Chang-Yun Chang
IPC分类号： H01L21/336
CPC分类号： H01L21/823431 , H01L21/845
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; providing a first lithography mask, a second lithography mask, and a third lithography mask; forming a first mask layer over the semiconductor substrate, wherein a pattern of the first mask layer is defined using the first lithography mask; performing a first etch to the semiconductor substrate to define an active region using the first mask layer; forming a second mask layer having a plurality of mask strips over the semiconductor substrate and over the active region; forming a third mask layer over the second mask layer, wherein a middle portion of the plurality of mask strips is exposed through an opening in the third mask layer, and end portions of the plurality of mask strips are covered by the third mask layer; and performing a second etch to the semiconductor substrate through the opening.
摘要翻译：形成集成电路结构的方法包括提供半导体衬底; 提供第一光刻掩模，第二光刻掩模和第三光刻掩模; 在所述半导体衬底上形成第一掩模层，其中使用所述第一光刻掩模限定所述第一掩模层的图案; 对所述半导体衬底执行第一蚀刻以使用所述第一掩模层限定有源区; 在所述半导体衬底上并在所述有源区上形成具有多个掩模条的第二掩模层; 在所述第二掩模层上形成第三掩模层，其中所述多个掩模条的中间部分通过所述第三掩模层中的开口露出，并且所述多个掩模条的端部被所述第三掩模层覆盖; 以及通过所述开口对所述半导体衬底进行第二蚀刻。

67. 发明申请

US20110095372A1 Forming Inter-Device STI Regions and Intra-Device STI Regions Using Different Dielectric Materials 有权
标题翻译：使用不同介质材料形成器件间STI区域和器件内STI区域
公开(公告)号：US20110095372A1
公开(公告)日：2011-04-28
申请号：US12843658
申请日：2010-07-26
申请人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
发明人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
IPC分类号： H01L27/088
CPC分类号： H01L21/76224 , H01L21/76229 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211
摘要： An integrated circuit structure includes a substrate having a first portion in a first device region and a second portion in a second device region; and two insulation regions in the first device region and over the substrate. The two insulation regions include a first dielectric material having a first k value. A semiconductor strip is between and adjoining the two insulation regions, with a top portion of the semiconductor strip forming a semiconductor fin over top surfaces of the two insulation regions. An additional insulation region is in the second device region and over the substrate. The additional insulation region includes a second dielectric material having a second k value greater than the first k value.
摘要翻译：集成电路结构包括具有第一器件区域中的第一部分和第二器件区域中的第二部分的衬底; 以及在第一器件区域和衬底上的两个绝缘区域。两个绝缘区域包括具有第一k值的第一电介质材料。半导体条在两个绝缘区之间并相邻，半导体条的顶部在两个绝缘区的顶表面上形成半导体鳍。另外的绝缘区域位于第二器件区域和衬底之上。附加绝缘区域包括具有大于第一k值的第二k值的第二电介质材料。

68. 发明授权

US07405119B2 Structure and method for a sidewall SONOS memory device 有权
标题翻译：侧壁SONOS存储器件的结构和方法
公开(公告)号：US07405119B2
公开(公告)日：2008-07-29
申请号：US11327185
申请日：2006-01-06
申请人： Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
发明人： Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
IPC分类号： H01L21/8239
CPC分类号： H01L21/28282 , H01L29/4234 , H01L29/66833 , H01L29/7923 , Y10S438/954
摘要： A system and method for a sidewall SONOS memory device is provided. An electronic device includes a non-volatile memory. A substrate includes source/drain regions. A gate stack is directly over the substrate and between the source/drain regions. The gate stack has a sidewall. A nitride spacer is formed adjacent to the gate stack. A first oxide material is formed directly adjacent the spacer. An oxide-nitride-oxide structure is formed between the spacer and the gate stack. The oxide-nitride-oxide structure has a generally L-shaped cross-section on at least one side of the gate stack. The oxide-nitride-oxide structure includes a vertical portion and a horizontal portion. The vertical portion is substantially aligned with the sidewall and located between the first oxide material and the gate sidewall. The horizontal portion is substantially aligned with the substrate and located between the first oxide and the substrate.
摘要翻译：提供了一种用于侧壁SONOS存储器件的系统和方法。电子设备包括非易失性存储器。衬底包括源极/漏极区域。栅极堆叠直接在衬底上并且在源极/漏极区域之间。栅极堆叠具有侧壁。在栅叠层附近形成氮化物间隔物。第一氧化物材料直接邻近间隔物形成。在间隔物和栅极叠层之间形成氧化物 - 氧化物 - 氧化物结构。氧化物 - 氧化物 - 氧化物结构在栅极堆叠的至少一侧具有大致L形的横截面。氧化物 - 氮化物 - 氧化物结构包括垂直部分和水平部分。垂直部分基本上与侧壁对准并且位于第一氧化物材料和栅极侧壁之间。水平部分基本上与衬底对准并位于第一氧化物和衬底之间。

69. 发明申请

US20070161174A1 Manufacturing of memory array and periphery 有权
标题翻译：内存阵列和周边的制造
公开(公告)号：US20070161174A1
公开(公告)日：2007-07-12
申请号：US11529067
申请日：2006-09-28
申请人： Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
发明人： Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/4983 , H01L21/28282 , H01L21/823828 , H01L21/823864 , H01L27/1052 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/517 , H01L29/518 , H01L29/6656 , H01L29/66833 , H01L29/792 , H01L29/7923
摘要： Method of manufacturing a semiconductor chip. An array region gate stack is formed on an array region of a substrate and a periphery region gate stack is formed on a periphery region of a substrate. A first dielectric material, a charge-storing material, and a second dielectric material are deposited over the substrate. Portions of the first dielectric material, the charge-storing material, and the second dielectric material are removed to form storage structures on the array region gate stack and on the periphery region gate stack. The storage structures have a generally L-shaped cross-section. A first source/drain region is formed in the array region well. A third dielectric material and a spacer material are deposited over the substrate. Portions of the third dielectric material and the spacer material are removed to form spacers. A second source/drain region is formed in the periphery region well.
摘要翻译：制造半导体芯片的方法在基板的阵列区域上形成阵列区域栅极叠层，并且在基板的周边区域上形成周边区域栅叠层。在衬底上沉积第一介电材料，电荷存储材料和第二介电材料。去除第一介电材料的部分，电荷存储材料和第二介电材料，以在阵列区域栅极叠层和周边区域栅叠层上形成存储结构。存储结构具有大致L形的横截面。在阵列区域中形成第一源极/漏极区域。在衬底上沉积第三介电材料和间隔物材料。去除第三电介质材料和间隔物材料的部分以形成间隔物。在周边区域中形成第二源极/漏极区域。

70. 发明申请

US20060281254A1 SELF-ALIGNED CONDUCTIVE SPACER PROCESS FOR SIDEWALL CONTROL GATE OF HIGH-SPEED RANDOM ACCESS MEMORY 有权
标题翻译：高速随机存取存储器的门控控制门自对准导通间隔过程
公开(公告)号：US20060281254A1
公开(公告)日：2006-12-14
申请号：US11148342
申请日：2005-06-09
申请人： Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
发明人： Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L21/2815 , H01L21/28273 , H01L29/42324
摘要： A self-aligned conductive spacer process for fabricating sidewall control gates on both sides of a floating gate for high-speed RAM applications, which can well define dimensions and profiles of the sidewall control gates. A conductive layer is formed on the dielectric layer to cover a floating gate patterned on a semiconductor substrate. Oxide spacer are formed on the conductive layer adjacent to the sidewalls of the floating gate. Performing an anisotropic etch process on the conductive layer and using the oxide spacers as a hard mask, a conductive spacers are self-aligned fabricated at both sides of the floating gate, serving as sidewall control gates.
摘要翻译：一种用于在用于高速RAM应用的浮动栅极的两侧上制造侧壁控制栅极的自对准导电间隔物工艺，其可以很好地限定侧壁控制栅极的尺寸和轮廓。在电介质层上形成导电层，以覆盖图案化在半导体衬底上的浮动栅极。在与浮动栅极的侧壁相邻的导电层上形成氧化物间隔物。在导电层上进行各向异性蚀刻处理并使用氧化物间隔物作为硬掩模，导电间隔物在浮栅的两侧制造，用作侧壁控制栅极。

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