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61. 发明授权

US07352247B2 Triple cascode power amplifier of inner parallel configuration with dynamic gate bias technique 失效
标题翻译：具有动态门偏置技术的内部并联配置的三重共源共栅功率放大器
公开(公告)号：US07352247B2
公开(公告)日：2008-04-01
申请号：US11843042
申请日：2007-08-22
申请人： Hyoung-Seok Oh , Hyun-Kyu Yu , Mun-Yang Park , Cheon-Soo Kim
发明人： Hyoung-Seok Oh , Hyun-Kyu Yu , Mun-Yang Park , Cheon-Soo Kim
IPC分类号： H03F3/04
CPC分类号： H03F3/191 , H03F1/223 , H03F1/301 , H03F3/72 , H03F2200/27 , H03F2203/7206
摘要： Provided is a power amplifier which fits to a deep-submicron technology in radio frequency wireless communication. The power amplifier includes a cascode including a first transistor which receives and amplifies an input signal, and a second transistor which is connected to the first transistor in series and operated by a DC bias voltage; a third transistor which is connected between the cascode and an output end, operated by a dynamic gate bias and outputting a signal; and a voltage divider which includes first and second capacitors that are connected between the output end, i.e. a drain of the third transistor, and a ground in series, and provides the dynamic bias to a gate of the third transistor.
摘要翻译：提供了一种适用于射频无线通信中的深亚微米技术的功率放大器。功率放大器包括：共源共栅，包括接收和放大输入信号的第一晶体管;以及第二晶体管，其串联连接到第一晶体管并由DC偏置电压驱动; 连接在共源共栅和输出端之间的第三晶体管，由动态栅极偏置操作并输出信号; 以及分压器，其包括连接在输出端（即，第三晶体管的漏极）和串联的地之间的第一和第二电容器，并且向第三晶体管的栅极提供动态偏置。

62. 发明授权

US07276976B2 Triple cascode power amplifier of inner parallel configuration with dynamic gate bias technique 有权
标题翻译：具有动态门偏置技术的内部并联配置的三重共源共栅功率放大器
公开(公告)号：US07276976B2
公开(公告)日：2007-10-02
申请号：US11267243
申请日：2005-11-04
申请人： Hyoung-Seok Oh , Hyun-Kyu Yu , Mun-Yang Park , Cheon-Soo Kim
发明人： Hyoung-Seok Oh , Hyun-Kyu Yu , Mun-Yang Park , Cheon-Soo Kim
IPC分类号： H03F3/04
CPC分类号： H03F3/191 , H03F1/223 , H03F1/301 , H03F3/72 , H03F2200/27 , H03F2203/7206
摘要： Provided is a power amplifier which fits to a deep-submicron technology in radio frequency wireless communication. The power amplifier includes a cascode including a first transistor which receives and amplifies an input signal, and a second transistor which is connected to the first transistor in series and operated by a DC bias voltage; a third transistor which is connected between the cascode and an output end, operated by a dynamic gate bias and outputting a signal; and a voltage divider which includes first and second capacitors that are connected between the output end, i.e. a drain of the third transistor, and a ground in series, and provides the dynamic bias to a gate of the third transistor.
摘要翻译：提供了一种适用于射频无线通信中的深亚微米技术的功率放大器。功率放大器包括：共源共栅，包括接收和放大输入信号的第一晶体管;以及第二晶体管，其串联连接到第一晶体管并由DC偏置电压驱动; 连接在共源共栅和输出端之间的第三晶体管，由动态栅极偏置操作并输出信号; 以及分压器，其包括连接在输出端（即，第三晶体管的漏极）和串联的地之间的第一和第二电容器，并且向第三晶体管的栅极提供动态偏置。

63. 发明申请

US20060119435A1 Triple cascode power amplifier of inner parallel configuration with dynamic gate bias technique 有权
标题翻译：具有动态门偏置技术的内部并联配置的三重共源共栅功率放大器
公开(公告)号：US20060119435A1
公开(公告)日：2006-06-08
申请号：US11267243
申请日：2005-11-04
申请人： Hyoung-Seok Oh , Hyun-Kyu Yu , Mun-Yang Park , Cheon-Soo Kim
发明人： Hyoung-Seok Oh , Hyun-Kyu Yu , Mun-Yang Park , Cheon-Soo Kim
IPC分类号： H03F1/22
CPC分类号： H03F3/191 , H03F1/223 , H03F1/301 , H03F3/72 , H03F2200/27 , H03F2203/7206
摘要： Provided is a power amplifier which fits to a deep-submicron technology in radio frequency wireless communication. The power amplifier includes a cascode including a first transistor which receives and amplifies an input signal, and a second transistor which is connected to the first transistor in series and operated by a DC bias voltage; a third transistor which is connected between the cascode and an output end, operated by a dynamic gate bias and outputting a signal; and a voltage divider which includes first and second capacitors that are connected between the output end, i.e. a drain of the third transistor, and a ground in series, and provides the dynamic bias to a gate of the third transistor.
摘要翻译：提供了一种适用于射频无线通信中的深亚微米技术的功率放大器。功率放大器包括：共源共栅，包括接收和放大输入信号的第一晶体管;以及第二晶体管，其串联连接到第一晶体管并由DC偏置电压驱动; 连接在共源共栅和输出端之间的第三晶体管，由动态栅极偏置操作并输出信号; 以及分压器，其包括连接在输出端（即，第三晶体管的漏极）和串联的地之间的第一和第二电容器，并且向第三晶体管的栅极提供动态偏置。

64. 发明申请

US20060104399A1 Clock and data recovery apparatus 有权
标题翻译：时钟和数据恢复装置
公开(公告)号：US20060104399A1
公开(公告)日：2006-05-18
申请号：US11280187
申请日：2005-11-15
申请人： Sang-Jin Byun , Hyun-Kyu Yu
发明人： Sang-Jin Byun , Hyun-Kyu Yu
IPC分类号： H03D3/24
CPC分类号： H03L7/107 , H03D13/004 , H03L7/0891 , H03L7/091 , H03L7/0995 , H04L7/033
摘要： A clock and data recovery apparatus reduces current consumption and enables easy integration. The inventive apparatus includes a first loop including a frequency/phase detection unit, a first charge pump unit, a multiplexing unit, a filtering unit, and a voltage controlled oscillator unit operating at a speed ¼ as fast as that of received data; a second loop having a phase detection unit operating at a speed ¼ as fast as a speed of received data, a second charge pump unit suitable for the phase detection unit, the multiplexing unit, the filtering unit, and the voltage controlled oscillator unit; a frequency lock detection unit for judging whether a frequency of a feedback clock signal falls within a desired frequency range; and a data recovery unit for recovering data from received data.
摘要翻译：时钟和数据恢复装置降低了电流消耗并且使得易于集成。本发明的装置包括第一回路，其包括频率/相位检测单元，第一电荷泵单元，复用单元，滤波单元和以与接收数据速度相同的速度运行的压控振荡器单元; 第二回路，其具有以接收数据速度快的速度操作的相位检测单元，适用于相位检测单元的第二电荷泵单元，多路复用单元，滤波单元和压控振荡器单元; 频率锁定检测单元，用于判断反馈时钟信号的频率是否在期望的频率范围内; 以及用于从接收到的数据恢复数据的数据恢复单元。

65. 发明申请

US20060087352A1 Frequency lock detector 有权
标题翻译：频率锁定检测器
公开(公告)号：US20060087352A1
公开(公告)日：2006-04-27
申请号：US11204957
申请日：2005-08-16
申请人： Sang-Jin Byun , Hyun-Kyu Yu
发明人： Sang-Jin Byun , Hyun-Kyu Yu
IPC分类号： H03L7/06
CPC分类号： G01R23/10 , G01R23/005
摘要： Provided is a frequency lock detector which includes one counter and a clock number difference detector for detecting a clock number difference while not increasing complexity according to the counting number N to compare the frequencies of two clock signals whose phases are not synchronous to each other and determine whether the difference between the frequencies of the two signals is within a desired frequency accuracy. The frequency lock detector includes: a counter for counting the number of clocks of a reference clock signal inputted from outside; a clock number difference detector for detecting a difference between the clock number of the reference clock signal and the clock number of a recovered clock signal whose phase is not synchronous to the phase of the reference clock signal; and a lock determiner for determining a frequency lock based on result values of the counter and the clock number difference detector.
摘要翻译：提供一种频率锁定检测器，其包括一个计数器和时钟数差分检测器，用于检测时钟数差，同时根据计数数N不增加复杂度，以比较相位彼此不同步的两个时钟信号的频率，并确定两个信号的频率之间的差异是否在期望的频率精度内。频率锁定检测器包括：用于对从外部输入的参考时钟信号的时钟数进行计数的计数器; 时钟数差检测器，用于检测参考时钟信号的时钟数与其相位与参考时钟信号的相位不同步的恢复时钟信号的时钟数之间的差; 以及锁定确定器，用于基于计数器和时钟数差分检测器的结果值来确定频率锁定。

66. 发明授权

US06620667B2 Method of making a HF LDMOS structure with a trench type sinker 有权
标题翻译：制造具有沟槽型沉降片的HF LDMOS结构的方法
公开(公告)号：US06620667B2
公开(公告)日：2003-09-16
申请号：US10160447
申请日：2002-05-31
申请人： Cheon-Soo Kim , Hyun-Kyu Yu , Nam Hwang , Jung-Woo Park
发明人： Cheon-Soo Kim , Hyun-Kyu Yu , Nam Hwang , Jung-Woo Park
IPC分类号： H01L218234
CPC分类号： H01L29/7835 , H01L29/1087 , H01L29/4175 , H01L29/41766 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an HF power device. The method includes forming a semiconductor layer as a first conductive type on a semiconductor substrate; etching the semiconductor layer forming a first trench; doping an impurity in the neighborhood of the first trench forming a first impurity layer; burying a conduction film into the first trench; etching the semiconductor layer forming a second trench; forming a field oxide film buried into the second trench; forming a gate electrode on a surface of the semiconductor layer; forming a source on the surface of the semiconductor layer; forming a drain area on the surface of the semiconductor layer; forming an LLD area on the surface of the semiconductor layer between the drain area and the gate electrode; forming a first metal electrode; and forming a second metal electrode electrically connected to the LDD area.
摘要翻译：一种形成HF功率器件的方法。该方法包括在半导体衬底上形成作为第一导电类型的半导体层; 蚀刻形成第一沟槽的半导体层; 在形成第一杂质层的第一沟槽附近掺杂杂质; 将导电膜埋入第一沟槽中; 蚀刻形成第二沟槽的半导体层; 形成掩埋在所述第二沟槽中的场氧化膜; 在所述半导体层的表面上形成栅电极; 在半导体层的表面上形成源极; 在所述半导体层的表面上形成漏区; 在漏极区域和栅电极之间的半导体层的表面上形成LLD区域; 形成第一金属电极; 以及形成与LDD区域电连接的第二金属电极。

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