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61. 发明授权

US06438028B1 Semiconductor integrated circuit device, production and operation method thereof 有权
标题翻译：半导体集成电路器件，其生产和操作方法
公开(公告)号：US06438028B1
公开(公告)日：2002-08-20
申请号：US09616072
申请日：2000-07-13
申请人： Takashi Kobayashi , Hideaki Kurata , Naoki Kobayashi , Hitoshi Kume , Katsutaka Kimura , Shunichi Saeki
发明人： Takashi Kobayashi , Hideaki Kurata , Naoki Kobayashi , Hitoshi Kume , Katsutaka Kimura , Shunichi Saeki
IPC分类号： G11C700
CPC分类号： H01L27/11521 , G11C16/0425 , H01L27/115
摘要： In a semiconductor integrated circuit device including a third gate, the present invention improves miniaturization and operation speed and reduces a defect density of an insulator film. In a semiconductor integrated circuit device including a well of a first conductivity type formed in a semiconductor substrate, a source/drain diffusion layer of a second conductivity type inside the well, a floating gate formed over the semiconductor substrate through an insulator film, a control gate formed and isolated from the floating gate through an insulator film, word lines formed by connecting the control gates and a third gate formed and isolated from the semiconductor substrate, the floating gate and the control gate through an insulator film and different from the floating gate and the control gate, the third gate is buried into a space of the floating gates existing in a direction vertical to the word line and a channel.
摘要翻译：在包括第三栅极的半导体集成电路器件中，本发明改进了小型化和操作速度并降低了绝缘膜的缺陷密度。在包括形成在半导体衬底中的第一导电类型阱的阱的半导体集成电路器件中，阱内部具有第二导电类型的源极/漏极扩散层，通过绝缘膜形成在半导体衬底上的浮置栅极，栅极通过绝缘体膜从浮栅形成并隔离，通过连接控制栅极和通过绝缘膜形成并与半导体衬底，浮栅和控制栅极隔离的第三栅极形成的字线并且不同于浮置栅极并且控制栅极，第三栅极被埋在垂直于字线和通道的方向上存在的浮动栅极的空间中。

62. 发明授权

US06255690B1 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US06255690B1
公开(公告)日：2001-07-03
申请号：US09282204
申请日：1999-03-31
申请人： Kazuhiro Komori , Toshiaki Nishimoto , Satoshi Meguro , Hitoshi Kume , Yoshiaki Kamigaki
发明人： Kazuhiro Komori , Toshiaki Nishimoto , Satoshi Meguro , Hitoshi Kume , Yoshiaki Kamigaki
IPC分类号： H01L29788
CPC分类号： H01L27/105 , G11C16/0416 , H01L27/0688 , H01L27/1052 , H01L27/11526 , H01L27/11546 , H01L29/66659 , H01L29/7835 , H01L29/7885 , H01L29/7886
摘要： A semiconductor memory device having nonvolatile memory cells of a single-element type. The nonvolatile memory cells have a floating gate electrode insulatedly on a main surface of a semiconductor substrate and a control gate electrode on the floating gate via a second gate insulating film. An impurity, for example, arsenic, is introduced in self-alignment with the pair of opposing end sides of the control gate electrode to form both the first and second semiconductor regions but, however, a lower dose of arsenic is introduced in the formation of the second semiconductor region. In accordance with the scheme, the first semiconductor region is formed to have a junction depth greater than the junction depth associated with the second semiconductor region and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. Moreover, carriers which are stored in the floating gate electrode are transferred therefrom to the first semiconductor region by tunneling through the insulating film beneath the floating gate electrode.
摘要翻译：一种具有单一元件类型的非易失性存储单元的半导体存储器件。非易失性存储单元通过第二栅极绝缘膜，在半导体衬底的主表面和浮动栅极上的控制栅电极上绝缘地具有浮栅电极。引入与控制栅电极的一对相对端侧自对准的杂质，以形成第一和第二半导体区域，然而，较低剂量的砷被引入到第二半导体区域。根据该方案，第一半导体区域形成为具有大于与第二半导体区域相关联的结深度的结深度，并且第一和第二半导体区域都具有在浮置栅极下方延伸的部分。此外，存储在浮栅电极中的载流子通过隧穿穿过浮置栅电极下方的绝缘膜而从其转移到第一半导体区域。

63. 发明授权

US06201735B1 Electrically erasable and programmable nonvolatile semiconductor memory 有权
标题翻译：电可擦除和可编程的非易失性半导体存储器
公开(公告)号：US06201735B1
公开(公告)日：2001-03-13
申请号：US09362719
申请日：1999-07-29
申请人： Masataka Kato , Tetsuo Adachi , Toshihiro Tanaka , Toshio Sasaki , Hitoshi Kume , Katsutaka Kimura
发明人： Masataka Kato , Tetsuo Adachi , Toshihiro Tanaka , Toshio Sasaki , Hitoshi Kume , Katsutaka Kimura
IPC分类号： G11C1604
CPC分类号： G11C16/0416 , G11C8/08 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/34 , G11C16/3418 , G11C16/3427 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7883 , H01L29/7885
摘要： Each memory cell of a nonvolatile semiconductor memory, essentially, consists of a one-transistor type memory cell such as a MOSFET having a floating gate electrode. When an electric programming operation is carried out, a positive voltage is applied to an n type drain region, a negative voltage is applied to a control gate and a source region is grounded. When an erasing operation is carried out, the positive voltage is applied to the control gate while all the other electrodes and a semiconductor substrate are grounded. Low power consumption can be accomplished because both of the programming operation and erasing operations are carried out by utilizing a tunneling mechanism. Furthermore, because the negative voltage is applied to the word line, a drain voltage at the time of programming of data can be lowered, so that degradation of a gate oxide film at a channel portion can be mitigated.
摘要翻译：非易失性半导体存储器的每个存储单元基本上由诸如具有浮置栅电极的MOSFET的单晶体管型存储单元组成。当执行电编程操作时，向n型漏极区域施加正电压，向控制栅极施加负电压，并且源极区域接地。当执行擦除操作时，正电压被施加到控制栅极，而所有其它电极和半导体衬底接地。可以实现低功耗，因为通过利用隧道机制来执行编程操作和擦除操作两者。此外，因为负电压被施加到字线，所以可以降低编程数据时的漏极电压，从而可以减轻沟道部分处的栅极氧化膜的劣化。

64. 发明授权

US6157576A Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US6157576A
公开(公告)日：2000-12-05
申请号：US393301
申请日：1999-09-10
申请人： Koichi Seki , Takeshi Wada , Tadashi Muto , Kazuyoshi Shoji , Yasurou Kubota , Hitoshi Kume
发明人： Koichi Seki , Takeshi Wada , Tadashi Muto , Kazuyoshi Shoji , Yasurou Kubota , Hitoshi Kume
IPC分类号： G11C16/12 , G11C16/16 , G11C16/30 , G11C16/32 , G11C16/34 , G11C16/04
CPC分类号： G11C16/3445 , G11C16/06 , G11C16/12 , G11C16/16 , G11C16/30 , G11C16/32 , G11C16/344 , G11C2216/20
摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.
摘要翻译：在具有其中电可擦除非易失性存储元件以矩阵形式布置的存储器阵列的EEPROM中，包括擦除控制电路，其在执行擦除操作之后在对应的存储器单元上至少执行一次读出操作根据外部提供的擦除操作指令。擦除操作由内部擦除控制电路自动执行，同时响应于来自微处理器的指令，EEPROM与微处理器电隔离。微处理器的控制只需要稍微短的时间段，在擦除操作期间EEPROM保留在系统中时，指令擦除开始。在本发明的一个方面中，将Vcc电源施加到每个非易失性半导体存储单元的源极区域或漏极区域，并且将具有与Vcc电源的极性相反的极性的擦除电压施加到控制栅极电极。擦除电压被提供给设置在非易失性存储器件内的电压转换电路。因此，可以通过Vcc单电源实现擦除操作。此外，响应于每个存储元件的单独擦除速度，对于每个存储元件或每个集合存储元件单独控制集体擦除操作的实质端子。

65. 发明授权

US6101123A Nonvolatile semiconductor memory with programming and erasing verification 有权
标题翻译：非易失性半导体存储器，具有编程和擦除验证功能
公开(公告)号：US6101123A
公开(公告)日：2000-08-08
申请号：US288313
申请日：1999-04-08
申请人： Masataka Kato , Tetsuo Adachi , Toshihiro Tanaka , Toshio Sasaki , Hitoshi Kume , Katsutaka Kimura
发明人： Masataka Kato , Tetsuo Adachi , Toshihiro Tanaka , Toshio Sasaki , Hitoshi Kume , Katsutaka Kimura
IPC分类号： G11C8/08 , G11C16/04 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： G11C16/0416 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/34 , G11C16/3418 , G11C16/3427 , G11C8/08 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7883 , H01L29/7885
摘要： Each memory cell of a nonvolatile semiconductor memory essentially consisting of a one-transistor type memory cell such as a MOSFET having a floating gate electrode. When an electric programming operation is carried out, a positive voltage is applied to an n type drain region, a negative voltage is applied to a control gate and a source region is grounded. When an erasing operation is carried out, the positive voltage is applied to the control gate while all the other electrodes and a semiconductor substrate are grounded. Low power consumption can be accomplished because both of the programming operation and erasing operations are carried out by utilizing a tunneling mechanism. Particularly because the negative voltage is used for the word line, a drain voltage at the time of programming of data can be lowered, so that degradation of a gate oxide film at a channel portion can be mitigated.
摘要翻译：非易失性半导体存储器的每个存储单元基本上由诸如具有浮置栅电极的MOSFET的单晶体管型存储单元组成。当执行电编程操作时，向n型漏极区域施加正电压，向控制栅极施加负电压，并且源极区域接地。当执行擦除操作时，正电压被施加到控制栅极，而所有其它电极和半导体衬底接地。可以实现低功耗，因为通过利用隧道机制来执行编程操作和擦除操作两者。特别是由于用于字线的负电压，可以降低编程数据时的漏极电压，从而可以减轻沟道部分的栅极氧化膜的劣化。

66. 发明授权

US5932909A Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5932909A
公开(公告)日：1999-08-03
申请号：US851536
申请日：1997-05-05
申请人： Masataka Kato , Tetsuo Adachi , Hitoshi Kume , Shoji Shukuri
发明人： Masataka Kato , Tetsuo Adachi , Hitoshi Kume , Shoji Shukuri
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , Y10S257/90
摘要： A method of manufacturing a nonvolatile semiconductor memory device which is protected against deterioration in the electron injection/discharge characteristics between a floating gate of a memory cell and a channel. Three layers including a gate oxide film, a first polysilicon layer and a first nitride film are sequentially deposited on a silicon substrate surface and patterned with stripe-like columnwise lines. A second nitride film is formed on side walls of the columnwise lines, respectively. An element isolating insulation film is formed on the silicon substrate surface which is not covered with the first and second nitride films. After removal of the first and second nitride films, a first insulation film is formed on the side walls of the first polysilicon layer. Subsequently, at least two layers including a second insulation film and a second polysilicon layer are deposited and a pattern of rowwise lines extending orthogonally to the columnwise lines are formed by processing correspondingly the second polysilicon layer. Even after formation of the element isolating insulation film, thickening of the gate oxide film at distal portions thereof can be suppressed, whereby variations and deterioration in the characteristic of electron injection based on hot electron and tunnel phenomena can be minimized.
摘要翻译：一种制造非易失性半导体存储器件的方法，其被保护以防止存储单元的浮置栅极和沟道之间的电子注入/放电特性的劣化。在硅衬底表面上依次沉积包括栅极氧化膜，第一多晶硅层和第一氮化物膜的三个层，并用条纹状的列线进行图案化。分别在柱状线的侧壁上形成第二氮化物膜。在未被第一和第二氮化物膜覆盖的硅衬底表面上形成元件隔离绝缘膜。在去除第一和第二氮化物膜之后，在第一多晶硅层的侧壁上形成第一绝缘膜。随后，沉积包括第二绝缘膜和第二多晶硅层的至少两层，并且通过相应地处理第二多晶硅层来形成与柱状线垂直延伸的横线的图案。即使在形成元件隔离绝缘膜之后，也可以抑制其远端部分的栅极氧化膜的增厚，从而可以使基于热电子和隧道现象的电子注入特性的变化和劣化最小化。

67. 发明授权

US5781476A Nonvolatile semiconductor memory device 失效
公开(公告)号：US5781476A
公开(公告)日：1998-07-14
申请号：US456797
申请日：1995-06-01
申请人： Koichi Seki , Takeshi Wada , Tadashi Muto , Kazuyoshi Shoji , Yasurou Kubota , Hitoshi Kume
发明人： Koichi Seki , Takeshi Wada , Tadashi Muto , Kazuyoshi Shoji , Yasurou Kubota , Hitoshi Kume
IPC分类号： G11C16/12 , G11C16/16 , G11C16/30 , G11C16/32 , G11C16/34 , G11C11/34
CPC分类号： G11C16/3445 , G11C16/06 , G11C16/12 , G11C16/16 , G11C16/30 , G11C16/32 , G11C16/344 , G11C2216/20
摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

68. 发明授权

US5656522A Method of manufacturing a semiconductor integrated circuit device having single-element type non-volatile memory elements 失效
标题翻译：制造具有单元型非易失性存储元件的半导体集成电路器件的方法
公开(公告)号：US5656522A
公开(公告)日：1997-08-12
申请号：US451268
申请日：1995-05-30
申请人： Kazuhiro Komori , Toshiaki Nishimoto , Satoshi Meguro , Hitoshi Kume , Yoshiaki Kamigaki
发明人： Kazuhiro Komori , Toshiaki Nishimoto , Satoshi Meguro , Hitoshi Kume , Yoshiaki Kamigaki
IPC分类号： H01L21/8247 , H01L27/06 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/11526 , H01L27/11546 , H01L29/66659 , H01L29/7835 , H01L29/7885 , H01L29/7886 , G11C16/0416 , H01L27/0688
摘要： A method of manufacturing a semiconductor memory device having non-volatile memory elements or memory cells of a single-element type. The method provides for the formation of a floating gate electrode on a main surface of a semiconductor substrate and a control gate electrode on the floating gate electrode via a second gate insulating film. In accordance with the method, an impurity is introduced in self-alignment with one of a pair of opposing end portions of the control gate electrode to form a first semiconductor region, and on the second of the opposing end portions of the control gate electrode of the memory cell, the same impurity, for example, arsenic, but, however, of a lower dose is introduced in self-alignment to form a second semiconductor region. In accordance with the formation of the first semiconductor region, the impurity is selectively introduced into the substrate by using a mask layer which covers a portion of the main surface of the substrate where the second semiconductor region is to be formed. In accordance with such manufactured memory cells, carriers which are stored in the floating gate electrode are transferred therefrom to the first semiconductor region by tunneling through the insulating film underlying the floating gate electrode. The first semiconductor region is formed so as to extend in an overlapping relation with the floating gate electrode by a greater amount than that of the second semiconductor region.
摘要翻译：一种制造具有单一元件类型的非易失性存储元件或存储单元的半导体存储器件的方法。该方法提供了通过第二栅极绝缘膜在半导体衬底的主表面上形成浮置栅电极和浮置栅电极上的控制栅电极。根据该方法，与控制栅电极的一对相对端部之一自对准地引入杂质以形成第一半导体区域，并且在控制栅电极的相对端部的第二端部存储单元，相同的杂质，例如砷，但是以较低剂量引入自对准以形成第二半导体区域。根据第一半导体区域的形成，通过使用覆盖要形成第二半导体区域的基板的主表面的一部分的掩模层，将杂质选择性地引入到基板中。根据这种制造的存储单元，通过隧穿穿过浮置栅电极下面的绝缘膜，将存储在浮栅中的载流子从其转移到第一半导体区。第一半导体区域形成为与浮置栅电极重叠地延伸比第二半导体区域大的量。

69. 发明授权

US5602048A Semiconductor integrated circuit device and method of manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US5602048A
公开(公告)日：1997-02-11
申请号：US443036
申请日：1995-05-17
申请人： Kazuhiro Komori , Satoshi Meguro , Toshiaki Nishimoto , Hitoshi Kume , Hideaki Yamamoto
发明人： Kazuhiro Komori , Satoshi Meguro , Toshiaki Nishimoto , Hitoshi Kume , Hideaki Yamamoto
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/105 , H01L29/423
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/105 , H01L27/11546 , H01L29/42324
摘要： An EEPROM (Electrically Erasable Programmable Read Only Memory) has a structure in which the corners of a floating gate electrode of each memory cell MISFET near the source region thereof are rounded.The EEPROM is manufactured by a method characterized in that the ions of an impurity at a high dose are implanted in self-alignment with the floating gate electrode and control gate electrode of the memory cell MISFET so as to form the source and drain regions thereof, whereupon an oxidizing treatment is carried out.
摘要翻译： EEPROM（电可擦除可编程只读存储器）具有其源极区域附近的每个存储单元MISFET的浮置栅极的角部为圆形的结构。通过以下方法制造EEPROM：其特征在于，将高剂量杂质的离子与存储单元MISFET的浮置栅电极和控制栅电极自对准地注入，以形成其源区和漏区，于是进行氧化处理。

70. 发明申请

US20110051515A1 NONVOLATILE SEMICONDUCTOR MEMORY 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20110051515A1
公开(公告)日：2011-03-03
申请号：US12791177
申请日：2010-06-01
申请人： Masataka Kato , Tetsuo Adachi , Toshihiro Tanaka , Toshio Sasaki , Hitoshi Kume , Katsutaka Kimura
发明人： Masataka Kato , Tetsuo Adachi , Toshihiro Tanaka , Toshio Sasaki , Hitoshi Kume , Katsutaka Kimura
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/0416 , G11C8/08 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/34 , G11C16/3418 , G11C16/3427 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7883 , H01L29/7885
摘要： Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.
摘要翻译：公开了一种非易失性存储器系统，包括至少一个非易失性存储器，每个非易失性存储器具有多个非易失性存储单元和缓冲存储器; 以及耦合到所述非易失性存储器的控制装置。控制装置能够接收外部数据并将数据应用于非易失性存储器，并且使非易失性存储器能够操作程序操作，包括将接收到的数据存储到缓冲存储器并将保存在缓冲存储器中的数据存储到缓冲存储器中的非易失性存储单元。此外，控制装置能够在非易失性存储器在程序操作中操作时接收外部数据。此外，缓冲存储器能够接收与程序运行一次要存储的数据的数据长度相等的数据单位，数据长度大于1字节。

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