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61. 发明授权

US09524957B2 Back-to-back stacked dies 有权
标题翻译：背对背堆叠模具
公开(公告)号：US09524957B2
公开(公告)日：2016-12-20
申请号：US13358718
申请日：2012-01-26
申请人： Francois Hebert , Steven R. Rivet , Michael Althar , Peter Oaklander
发明人： Francois Hebert , Steven R. Rivet , Michael Althar , Peter Oaklander
IPC分类号： H01R43/00 , H01L25/16 , H01L23/373 , H01L23/433 , H01L23/495 , H01L23/00 , H01L23/31 , H01L23/64
CPC分类号： H01L25/18 , H01L23/3107 , H01L23/3114 , H01L23/367 , H01L23/3732 , H01L23/4334 , H01L23/49517 , H01L23/49541 , H01L23/49562 , H01L23/49575 , H01L23/645 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L25/16 , H01L2224/05553 , H01L2224/13147 , H01L2224/16245 , H01L2224/291 , H01L2224/2919 , H01L2224/32013 , H01L2224/32145 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48106 , H01L2224/48137 , H01L2224/48247 , H01L2224/48472 , H01L2224/49111 , H01L2224/49171 , H01L2224/73253 , H01L2224/73265 , H01L2224/83801 , H01L2224/83855 , H01L2224/92247 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2225/06589 , H01L2924/01015 , H01L2924/01029 , H01L2924/10162 , H01L2924/12032 , H01L2924/1306 , H01L2924/13064 , H01L2924/13091 , H01L2924/1425 , H01L2924/14253 , H01L2924/1426 , H01L2924/181 , Y10T29/49121 , H01L2924/00012 , H01L2924/00014 , H01L2924/0665 , H01L2924/014 , H01L2924/00
摘要： Embodiments disclosed herein provide for a circuit including first die having an active side and a backside, wherein the first die is flip-chip mounted to a carrier. The circuit also includes a second die stacked on the backside of the first die, wherein the second die is stacked on the first die such that a backside of the second die is facing the backside of the first die and an active side of the second die faces away from the first die.
摘要翻译：本文公开的实施例提供了包括具有有源侧和背侧的第一管芯的电路，其中第一管芯被倒装芯片安装到载体上。电路还包括堆叠在第一管芯的背面上的第二管芯，其中第二管芯堆叠在第一管芯上，使得第二管芯的背面面向第一管芯的背面，第二管芯的有源侧面对远离第一个模具。

62. 发明授权

US08362555B2 Voltage converter and systems including same 失效
标题翻译：电压转换器和系统包括相同
公开(公告)号：US08362555B2
公开(公告)日：2013-01-29
申请号：US12796178
申请日：2010-06-08
申请人： Dev Alok Girdhar , Francois Hebert
发明人： Dev Alok Girdhar , Francois Hebert
IPC分类号： H01L29/66
CPC分类号： H01L27/088
摘要： A voltage converter includes an output circuit having a high side device and a low side device which can be formed on a single die (i.e. a “PowerDie”) and connected to each other through a semiconductor substrate. Both the high side device and the low side device can include lateral diffused metal oxide semiconductor (LDMOS) transistors. Because both output transistors include the same type of transistors, the two devices can be formed simultaneously, thereby reducing the number of photomasks over other voltage converter designs. The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the PowerDie.
摘要翻译：电压转换器包括具有高侧器件和低侧器件的输出电路，其可以形成在单个管芯（即PowerDie）上，并通过半导体衬底相互连接。高侧器件和低侧器件都可以包括横向扩散的金属氧化物半导体（LDMOS）晶体管。因为两个输出晶体管都包含相同类型的晶体管，所以可以同时形成两个器件，从而减少超过其它电压转换器设计的光掩模数量。电压转换器还可以包括在不同的管芯上的控制器电路，其可以与PowerDie电耦合并与其一体化。

63. 发明申请

US20120293474A1 SYSTEMS AND METHODS FOR FACILITATING LIFT-OFF PROCESSES 审中-公开
标题翻译：促进提升过程的系统和方法
公开(公告)号：US20120293474A1
公开(公告)日：2012-11-22
申请号：US13233667
申请日：2011-09-15
申请人： I-Shan Sun , Francois Hebert , Rick Carlton Jerome
发明人： I-Shan Sun , Francois Hebert , Rick Carlton Jerome
IPC分类号： G09G5/10 , B05D1/36 , B05D5/06 , G01J1/42 , G01J1/02
CPC分类号： G01J1/0488 , G01J1/42 , G01J1/4204 , G09G2360/144
摘要： Systems and methods for facilitating lift-off processes are provided. In one embodiment, a method for pattering a thin film on a substrate comprises: depositing a first sacrificial layer of photoresist material onto a substrate such that one or more regions of the substrate are exposed through the first sacrificial layer; depositing a protective layer over at least part of the first sacrificial layer; partially removing the first sacrificial layer to form at least one gap between the protective layer and the substrate; depositing an optical coating over the protective layer and the one or more regions of the substrate exposed through the first sacrificial layer, wherein the optical coating deposited over the protective layer is separated by the at least one gap from the optical coating deposited over the regions of the substrate exposed through the first sacrificial layer; and removing the first sacrificial layer.
摘要翻译：提供了用于促进剥离过程的系统和方法。在一个实施例中，用于在衬底上图案化薄膜的方法包括：将光致抗蚀剂材料的第一牺牲层沉积到衬底上，使得衬底的一个或多个区域通过第一牺牲层暴露; 在第一牺牲层的至少一部分上沉积保护层; 部分地去除所述第一牺牲层以在所述保护层和所述衬底之间形成至少一个间隙; 在所述保护层上沉积光学涂层，并且通过所述第一牺牲层暴露出所述衬底的所述一个或多个区域，其中沉积在所述保护层上的所述光学涂层被所述光学涂层的所述至少一个间隙与沉积在所述衬底通过所述第一牺牲层暴露; 以及去除所述第一牺牲层。

64. 发明申请

US20110260174A1 GaN BASED POWER DEVICES WITH INTEGRATED PROTECTION DEVICES: STRUCTURES AND METHODS 有权
标题翻译：具有集成保护装置的GaN基功率器件：结构和方法
公开(公告)号：US20110260174A1
公开(公告)日：2011-10-27
申请号：US12950202
申请日：2010-11-19
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L29/778 , H01L21/335 , H01L29/12
CPC分类号： H01L27/0255 , H01L21/8258 , H01L27/0629 , H01L27/0688 , H01L29/0619 , H01L29/0653 , H01L29/1075 , H01L29/2003 , H01L29/41766 , H01L29/66136 , H01L29/66143 , H01L29/66462 , H01L29/7786 , H01L29/8611 , H01L29/872
摘要： Exemplary embodiments provide structures and methods for power devices with integrated clamp structures. The integration of clamp structures can protect the power device, e.g., from electrical overstress (EOS). In one embodiment, active devices can be formed over a substrate, while a clamp structure can be integrated outside the active regions of the power device, for example, under the active regions and/or inside the substrate. Integrating clamp structure outside active regions of power devices can maximize the active area for a given die size and improve robustness of the clamped device since the current will spread in the substrate by this integration.
摘要翻译：示例性实施例提供了具有集成钳位结构的功率器件的结构和方法。夹紧结构的集成可以保护功率器件，例如不受电力过应力（EOS）的影响。在一个实施例中，有源器件可以形成在衬底上，而钳位结构可以集成在功率器件的有源区域外部，例如在有源区域下方和/或衬底内部。在功率器件的有源区域之外集成钳位结构可以使给定管芯尺寸的有效面积最大化，并且改善钳位器件的鲁棒性，因为电流将通过该积分在衬底中扩展。

65. 发明申请

US20110180806A1 MONOLITHIC INTEGRATION OF GALLIUM NITRIDE AND SILICON DEVICES AND CIRCUITS, STRUCTURE AND METHOD 有权
标题翻译：氮化镓和硅器件和电路的单晶集成，结构和方法
公开(公告)号：US20110180806A1
公开(公告)日：2011-07-28
申请号：US12946669
申请日：2010-11-15
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L29/20 , H01L21/20
CPC分类号： H01L29/7787 , H01L21/0242 , H01L21/0245 , H01L21/0254 , H01L21/02658 , H01L21/76281 , H01L21/8258 , H01L27/085 , H01L29/2003 , H01L29/66462
摘要： A structure and method for a semiconductor device includes a silicon device layer and a gallium nitride (GaN) device layer. In an embodiment, the silicon device layer and the GaN device layer have upper surfaces which are coplanar with each other. In another embodiment, the GaN device layer does not directly underlie the silicon device layer, and the silicon device layer does not directly underlie the GaN device layer. The semiconductor device can further include a silicon-based semiconductor device formed on and/or within the silicon device layer, and a nitride-based semiconductor device formed on and/or within the GaN device layer. The GaN device layer can include a plurality of layers which can be formed as conformal blanket layers and then planarized, or which can be selectively formed then planarized.
摘要翻译：半导体器件的结构和方法包括硅器件层和氮化镓（GaN）器件层。在一个实施例中，硅器件层和GaN器件层具有彼此共面的上表面。在另一个实施例中，GaN器件层不直接位于硅器件层之下，并且硅器件层不直接位于GaN器件层的下面。半导体器件还可以包括形成在硅器件层上和/或内部的硅基半导体器件，以及形成在GaN器件层上和/或内部的氮化物基半导体器件。 GaN器件层可以包括可以形成为保形覆盖层然后平坦化的多个层，或者可以选择性地形成，然后进行平面化。

66. 发明申请

US20110156679A1 INTEGRATED TRENCH GUARDED SCHOTTKY DIODE COMPATIBLE WITH POWERDIE, STRUCTURE AND METHOD 有权
标题翻译：集成TRENCH保护肖特基二极管兼容POWERDIE，结构和方法
公开(公告)号：US20110156679A1
公开(公告)日：2011-06-30
申请号：US12938589
申请日：2010-11-03
申请人： Dev Alok Girdhar , Francois Hebert
发明人： Dev Alok Girdhar , Francois Hebert
IPC分类号： H01L27/06 , H01L21/336 , G05F1/618
CPC分类号： H01L27/0629 , H01L27/088 , H01L29/4236 , H01L29/66621 , H01L29/7834 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for a voltage converter including a trench field effect transistor (FET) and a trench guarded Schottky diode which is integrated with the trench FET. In an embodiment, a voltage converter can include a lateral FET, a trench FET, and a trench guarded Schottky diode integrated with the trench FET. A method to form a voltage converter can include the formation of a trench FET gate, a trench guarded Schottky diode gate, and a lateral FET gate using a single conductive layer such as a polysilicon layer.
摘要翻译：一种电压转换器的方法和结构，包括与沟槽FET集成的沟槽场效应晶体管（FET）和沟槽保护肖特基二极管。在一个实施例中，电压转换器可以包括横向FET，沟槽FET和与沟槽FET集成的沟槽保护肖特基二极管。形成电压转换器的方法可以包括使用诸如多晶硅层的单个导电层形成沟槽FET栅极，沟槽保护肖特基二极管栅极和横向FET栅极。

67. 发明申请

US20110140126A1 HEAT CONDUCTION FOR CHIP STACKS AND 3-D CIRCUITS 失效
标题翻译：芯片堆叠和三维电路的热传导
公开(公告)号：US20110140126A1
公开(公告)日：2011-06-16
申请号：US12773275
申请日：2010-05-04
申请人： Stephen Joseph Gaul , Francois Hebert
发明人： Stephen Joseph Gaul , Francois Hebert
IPC分类号： H01L23/373 , H01L21/768 , H01L23/48 , H01L21/02
CPC分类号： H01L23/3732 , H01L23/3677 , H01L23/481 , H01L24/05 , H01L24/06 , H01L24/14 , H01L25/0657 , H01L2224/0401 , H01L2224/0603 , H01L2224/06181 , H01L2224/06515 , H01L2224/1403 , H01L2224/14515 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06589 , H01L2924/1305 , H01L2924/13062 , H01L2924/14 , H01L2924/00
摘要： A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities.
摘要翻译：半导体器件组件和方法可以包括单个半导体层或层叠的半导体层，例如半导体晶片或晶片部分（半导体晶片）。在每个半导体层上，通过其形成的金刚石层可有助于散热和散热。金刚石层可以包括半导体层背面的第一部分和垂直延伸到半导体层中的一个或多个第二部分，例如完全穿过半导体层。然后可以对金刚石层进行热接触以将热量从一个或多个半导体层导出。可以通过金刚石层形成导电通孔，以提供信号路由和散热能力。

68. 发明申请

US20110121808A1 VOLTAGE CONVERTER AND SYSTEMS INCLUDING SAME 失效
标题翻译：电压转换器和系统包括相同
公开(公告)号：US20110121808A1
公开(公告)日：2011-05-26
申请号：US12796178
申请日：2010-06-08
申请人： Dev Alok Girdhar , Francois Hebert
发明人： Dev Alok Girdhar , Francois Hebert
IPC分类号： G05F3/02 , H01L21/8234
CPC分类号： H01L27/088
摘要： A voltage converter includes an output circuit having a high side device and a low side device which can be formed on a single die (i.e. a “PowerDie”) and connected to each other through a semiconductor substrate. Both the high side device and the low side device can include lateral diffused metal oxide semiconductor (LDMOS) transistors. Because both output transistors include the same type of transistors, the two devices can be formed simultaneously, thereby reducing the number of photomasks over other voltage converter designs. The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the PowerDie.
摘要翻译：电压转换器包括具有高侧器件的输出电路和可以形成在单个管芯（即“PowerDie”）上并通过半导体衬底相互连接的低侧器件。高侧器件和低侧器件都可以包括横向扩散的金属氧化物半导体（LDMOS）晶体管。因为两个输出晶体管都包含相同类型的晶体管，所以可以同时形成两个器件，从而减少超过其它电压转换器设计的光掩模数量。电压转换器还可以包括在不同的管芯上的控制器电路，其可以与PowerDie电耦合并与其一体化。

69. 发明申请

US20100330754A1 METHODS FOR MANUFACTURING ENHANCEMENT-MODE HEMTS WITH SELF-ALIGNED FIELD PLATE 有权
标题翻译：使用自对准的场板制造增强型模型的方法
公开(公告)号：US20100330754A1
公开(公告)日：2010-12-30
申请号：US12823060
申请日：2010-06-24
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L21/335
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/66462
摘要： Various embodiments of the disclosure include the formation of enhancement-mode (e-mode) gate injection high electron mobility transistors (HEMT). Embodiments can include GaN, AlGaN, and InAlN based HEMTs. Embodiments also can include self-aligned P-type gate and field plate structures. The gates can be self-aligned to the source and drain, which can allow for precise control over the gate-source and gate-drain spacing. Additional embodiments include the addition of a GaN cap structure, an AlGaN buffer layer, AlN, recess etching, and/or using a thin oxidized AlN layer. In manufacturing the HEMTs according to present teachings, selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) can both be utilized to form gates.
摘要翻译：本公开的各种实施例包括形成增强型（e模式）栅极注入高电子迁移率晶体管（HEMT）。实施例可以包括GaN，AlGaN和基于InAlN的HEMT。实施例还可以包括自对准P型门和场板结构。栅极可以与源极和漏极自对准，这可以精确控制栅极源极和栅极 - 漏极间隔。另外的实施例包括添加GaN帽结构，AlGaN缓冲层，AlN，凹陷蚀刻和/或使用薄的氧化AlN层。在根据本教导制造HEMT时，可以利用选择性外延生长（SEG）和外延横向过度生长（ELO）来形成栅极。

70. 发明申请

US20100237416A1 BOTTOM-DRAIN LDMOS POWER MOSFET STRUCTURE HAVING A TOP DRAIN STRAP 有权
标题翻译：底部排水LDMOS功率MOSFET结构具有顶部排水带
公开(公告)号：US20100237416A1
公开(公告)日：2010-09-23
申请号：US12406048
申请日：2009-03-17
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/0649 , H01L29/0653 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/41775 , H01L29/66659 , H01L29/7835
摘要： Lateral DMOS devices having improved drain contact structures and methods for making the devices are disclosed. A semiconductor device comprises a semiconductor substrate; an epitaxial layer on top of the substrate; a drift region at a top surface of the epitaxial layer; a source region at a top surface of the epitaxial layer; a channel region between the source and drift regions; a gate positioned over a gate dielectric on top of the channel region; and a drain contact trench that electrically connects the drift layer and substrate. The contact trench includes a trench formed vertically from the drift region, through the epitaxial layer to the substrate and filled with an electrically conductive drain plug; electrically insulating spacers along sidewalls of the trench; and an electrically conductive drain strap on top of the drain contact trench that electrically connects the drain contact trench to the drift region.
摘要翻译：公开了具有改进的漏极接触结构的侧面DMOS器件和用于制造器件的方法。半导体器件包括半导体衬底; 在衬底的顶部上的外延层; 位于外延层顶表面的漂移区; 在所述外延层的顶表面处的源极区; 源极和漂移区域之间的沟道区域; 栅极位于沟道区域顶部的栅极电介质上; 以及电连接漂移层和衬底的漏极接触沟槽。接触沟槽包括从漂移区垂直形成的沟槽，穿过外延层到衬底并填充有导电排放塞; 沿沟槽侧壁的电绝缘垫片; 以及在漏极接触沟槽的顶部上的导电漏极带，其将漏极接触沟槽电连接到漂移区域。

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