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61. 发明授权

US07366306B1 Programmable logic device that supports secure and non-secure modes of decryption-key access 有权
标题翻译：可编程逻辑器件，支持安全和非安全的解密密钥访问模式
公开(公告)号：US07366306B1
公开(公告)日：2008-04-29
申请号：US10150308
申请日：2002-05-17
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： H04L9/00 , H04L29/00 , H04L9/32
CPC分类号： G06F12/1425 , G06F21/57 , G06F21/79 , G06Q20/3829 , H04L9/0637 , H04L9/0897 , H04L2209/34
摘要： Described are programmable logic devices that decrypt proprietary configuration data using on-chip decryption keys. The keys are stored in a key memory that can be operated in a secure mode or a non-secure mode. The non-secure mode allows the decryption keys to be read or written freely; the secure mode bars read and write access to the decryption keys. The programmable logic device supports secure and non-secure modes on a key-by-key basis, allowing users to write, verify, and erase individual keys without affecting others.
摘要翻译：描述了使用片上解密密钥来解密专有配置数据的可编程逻辑器件。密钥存储在可以以安全模式或非安全模式操作的密钥存储器中。非安全模式允许解密密钥被自由读取或写入; 安全模式可以读取和写入对解密密钥的访问。可编程逻辑器件在逐个密钥的基础上支持安全和非安全模式，允许用户写入，验证和擦除各个密钥，而不影响其他密钥。

62. 发明授权

US07365568B1 Method and circuit for reducing programmable logic pin counts for large scale logic 有权
标题翻译：用于大规模逻辑降低可编程逻辑引脚数的方法和电路
公开(公告)号：US07365568B1
公开(公告)日：2008-04-29
申请号：US11699114
申请日：2007-01-29
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： H03K19/177 , H01L25/00
CPC分类号： H03K19/1732 , H05K1/029 , H05K2201/09127 , H05K2201/10212 , H05K2201/10689
摘要： A circuit board includes a large scale logic device and at least one outrigger device wherein signals having a transmission delay budget that exceed a threshold value are produced to the outrigger device for coupling to circuit devices of the circuit board that are external to the large scale logic device. One embodiment of the invention comprises a plurality of outrigger devices that communicate with the large scale logic device by way of parallel data buses, as well as multi-gigabit transceiver data lines. Logic within the outrigger devices is generally limited to signal routing and transmission logic. The large scale logic device further comprises logic to transmit and receive signals to and from the outrigger devices in a way that is transparent to internal logic of the large scale logic device.
摘要翻译：电路板包括大规模逻辑器件和至少一个外伸支架装置，其中具有超过阈值的传输延迟预算的信号被产生到外伸支架装置，用于耦合到大规模逻辑外部的电路板的电路装置设备。本发明的一个实施例包括通过并行数据总线以及多吉比特收发器数据线与大规模逻辑设备通信的多个外伸支架设备。外伸装置内的逻辑通常限于信号路由和传输逻辑。大规模逻辑设备还包括以对大规模逻辑设备的内部逻辑透明的方式向外伸支架设备发送信号和从外伸支架设备接收信号的逻辑。

63. 发明授权

US07328384B1 Method and apparatus using device defects as an identifier 有权
标题翻译：使用设备缺陷作为标识符的方法和设备
公开(公告)号：US07328384B1
公开(公告)日：2008-02-05
申请号：US11238781
申请日：2005-09-29
申请人： Chidamber R. Kulkarni , Gary R. Lawman , Stephen M. Trimberger
发明人： Chidamber R. Kulkarni , Gary R. Lawman , Stephen M. Trimberger
IPC分类号： G01R31/28
CPC分类号： G01R31/318519
摘要： A method and apparatus that uses device defects as an identifier. Data is written to memory of an integrated circuit. Defects are identified based upon the writing of the data. An identifier for the IC is then derived using the identification of the defects.
摘要翻译：使用设备缺陷作为标识符的方法和装置。数据被写入集成电路的存储器。缺陷根据数据的写入来识别。然后使用缺陷的识别导出IC的标识符。

64. 发明授权

US07284229B1 Multiple bitstreams enabling the use of partially defective programmable integrated circuits while avoiding localized defects therein 有权
标题翻译：多个比特流能够使用部分有缺陷的可编程集成电路，同时避免其中的局部缺陷
公开(公告)号：US07284229B1
公开(公告)日：2007-10-16
申请号：US10957261
申请日：2004-10-01
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Memory devices and data structures including multiple configuration bitstreams for programming integrated circuits (ICs) such as programmable logic devices (PLDs), thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utilizing different programmable resources as much as possible in each configuration bitstream. The resulting configuration bitstreams are stored in a memory device. Test bitstreams associated with the user bitstreams are optionally also included in the memory device. Under the control of a configuration control circuit, the various bitstreams are sequentially loaded into a partially defective IC and tested using an automated testing procedure. When a bitstream is found that enables the design to function correctly in the programmed IC, i.e., that avoids the defective programmable resources in the IC, the configuration procedure terminates. When separate test bitstreams are used, the configuration procedure programs the IC with an associated user bitstream before terminating.
摘要翻译：存储器件和数据结构，包括用于编程集成电路（IC）的多个配置位流，例如可编程逻辑器件（PLD），从而能够利用部分有缺陷的IC。用户设计实现两次或更多次，优选地在每个配置比特流中尽可能多地使用不同的可编程资源。所得到的配置比特流被存储在存储设备中。与用户比特流相关联的测试比特流可选地还包括在存储器设备中。在配置控制电路的控制下，各种比特流被顺序地加载到部分有缺陷的IC中，并使用自动测试程序进行测试。当找到使得设计能够在编程IC中正常工作的比特流，即避免IC中的有缺陷的可编程资源时，配置过程终止。当使用单独的测试比特流时，配置过程在终止之前使用相关联的用户比特流来编程IC。

65. 发明授权

US07250786B1 Method and apparatus for modular redundancy with alternative mode of operation 有权
标题翻译：具有替代操作模式的模块化冗余的方法和装置
公开(公告)号：US07250786B1
公开(公告)日：2007-07-31
申请号：US11184376
申请日：2005-07-19
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： H03K19/003
CPC分类号： H03K19/007
摘要： A method and apparatus to provide triple modular redundancy (TMR) in one mode of operation, while providing multiple context selection during a second mode of operation. Intelligent voting circuitry facilitates both modes of operation, while further enhancing the robustness of the design when used in a TMR mode of operation. Various addressing schemes are provided, which allow dual use of the configuration data lines as selection signals using one addressing scheme, while allowing for dual use of the configuration address lines as selection signals using the second addressing scheme.
摘要翻译：一种在一种操作模式下提供三重模块冗余（TMR）的方法和装置，同时在第二操作模式下提供多个上下文选择。智能投票电路有助于两种操作模式，同时在TMR操作模式下进一步提高设计的鲁棒性。提供了各种寻址方案，其允许使用一种寻址方案将配置数据线双重使用为选择信号，同时允许使用第二寻址方案将配置地址线双重使用为选择信号。

66. 发明授权

US07240320B1 Routing with derivative frame awareness to minimize device programming time and test cost 有权
标题翻译：具有派生框架意识的路由，以最小化设备编程时间和测试成本
公开(公告)号：US07240320B1
公开(公告)日：2007-07-03
申请号：US10989679
申请日：2004-11-16
申请人： Stephen M. Trimberger , Austin H. Lesea , Bernard J. New
发明人： Stephen M. Trimberger , Austin H. Lesea , Bernard J. New
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of implementing a design on a programmable logic device (PLD) includes generating a database that identifies correspondence between resources and programming frames of the PLD. A first PLD design is compiled, wherein the first design uses a first set of resources in a first manner. Costs associated with using the first set of resources of the first design in the first manner are reduced. A second PLD design is then compiled, applying the reduced costs associated with using the first set of resources. A second set of resources required to compile the second design is identified, wherein the second set of resources is not used in the same manner as the first set of resources. A set of programming frames associated with the second set of resources is identified. Costs associated with using a third set of resources associated with the set of programming frames are increased.
摘要翻译：在可编程逻辑器件（PLD）上实现设计的方法包括生成识别PLD的资源和编程帧之间的对应关系的数据库。编译第一PLD设计，其中第一设计以第一方式使用第一组资源。降低了以第一种方式使用第一种设计的第一组资源相关联的成本。然后编制第二PLD设计，应用与使用第一组资源相关联的降低的成本。识别编译第二设计所需的第二组资源，其中第二组资源不以与第一组资源相同的方式使用。识别与第二组资源相关联的一组编程帧。与使用与该组编程帧相关联的第三组资源相关联的成本增加。

67. 发明授权

US07218567B1 Method and apparatus for the protection of sensitive data within an integrated circuit 有权
标题翻译：用于保护集成电路内的敏感数据的方法和装置
公开(公告)号：US07218567B1
公开(公告)日：2007-05-15
申请号：US11234595
申请日：2005-09-23
申请人： Stephen M. Trimberger , Weiguang Lu
发明人： Stephen M. Trimberger , Weiguang Lu
IPC分类号： G11C5/14
CPC分类号： G11C5/141 , G11C7/24 , H03K19/17768
摘要： Methods and apparatus for the protection of memory within an integrated circuit (IC) are provided for various phases of operation of the IC. Various portions of sensitive data may be contained within battery backed random access memory (RAM) (310), which may then be protected using either a passive, or an active, zeroization sequence depending upon the phase of operation of the IC. In an idle state, detection circuit (324) senses a drop in battery power (VBATT) to launch active destruction of RAM (310) memory using active zeroization circuits (312 and 314). In a configuration state, detection circuit (402) or (504) senses a drop in battery power (VBATT) to launch active destruction of RAM (310) memory using active zeroization circuits (312 and 314). In an operational state, various methods may be employed to detect and counteract the unauthorized access to RAM (310).
摘要翻译：为集成电路（IC）中的存储器的保护提供了用于IC的各种操作阶段的方法和装置。敏感数据的各个部分可以包含在电池支持的随机存取存储器（RAM）（310）中，然后根据IC的操作阶段，其可以使用无源或有源零序序列进行保护。在空闲状态下，检测电路（324）感测到使用有源归零电路（312和314）的电池功率的下降（V BAT BAT）以发起RAM（310）存储器的有效破坏。在配置状态下，检测电路（402）或（504）检测电池功率的下降（V BAT BAT）以使用主动归零电路（312和314）来启动RAM（310）存储器的有效破坏，。在操作状态下，可以采用各种方法来检测和抵消未经授权的访问RAM（310）。

68. 发明授权

US07187202B1 Circuit for reducing programmable logic pin counts for large scale logic 有权
标题翻译：用于大规模逻辑的可编程逻辑引脚计数的电路
公开(公告)号：US07187202B1
公开(公告)日：2007-03-06
申请号：US10956210
申请日：2004-09-30
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： H03K19/173 , H01L25/00
CPC分类号： H03K19/1732 , H05K1/029 , H05K2201/09127 , H05K2201/10212 , H05K2201/10689
摘要： A circuit board includes a large scale logic device and at least one outrigger device wherein signals having a transmission delay budget that exceed a threshold value are produced to the outrigger device for coupling to circuit devices of the circuit board that are external to the large scale logic device. One embodiment of the invention comprises a plurality of outrigger devices that communicate with the large scale logic device by way of parallel data buses, as well as multi-gigabit transceiver data lines. Logic within the outrigger devices is generally limited to signal routing and transmission logic. The large scale logic device further comprises logic to transmit and receive signals to and from the outrigger devices in a way that is transparent to internal logic of the large scale logic device.
摘要翻译：电路板包括大规模逻辑器件和至少一个外伸支架装置，其中具有超过阈值的传输延迟预算的信号被产生到外伸支架装置，用于耦合到大规模逻辑外部的电路板的电路装置设备。本发明的一个实施例包括通过并行数据总线以及多吉比特收发器数据线与大规模逻辑设备通信的多个外伸支架设备。外伸装置内的逻辑通常限于信号路由和传输逻辑。大规模逻辑设备还包括以对大规模逻辑设备的内部逻辑透明的方式向外伸支架设备发送信号和从外伸支架设备接收信号的逻辑。

69. 发明授权

US07134025B1 Methods and circuits for preventing the overwriting of memory frames in programmable logic devices 有权
标题翻译：用于防止在可编程逻辑器件中重写存储器帧的方法和电路
公开(公告)号：US07134025B1
公开(公告)日：2006-11-07
申请号：US10146177
申请日：2002-05-14
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： G06F11/30 , G06F12/14 , H04L9/32
CPC分类号： G06F12/1425 , G06F21/57 , G06F21/79 , G06Q20/3829 , H04L9/0637 , H04L9/0897 , H04L2209/34
摘要： Described are various methods and systems for protecting proprietary configuration data for programmable logic devices. In one example, frames of configuration memory include overwrite-protect circuitry that reduces the risks associated with Trojan Horse attacks by preventing the overwriting of frames between device resets.
摘要翻译：描述了用于保护可编程逻辑器件的专有配置数据的各种方法和系统。在一个示例中，配置存储器的帧包括覆盖保护电路，其通过防止在设备复位之间重写帧来降低与特洛伊木马攻击相关的风险。

70. 发明授权

US07047465B1 Methods for using defective programmable logic devices by customizing designs based on recorded defects 有权
标题翻译：通过根据记录的缺陷定制设计来使用有缺陷的可编程逻辑器件的方法
公开(公告)号：US07047465B1
公开(公告)日：2006-05-16
申请号：US10085305
申请日：2002-02-28
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： G01R31/28
CPC分类号： G01R31/2894
摘要： Methods for utilizing PLDs with localized defects. Each PLD has a unique identifier. In one embodiment, a PLD provider tests a series of PLDs, selecting those having localized defects and recording the location of each detected defect for each defective PLD in a defect database. On receiving an identifier from a user, the PLD provider provides to the user the location information for the defects associated with the identified PLD. The data can be received and provided, for example, over the Internet. In one embodiment, the PLD provider implements the design based on the defect locations and provides the resulting design file to the user. In some embodiments, an incremental compilation is performed. The methods of the invention can also be applied to other device-specific information, such as information on the speed of critical sub-components of the PLD.
摘要翻译：利用具有局部缺陷的PLD的方法。每个PLD都有唯一的标识符。在一个实施例中，PLD提供者测试一系列PLD，选择具有局部缺陷的那些，并将每个缺陷PLD的每个检测到的缺陷的位置记录在缺陷数据库中。在从用户接收到标识符的情况下，PLD提供商向用户提供与所识别的PLD相关联的缺陷的位置信息。数据可以例如通过因特网接收和提供。在一个实施例中，PLD提供者基于缺陷位置实现设计，并将所得到的设计文件提供给用户。在一些实施例中，执行增量编译。本发明的方法还可以应用于其他设备特定信息，例如关于PLD的关键子组件的速度的信息。

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