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61. 发明授权

US08601241B2 General purpose register cloning 有权
标题翻译：通用寄存器克隆
公开(公告)号：US08601241B2
公开(公告)日：2013-12-03
申请号：US12024198
申请日：2008-02-01
申请人： Ravi K. Arimilli , Juan C. Rubio , Balaram Sinharoy
发明人： Ravi K. Arimilli , Juan C. Rubio , Balaram Sinharoy
IPC分类号： G06F9/30
CPC分类号： G06F9/30123 , G06F9/3851 , G06F9/462
摘要： A clone set of General Purpose Registers (GPRs) is created to be used by a set of helper thread binaries, which is created from a set of main thread binaries. When the set of main thread binaries enters a wait state, the set of helper thread binaries uses the clone set of GPRs to continue using unused execution units within a processor core. The set of helper threads are thus able to warm up local cache memory with data that will be needed when execution of the set of main thread binaries resumes.
摘要翻译：通用目录寄存器（GPR）的克隆集被创建为由一组主线程二进制文件创建的一组辅助线程二进制文件使用。当主线程二进制文件集进入等待状态时，该组辅助线程二进制文件使用克隆集GPR来继续使用处理器内核中未使用的执行单元。因此，一组辅助线程能够使用在主线程二进制文件集的执行恢复时将需要的数据来预热本地高速缓冲存储器。

62. 发明授权

US08443146B2 Techniques for cache injection in a processor system responsive to a specific instruction sequence 失效
标题翻译：用于响应特定指令序列的处理器系统中缓存注入的技术
公开(公告)号：US08443146B2
公开(公告)日：2013-05-14
申请号：US12212961
申请日：2008-09-18
申请人： Lakshminarayana Baba Arimilli , Ravi K. Arimilli , Balaram Sinharoy
发明人： Lakshminarayana Baba Arimilli , Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0862 , G06F12/0831 , G06F12/0897 , G06F2212/6024
摘要： A technique for performing cache injection includes monitoring an instruction stream for a specific instruction sequence. Addresses on a bus are then monitored, at a cache, in response to detecting the specific instruction sequence a determined number of times. Ownership of input/output data on the bus is then acquired by the cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache.
摘要翻译：用于执行高速缓存注入的技术包括监视特定指令序列的指令流。响应于检测到特定指令序列确定的次数，在总线上的地址被监视在高速缓存。当总线上的地址（与输入/输出数据相关联）对应于存储在高速缓存中的数据块的地址时，总线上的输入/输出数据的所有权由高速缓存获取。

63. 发明授权

US08015380B2 Launching multiple concurrent memory moves via a fully asynchronoous memory mover 失效
标题翻译：通过完全异步的内存移动器启动多个并发内存移动
公开(公告)号：US08015380B2
公开(公告)日：2011-09-06
申请号：US12024690
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3851 , G06F12/10
摘要： A data processing system has an asynchronous memory mover, which includes multiple sets of registers for storing addressing and control parameters utilized to generate one or more asynchronous memory move (AMM) operations. The memory mover detects a receipt of a first set of parameters in a first set of registers from the processor. The processor forwards the parameters after the processor initiates a data move in virtual address space, utilizing a source effective address and a destination effective address. The memory mover responds to receiving the first set of parameters by generating and launching a first asynchronous memory move (AMM) operation. When the memory mover receives a second set of parameters in a second set of registers before the first AMM operation completes, the memory mover generates and launches a second AMM operation concurrently with the first AMM operation if no address conflicts exist.
摘要翻译：数据处理系统具有异步存储器移动器，其包括用于存储用于生成一个或多个异步存储器移动（AMM）操作的寻址和控制参数的多组寄存器。存储器移动器检测来自处理器的第一组寄存器中的第一组参数的接收。处理器在虚拟地址空间中启动数据移动后，使用源有效地址和目标有效地址，处理器转发参数。存储器移动器响应于通过生成和启动第一异步存储器移动（AMM）操作来接收第一组参数。当存储器移动器在第一个AMM操作完成之前在第二组寄存器中接收到第二组参数时，如果不存在地址冲突，则存储器移动器生成并与第一个AMM操作同时启动第二个AMM操作。

64. 发明申请

US20100293359A1 General Purpose Register Cloning 有权
标题翻译：通用寄存器克隆
公开(公告)号：US20100293359A1
公开(公告)日：2010-11-18
申请号：US12024198
申请日：2008-02-01
申请人： Ravi K. Arimilli , Juan C. Rubio , Balaram Sinharoy
发明人： Ravi K. Arimilli , Juan C. Rubio , Balaram Sinharoy
IPC分类号： G06F9/312
CPC分类号： G06F9/30123 , G06F9/3851 , G06F9/462
摘要： A clone set of General Purpose Registers (GPRs) is created to be used by a set of helper thread binaries, which is created from a set of main thread binaries. When the set of main thread binaries enters a wait state, the set of helper thread binaries uses the clone set of GPRs to continue using unused execution units within a processor core. The set of helper threads are thus able to warm up local cache memory with data that will be needed when execution of the set of main thread binaries resumes.
摘要翻译：通用目录寄存器（GPR）的克隆集被创建为由一组主线程二进制文件创建的一组辅助线程二进制文件使用。当主线程二进制文件集进入等待状态时，该组辅助线程二进制文件使用克隆集GPR来继续使用处理器内核中未使用的执行单元。因此，一组辅助线程能够使用在主线程二进制文件集的执行恢复时将需要的数据来预热本地高速缓冲存储器。

65. 发明申请

US20100269118A1 SPECULATIVE POPCOUNT DATA CREATION 有权
标题翻译：统计数据创建数据
公开(公告)号：US20100269118A1
公开(公告)日：2010-10-21
申请号：US12425343
申请日：2009-04-16
申请人： Ravi K. Arimilli , Ronald N. Kalla , Balaram Sinharoy
发明人： Ravi K. Arimilli , Ronald N. Kalla , Balaram Sinharoy
IPC分类号： G06F9/46 , G06F9/44 , G06F12/00
CPC分类号： G06F9/3001 , G06F9/30018 , G06F9/3842
摘要： A method and a data processing system by which population count (popcount) operations are efficiently performed without incurring the latency and loss of critical processing cycles and bandwidth of real time processing. The method comprises: identifying data to be stored to memory for which a popcount may need to be determined; speculatively performing a popcount operation on the data as a background process of the processor while the data is being stored to memory; storing the data to a first memory location; and storing a value of the popcount generated by the popcount operation within a second memory location. The method further comprises: determining a size of data; determining a granular level at which the popcount operation on the data will be performed; and reserving a size of said second memory location that is sufficiently large to hold the value of the popcount.
摘要翻译：一种方法和数据处理系统，通过该方法和数据处理系统有效地执行人口计数（popcount）操作，而不会导致关键处理周期的延迟和丢失以及实时处理的带宽。该方法包括：识别要存储到可能需要确定一个弹出窗口的存储器的数据; 在将数据存储到存储器中的情况下，作为处理器的后台处理推测性地对数据进行弹出数据操作; 将数据存储到第一存储器位置; 以及将由所述popcount操作生成的所述popcount的值存储在第二存储器位置内。该方法还包括：确定数据的大小; 确定将执行对数据的弹出数据操作的粒度级别; 以及保留所述第二存储器位置的大小足够大以保持所述用户名的值。

66. 发明申请

US20100153938A1 Computation Table For Block Computation 有权
标题翻译：块计算计算表
公开(公告)号：US20100153938A1
公开(公告)日：2010-06-17
申请号：US12336332
申请日：2008-12-16
申请人： Ravi K. Arimilli , Balaram Sinharoy
发明人： Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F9/45
CPC分类号： G06F8/4441
摘要： In response to receiving pre-processed code, a compiler identifies a code section that is not candidate for acceleration and identifying a code block specifying an iterated operation that is a candidate for acceleration. In response to identifying the code section, the compiler generates post-processed code containing one or more lower level instructions corresponding to the identified code section, and in response to identifying the code block, the compiler creates and outputs an operation data structure separate from the post-processed code that identifies the iterated operation. The compiler places a block computation command in the post-processed code that invokes processing of the operation data structure to perform the iterated operation and outputs the post-processed code.
摘要翻译：响应于接收预处理的代码，编译器识别不是加速候选的代码段，并且识别指定作为加速候选的迭代操作的代码块。响应于识别代码部分，编译器生成包含与识别的代码部分相对应的一个或多个较低级别指令的后处理代码，并且响应于识别代码块，编译器创建并输出与标识迭代操作的后处理代码。编译器在后处理代码中放置块计算命令，该代码调用操作数据结构的处理以执行迭代操作，并输出后处理代码。

67. 发明申请

US20100153931A1 Operand Data Structure For Block Computation 有权
标题翻译：块计算的操作数数据结构
公开(公告)号：US20100153931A1
公开(公告)日：2010-06-17
申请号：US12336301
申请日：2008-12-16
申请人： Ravi K. Arimilli , Balaram Sinharoy
发明人： Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F9/45
CPC分类号： G06F8/4441 , G06F8/447
摘要： In response to receiving pre-processed code, a compiler identifies a code section that is not a candidate for acceleration and a code block that is a candidate for acceleration. The code block specifies an iterated operation having a first operand and a second operand, where each of multiple first operands and each of multiple second operands for the iterated operation has a defined addressing relationship. In response to the identifying, the compiler generates post-processed code containing lower level instruction(s) corresponding to the identified code section and creates and outputs an operand data structure separate from the post-processed code. The operand data structure specifies the defined addressing relationship for the multiple first operands and for the multiple second operands. The compiler places a block computation command in the post-processed code that invokes processing of the operand data structure to compute operand addresses.
摘要翻译：响应于接收预处理的代码，编译器识别不是加速候选的代码段和作为加速候选的代码块。代码块指定具有第一操作数和第二操作数的迭代操作，其中迭代操作的多个第一操作数和多个第二操作数中的每一个具有定义的寻址关系。响应于识别，编译器生成包含对应于所识别的代码段的较低级别指令的后处理代码，并创建并输出与后处理代码分离的操作数数据结构。操作数数据结构指定多个第一个操作数和多个第二个操作数的定义的寻址关系。编译器在后处理代码中放置块计算命令，该代码调用操作数数据结构的处理以计算操作数地址。

68. 发明申请

US20100070712A1 Techniques for Cache Injection in a Processor System with Replacement Policy Position Modification 失效
标题翻译：具有更换政策位置修改的处理器系统中缓存注入的技术
公开(公告)号：US20100070712A1
公开(公告)日：2010-03-18
申请号：US12212977
申请日：2008-09-18
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F12/08 , G06F13/28
CPC分类号： G06F12/0862 , G06F12/0835 , G06F12/127 , G06F2212/6028
摘要： A technique for performing cache injection includes monitoring, at a cache, addresses on a bus. Ownership of input/output data on the bus is then acquired by the cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache. A replacement policy position of the data block is then modified (to increase a probability that the data block is consumed prior to ejection from the cache).
摘要翻译：用于执行高速缓存注入的技术包括在缓存上监视总线上的地址。当总线上的地址（与输入/输出数据相关联）对应于存储在高速缓存中的数据块的地址时，总线上的输入/输出数据的所有权由高速缓存获取。然后修改数据块的替换策略位置（以增加数据块在从高速缓存弹出之前消耗的概率）。

69. 发明申请

US20100070710A1 Techniques for Cache Injection in a Processor System 有权
标题翻译：处理器系统中缓存注入的技术
公开(公告)号：US20100070710A1
公开(公告)日：2010-03-18
申请号：US12212917
申请日：2008-09-18
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F12/08 , G06F12/00 , G06F13/28
CPC分类号： G06F13/28 , G06F12/0835 , G06F2212/507 , G06F2212/621
摘要： A technique for performing cache injection includes monitoring addresses on a bus. Ownership of input/output data on the bus is acquired by a cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache.
摘要翻译：执行高速缓存注入的技术包括监视总线上的地址。当总线上的地址（与输入/输出数据相关联）对应于存储在高速缓存中的数据块的地址时，通过高速缓存获取总线上的输入/输出数据的所有权。

70. 发明申请

US20090199181A1 Use of a Helper Thread to Asynchronously Compute Incoming Data 有权
标题翻译：使用助手线程异步计算进来的数据
公开(公告)号：US20090199181A1
公开(公告)日：2009-08-06
申请号：US12024228
申请日：2008-02-01
申请人： Ravi K. Arimilli , Juan C. Rubio , Balaram Sinharoy
发明人： Ravi K. Arimilli , Juan C. Rubio , Balaram Sinharoy
IPC分类号： G06F9/46
CPC分类号： G06F9/544 , G06F9/4843
摘要： A set of helper thread binaries is created from a set of main thread binaries. The helper thread monitors software or hardware ports for incoming data events. When the helper thread detects an incoming event, the helper thread asynchronously executes instructions that calculate incoming data needed by the main thread.
摘要翻译：一组辅助线程二进制文件是从一组主线程二进制文件创建的。辅助线程监视输入数据事件的软件或硬件端口。当辅助线程检测到传入事件时，辅助线程异步执行计算主线程所需的传入数据的指令。

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