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61. 发明授权

US5565816A Clock distribution network 失效
标题翻译：时钟分配网络
公开(公告)号：US5565816A
公开(公告)日：1996-10-15
申请号：US516735
申请日：1995-08-18
申请人： Paul W. Coteus
发明人： Paul W. Coteus
IPC分类号： G06F1/10 , H03K5/15 , H03L7/07 , H03K3/00 , H03K5/13 , H03L7/18
CPC分类号： G06F1/10 , H03K5/1506 , H03L7/07
摘要： A clock distribution network for synchronously coupled electronic communication systems that includes a clock distribution device having a phase locked loop for synchronizing the external clock signals provided to each semiconductive device with each other. The clock distribution device distributes a low speed clock to a large number of clocked semiconductor devices where those devices then internally generate high speed clocks in phase with the low speed clock. The low speed clocks are phase shifted with respect to each other to reduce radiated energy. The ratio of internal to external clock speed is also communicated to each chip so that the chips can be programmed to operate with a variety of external clock speeds. The phase shifting of the external clock to different chips is provided so that the chips can still communicate synchronously at the high speed internal clock.
摘要翻译：一种用于同步耦合电子通信系统的时钟分配网络，其包括具有用于使提供给每个半导体装置的外部时钟信号彼此同步的锁相环的时钟分配装置。时钟分配器件将低速时钟分配给大量的时钟半导体器件，在那些器件内部将与低速时钟同相内部生成高速时钟。低速时钟相对于彼此相移以减少辐射能量。内部与外部时钟速度的比率也传达到每个芯片，使得芯片可以被编程为以各种外部时钟速度运行。提供外部时钟到不同芯片的相移，使得芯片仍然可以在高速内部时钟同步地通信。

62. 发明授权

US5537476A Secure viewing of display units by image superposition and wavelength separation 失效
标题翻译：通过图像叠加和波长分离安全观看显示单元
公开(公告)号：US5537476A
公开(公告)日：1996-07-16
申请号：US342514
申请日：1994-11-21
申请人： Paul W. Coteus , Douglas S. Goodman
发明人： Paul W. Coteus , Douglas S. Goodman
IPC分类号： G09C5/00 , H04N13/00 , H04L9/00
CPC分类号： H04N13/0422 , G09C5/00 , H04N13/0431 , H04N13/0434 , H04N13/0443 , H04N13/0459
摘要： Apparatus for masking a displayed image by mixing the image with a secondary image that is electronically generated to be related to the primary image that when combined with the primary image obscures viewing of the primary image. The primary image is generated in the form of a first set of wavelength bands and the secondary image is a second set of related wavelength bands. A filter is provided to absorb the second set of wavelength bands to permit secure viewing of the primary image.
摘要翻译：用于通过将图像与电子产生的与主图像相关的次要图像混合来掩蔽所显示的图像的装置，当与主图像组合时，该图像掩盖了主图像的观看。主图像以第一组波长带的形式产生，次要图像是第二组相关波长带。提供滤波器以吸收第二组波长带以允许主图像的安全观看。

63. 发明授权

US09137098B2 T-Star interconnection network topology 有权
标题翻译： T星互连网络拓扑
公开(公告)号：US09137098B2
公开(公告)日：2015-09-15
申请号：US13584300
申请日：2012-08-13
申请人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Philip Heidelberger , Robert M. Senger , Yutaka Sugawara
发明人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Philip Heidelberger , Robert M. Senger , Yutaka Sugawara
IPC分类号： H04L12/715 , H04L12/24
CPC分类号： H04L41/0663 , H04L41/12 , H04L41/145 , H04L45/04
摘要： According to one embodiment of the present invention, a method of constructing network communication for a grid of node groups is provided, the grid including an M dimensional grid, each node group including N nodes, wherein M is greater than or equal to one and N is greater than one, wherein each node includes a router. The method includes directly connecting each node in each node group to every other node in the node group via intra-group links and directly connecting each node in each node group of the M dimensional grid to a node in each neighboring node group in the M dimensional grid via inter-group links.
摘要翻译：根据本发明的一个实施例，提供了一种为节点组网格构建网络通信的方法，所述网格包括M维网格，每个节点组包括N个节点，其中M大于或等于1，并且N 大于1，其中每个节点包括路由器。该方法包括通过组内链路将每个节点组中的每个节点直接连接到节点组中的每个其他节点，并将M维网格的每个节点组中的每个节点直接连接到M维中的每个相邻节点组中的节点网格通过组间链接。

64. 发明授权

US08909878B2 Implementing timing alignment and synchronized memory activities of multiple memory devices accessed in parallel 有权
标题翻译：实现并行访问的多个存储器设备的时序校准和同步存储器活动
公开(公告)号：US08909878B2
公开(公告)日：2014-12-09
申请号：US13494280
申请日：2012-06-12
申请人： Paul W. Coteus , Kyu-hyoun Kim
发明人： Paul W. Coteus , Kyu-hyoun Kim
IPC分类号： G06F12/00
CPC分类号： G11C29/26 , G06F13/1684 , G06F13/1689 , G11C29/023 , G11C29/028 , G11C2029/2602
摘要： A method and circuit for implementing synchronized memory activities of multiple memory devices being accessed in parallel, and a design structure on which the subject circuit resides are provided. Each memory circuit generates an internal status signal for predefined internal memory activities and provides an output signal coupled to the multiple memory devices. Each memory circuit monitors the generated internal status signal and the output signal of at least one of the multiple memory devices, and responsive to the monitored signals generates a control signal for adjusting operation of its memory activities to synchronize memory activities of the memory devices.
摘要翻译：一种用于实现并行访问的多个存储器件的同步存储器活动的方法和电路，以及设置有被摄体电路的设计结构。每个存储器电路产生用于预定义的内部存储器活动的内部状态信号，并提供耦合到多个存储器件的输出信号。每个存储器电路监视生成的内部状态信号和多个存储器件中的至少一个的输出信号，并且响应于所监视的信号产生用于调整其存储器活动的操作以控制存储器件的存储器活动的控制信号。

65. 发明授权

US08667049B2 Massively parallel supercomputer 有权
标题翻译：大容量并行超级计算机
公开(公告)号：US08667049B2
公开(公告)日：2014-03-04
申请号：US13566024
申请日：2012-08-03
申请人： Matthias A. Blumrich , Dong Chen , George L. Chiu , Thomas M. Cipolla , Paul W. Coteus , Alan G. Gara , Mark E. Giampap , Philip Heidlberger , Gerard V. Kopcsay , Lawrence S. Mok , Todd E. Takken
发明人： Matthias A. Blumrich , Dong Chen , George L. Chiu , Thomas M. Cipolla , Paul W. Coteus , Alan G. Gara , Mark E. Giampap , Philip Heidlberger , Gerard V. Kopcsay , Lawrence S. Mok , Todd E. Takken
IPC分类号： G06F15/173
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node individually or simultaneously work on any combination of computation or communication as required by the particular algorithm being solved. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. The multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions.
摘要翻译：数百个teraOPS级别的新型大规模并行超级计算机包括基于片上系统技术的节点架构，即每个处理节点包括单个专用集成电路（ASIC）。在每个ASIC节点内是多个处理元件，每个处理元件由中央处理单元（CPU）和多个浮点处理器组成，以实现计算性能，封装密度，低成本以及功率和冷却要求的最佳平衡。单个节点内的多个处理器单独或同时工作在要解决的特定算法所要求的计算或通信的任何组合上。片上系统ASIC节点通过多个独立网络互连，从而最大限度地最大限度地提高了分组通信吞吐量并最大限度地减少了延迟。多个网络包括用于并行算法消息传递的三个高速网络，包括Torus，全局树和提供全局障碍和通知功能的全球异步网络。

66. 发明申请

US20140044015A1 T-STAR INTERCONNECTION NETWORK TOPOLOGY 审中-公开
标题翻译： T-STAR互联网络拓扑
公开(公告)号：US20140044015A1
公开(公告)日：2014-02-13
申请号：US13584300
申请日：2012-08-13
申请人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Philip Heidelberger , Robert M. Senger , Yutaka Sugawara
发明人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Philip Heidelberger , Robert M. Senger , Yutaka Sugawara
IPC分类号： H04L12/28
CPC分类号： H04L41/0663 , H04L41/12 , H04L41/145 , H04L45/04
摘要： According to one embodiment of the present invention, a method of constructing network communication for a grid of node groups is provided, the grid including an M dimensional grid, each node group including N nodes, wherein M is greater than or equal to one and N is greater than one, wherein each node includes a router. The method includes directly connecting each node in each node group to every other node in the node group via intra-group links and directly connecting each node in each node group of the M dimensional grid to a node in each neighboring node group in the M dimensional grid via inter-group links.
摘要翻译：根据本发明的一个实施例，提供了一种为节点组网格构建网络通信的方法，所述网格包括M维网格，每个节点组包括N个节点，其中M大于或等于1，并且N 大于1，其中每个节点包括路由器。该方法包括通过组内链路将每个节点组中的每个节点直接连接到节点组中的每个其他节点，并将M维网格的每个节点组中的每个节点直接连接到M维中的每个相邻节点组中的节点网格通过组间链接。

67. 发明授权

US08626957B2 Collective network for computer structures 有权
标题翻译：计算机结构集体网络
公开(公告)号：US08626957B2
公开(公告)日：2014-01-07
申请号：US13101566
申请日：2011-05-05
申请人： Matthias A. Blumrich , Paul W. Coteus , Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Todd E. Takken , Burkhard D. Steinmacher-Burow , Pavlos M. Vranas
发明人： Matthias A. Blumrich , Paul W. Coteus , Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Todd E. Takken , Burkhard D. Steinmacher-Burow , Pavlos M. Vranas
IPC分类号： G06F15/16
CPC分类号： H04L1/08 , G06F9/46 , G06F11/08 , G06F11/1423 , H03M13/09 , H04L1/0061 , H04L1/1607 , H04L1/1867 , H04L2001/0093 , H04L2001/0097
摘要： A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.
摘要翻译：一种用于实现互连处理节点之间的高速，低延迟全局集体通信的系统和方法。全局集体网络最优地使得能够在具有多个互连处理节点的计算机结构中执行并行算法操作期间执行集体缩减操作。包括通过链路互连网络节点的路由器设备，以便于在虚拟网络的节点处执行低延迟全局处理操作。全局集体网络可以被配置为以异步或同步方式提供全局屏障和中断功能。当在大规模并行超级计算结构中实现时，全局集体网络根据处理算法的需要在物理上和逻辑上可分割。

68. 发明授权

US08595554B2 Reproducibility in a multiprocessor system 有权
标题翻译：多处理器系统中的重现性
公开(公告)号：US08595554B2
公开(公告)日：2013-11-26
申请号：US12774475
申请日：2010-05-05
申请人： Ralph A. Bellofatto , Dong Chen , Paul W. Coteus , Noel A. Eisley , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Philip Heidelberger , Gerard V. Kopcsay , Thomas A. Liebsch , Martin Ohmacht , Don D. Reed , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
发明人： Ralph A. Bellofatto , Dong Chen , Paul W. Coteus , Noel A. Eisley , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Philip Heidelberger , Gerard V. Kopcsay , Thomas A. Liebsch , Martin Ohmacht , Don D. Reed , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
IPC分类号： G06F11/00
CPC分类号： G06F1/10 , G06F11/2242
摘要： Fixing a problem is usually greatly aided if the problem is reproducible. To ensure reproducibility of a multiprocessor system, the following aspects are proposed: a deterministic system start state, a single system clock, phase alignment of clocks in the system, system-wide synchronization events, reproducible execution of system components, deterministic chip interfaces, zero-impact communication with the system, precise stop of the system and a scan of the system state.
摘要翻译：如果问题是可重现的，通常会大大帮助解决问题。为了确保多处理器系统的可重复性，提出了以下方面：确定性系统启动状态，单个系统时钟，系统中的时钟相位对齐，全系统同步事件，系统组件的可重复执行，确定性芯片接口，零 - 与系统进行通信，精确地停止系统并扫描系统状态。

69. 发明授权

US08549363B2 Reliability and performance of a system-on-a-chip by predictive wear-out based activation of functional components 失效
标题翻译：通过基于功能组件的预先磨损的激活来实现片上系统的可靠性和性能
公开(公告)号：US08549363B2
公开(公告)日：2013-10-01
申请号：US12727967
申请日：2010-03-19
申请人： Chen-Yong Cher , Paul W. Coteus , Alan Gara , Eren Kursun , David P. Paulsen , Brian A. Schuelke , John E. Sheets, II , Shurong Tian
发明人： Chen-Yong Cher , Paul W. Coteus , Alan Gara , Eren Kursun , David P. Paulsen , Brian A. Schuelke , John E. Sheets, II , Shurong Tian
IPC分类号： G06F11/30
CPC分类号： G06F17/5045 , G01R31/31725
摘要： A processor-implemented method for determining aging of a processing unit in a processor the method comprising: calculating an effective aging profile for the processing unit wherein the effective aging profile quantifies the effects of aging on the processing unit; combining the effective aging profile with process variation data, actual workload data and operating conditions data for the processing unit; and determining aging through an aging sensor of the processing unit using the effective aging profile, the process variation data, the actual workload data, architectural characteristics and redundancy data, and the operating conditions data for the processing unit.
摘要翻译：一种用于确定处理器中处理单元的老化的处理器实现的方法，该方法包括：计算处理单元的有效老化简档，其中有效老化简档量化老化对处理单元的影响; 将有效的老化轮廓与处理单元的过程变化数据，实际工作负载数据和操作条件数据相结合; 以及通过所述处理单元的老化传感器使用所述有效老化简档，所述过程变化数据，所述实际工作负载数据，架构特征和冗余数据以及所述处理单元的操作条件数据来确定老化。

70. 发明授权

US08359521B2 Providing a memory device having a shared error feedback pin 有权
标题翻译：提供具有共享错误反馈引脚的存储器件
公开(公告)号：US08359521B2
公开(公告)日：2013-01-22
申请号：US12018030
申请日：2008-01-22
申请人： Kyu-hyoun Kim , Paul W. Coteus , Timothy J. Dell
发明人： Kyu-hyoun Kim , Paul W. Coteus , Timothy J. Dell
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G06F11/1004
摘要： A system and method for providing a memory device having a shared error feedback pin. The system includes a memory device having a data interface configured to receive data bits and CRC bits, CRC receiving circuitry, CRC creation circuitry, a memory device pad, and driver circuitry. The CRC receiving circuitry utilizes a CRC equation for the detection of errors in one or more of the received data and the received CRC bits. The CRC creation circuitry utilizes the CRC equation for the creation of CRC bits consistent with data to be transmitted to a separate device bits. The memory device pad is configured for reporting of any errors detected in the received data and the received CRC bits. The driver circuitry is connected to the memory device pad and merged with one or more other driver circuitries resident on one or more other memory devices into an error reporting line.
摘要翻译：一种用于提供具有共享错误反馈引脚的存储器件的系统和方法。该系统包括具有被配置为接收数据比特和CRC比特，CRC接收电路，CRC创建电路，存储器装置垫和驱动器电路的数据接口的存储器装置。 CRC接收电路利用CRC方程来检测一个或多个接收数据和接收的CRC比特中的错误。 CRC创建电路利用CRC方程来创建与要发送到单独设备位的数据一致的CRC位。存储器件焊盘被配置为报告在接收的数据和接收的CRC位中检测到的任何错误。驱动器电路连接到存储器件焊盘并与驻留在一个或多个其它存储器件上的一个或多个其它驱动器电路合并到错误报告行中。

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