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61. 发明授权

US06246422B1 Efficient method for storing texture maps in multi-bank memory 有权
标题翻译：将纹理贴图存储在多行存储器中的高效方法
公开(公告)号：US06246422B1
公开(公告)日：2001-06-12
申请号：US09144863
申请日：1998-09-01
申请人： Brian Emberling , Michael G. Lavelle
发明人： Brian Emberling , Michael G. Lavelle
IPC分类号： G06T1140
CPC分类号： G06F12/0607 , G06T15/04
摘要： A method for storing mip map series in a multi-bank texture memory is disclosed. Each mip map has a different size and represents a different resolution version of a texture map image that is to be mapped onto a three dimensional object comprising one or more polygons. To prevent page faults when accessing corresponding texels in consecutive mip maps, each mip map is divided in two halves. The halves are stored in different banks of the multi-bank texture memory. The banks used are alternated so that corresponding texels in consecutive mip maps are stored in different memory banks. Mip maps may be categorized as large or small, with all small mip maps after the first being stored in their entirety in one memory bank. Small mip maps are those that are equal to or smaller than the page size of the multi-bank texture memory. A computer system, graphics subsystem, and software program capable to efficiently store mip map series in a multi-bank texture memories are also disclosed.
摘要翻译：公开了一种在多组织纹理存储器中存储mip映射序列的方法。每个mip映射具有不同的大小，并且表示要映射到包括一个或多个多边形的三维对象的纹理映射图像的不同分辨率版本。为了防止在连续的mip地图访问相应的纹素时出现页面错误，每个mip映射被分成两半。一半存储在多银行纹理存储器的不同库中。使用的存储体是交替的，使得连续mip映射中的相应纹素被存储在不同的存储体中。 Mip地图可能被分类为大或小，所有小的mip地图首先被全部存储在一个存储器中。小的mip映射是等于或小于多存储库纹理存储器的页面大小的映射。还公开了能够有效地将mip映射序列存储在多存储体纹理存储器中的计算机系统，图形子系统和软件程序。

62. 发明授权

US6141741A Computer system with a shared address bus and pipelined write operations 失效
标题翻译：具有共享地址总线和流水线写入操作的计算机系统
公开(公告)号：US6141741A
公开(公告)日：2000-10-31
申请号：US705057
申请日：1996-08-29
申请人： Curtis Priem , Satyanarayana Nishtala , Michael G. Lavelle , Thomas Webber , Daniel E. Lenoski , Peter A. Mehring , Guy Moffat , Christopher R. Owen
发明人： Curtis Priem , Satyanarayana Nishtala , Michael G. Lavelle , Thomas Webber , Daniel E. Lenoski , Peter A. Mehring , Guy Moffat , Christopher R. Owen
IPC分类号： G06F12/02 , G06F13/16 , G06F13/36 , G06F13/42 , G06F12/00
CPC分类号： G06F12/0215 , G06F13/161 , G06F13/1615
摘要： A computer system with a multiplexed address bus that is shared by both system memory and by slave devices is described. The slave devices are incorporated into an existing system memory configuration by providing a bus controller to execute a two-cycle address sequence on the multiplexed address bus. The address sequence is followed by a transfer of data. A random latency can exist between the time of receiving address information and the time of receiving data corresponding to the address information. This random latency can be exploited by the system CPU for other computational purposes. The bus controller of the system executes multiple, or pipelined, data writes to the bus before an acknowledgement for the first data write is received. In this scheme, the acknowledgement for the first data write is typically sent during the same time period that the subsequent data writes are being received. Consequently, data transfer acknowledgements overlap data writes. This overlapping operation allows the bus to be completely utilized during write operations, thereby improving data bandwidth.
摘要翻译：描述了由系统存储器和从设备共享的具有多路复用地址总线的计算机系统。通过提供总线控制器来在多路复用地址总线上执行两周期地址序列，将从设备并入现有系统存储器配置。地址序列之后是数据传输。在接收地址信息的时间和接收与地址信息对应的数据的时间之间可以存在随机延迟。这个随机延迟可以被系统CPU用于其他计算目的。在接收到第一个数据写入的确认之前，系统的总线控制器在总线上执行多个或流水线的数据写入。在该方案中，通常在接收后续数据写入的相同时间段期间发送对第一数据写入的确认。因此，数据传输确认与数据写入重叠。这种重叠操作允许在写入操作期间完全利用总线，从而提高数据带宽。

63. 发明授权

US5544306A Flexible dram access in a frame buffer memory and system 失效
标题翻译：在一个帧缓冲存储器和系统中灵活的电脑访问
公开(公告)号：US5544306A
公开(公告)日：1996-08-06
申请号：US237307
申请日：1994-05-03
申请人： Michael F. Deering , Stephen A. Schlapp , Michael G. Lavelle
发明人： Michael F. Deering , Stephen A. Schlapp , Michael G. Lavelle
IPC分类号： G06T1/60 , G06F12/08 , G06T11/00 , G06T15/40 , G09G5/39 , G09G5/399 , G06F12/00
CPC分类号： G09G5/39 , G06T15/405 , G06F12/0875 , G09G2340/10 , G09G2360/121 , G09G2360/123 , G09G2360/126
摘要： A frame buffer dynamic random access memory (FBRAM) is disclosed that enables accelerated rendering of Z-buffered graphics primitives. The FBRAM converts read-modify-write transactions such as Z-buffer compare and RBG alpha blending into a write only operation. The FBRAM also implements two levels of internal pixel caches, and a four-way interleaved frame buffer.
摘要翻译：公开了一种帧缓冲器动态随机存取存储器（FBRAM），其实现了Z缓冲图形基元的加速渲染。 FBRAM将读取 - 修改 - 写入事务（如Z缓冲区比较和RBG alpha混合）转换为只写操作。 FBRAM还实现了两级内部像素高速缓存和四路交错帧缓冲器。

64. 发明授权

US08593468B2 Scalable high performance 3D graphics 有权
标题翻译：可扩展的高性能3D图形
公开(公告)号：US08593468B2
公开(公告)日：2013-11-26
申请号：US12898249
申请日：2010-10-05
申请人： Michael F. Deering , Michael G. Lavelle
发明人： Michael F. Deering , Michael G. Lavelle
IPC分类号： G06F13/14 , G06F12/02 , G06T1/20
CPC分类号： G06T1/20 , G06T1/60 , G06T5/002 , G06T15/005
摘要： A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).
摘要翻译：高速环形拓扑。在一个实施例中，需要两种基本芯片类型：“绘图”芯片，LoopDraw和“接口”芯片，LoopInterface。每个芯片都有一组引脚，支持相同的高速点对点输入和输出环互连接口：LoopLink。 LoopDraw芯片使用额外的引脚连接到形成高带宽本地存储器子系统的多个标准存储器。 LoopInterface芯片使用额外的引脚来支持高速主机主机接口，至少一个视频输出接口，以及可能与其他LoopInterface芯片的附加非本地互连。

65. 发明申请

US20080148063A1 Method and apparatus for content protection within an open architecture system 有权
标题翻译：开放式架构系统内容保护的方法和装置
公开(公告)号：US20080148063A1
公开(公告)日：2008-06-19
申请号：US10679055
申请日：2003-10-03
申请人： James G. Hanko , Michael G. Lavelle , James D. Lyle , J. Duane Northcutt
发明人： James G. Hanko , Michael G. Lavelle , James D. Lyle , J. Duane Northcutt
IPC分类号： G06F12/14
CPC分类号： H04N5/913 , G06F21/10 , G06F21/85 , G11B20/00086 , G11B20/0021 , H04L63/0464 , H04L63/0823 , H04L63/0869 , H04L2463/101 , H04N7/088 , H04N7/1675 , H04N21/2541 , H04N21/4334 , H04N21/4367 , H04N21/4405 , H04N21/4408 , H04N21/4627 , H04N21/835
摘要： In a class of embodiments, the invention is an open computing system (e.g., a PC) in which a protected, closed subsystem is embedded. The closed subsystem typically includes multiple parts that ensure that content protection keys and protected content are never revealed outside the closed subsystem. Content (e.g., high-definition digital video) that enters the closed subsystem (and is typically decrypted and re-encrypted within the closed subsystem) is afforded a similar level of protection within the open system as can be obtained in standalone closed systems. Other aspects of the invention are methods for protecting content within an open computing system, a closed system (or disk drive thereof) configured to be embedded in an open computing system, and circuitry configured to be embedded in an open computing system for combining the output of a closed subsystem with other output (e.g., graphics and/or audio output) of the open computing system.
摘要翻译：在一类实施例中，本发明是其中嵌入了受保护的封闭子系统的开放式计算系统（例如，PC）。封闭的子系统通常包括多个部分，确保内容保护密钥和受保护内容永远不会在封闭子系统外部显示。进入封闭子系统（并且通常在封闭子系统内被解密并重新加密）的内容（例如，高清数字视频）在独立的封闭系统中可获得与开放系统相似的保护水平。本发明的其他方面是用于保护开放式计算系统内的内容的方法，被配置为嵌入在开放式计算系统中的封闭系统（或其盘驱动器）以及被配置为嵌入开放式计算系统中的组合的输出的方法，具有开放式计算系统的其他输出（例如，图形和/或音频输出）的封闭子系统。

66. 发明授权

US06999087B2 Dynamically adjusting sample density in a graphics system 有权
公开(公告)号：US06999087B2
公开(公告)日：2006-02-14
申请号：US10383165
申请日：2003-03-06
申请人： Michael G. Lavelle , Justin Michael Mahan
发明人： Michael G. Lavelle , Justin Michael Mahan
IPC分类号： G06F12/02
CPC分类号： G06T15/005 , G09G5/006 , G09G5/363 , G09G5/397 , G09G2340/0442 , G09G2340/0464 , G09G2360/08 , G09G2360/18
摘要： A graphics system may include a frame buffer and a hardware accelerator. The frame buffer may include a sample buffer and a double-buffered display area. The hardware accelerator may be coupled to the frame buffer, and configured (a) to receive primitives, (b) to generate samples for the primitives based on a dynamically adjustable sample density value, (c) to write the samples into the sample buffer, (d) to read the samples from the sample buffer, (e) to filter the samples to generate pixels, (f) to store the pixels in a back buffer of the double-buffered display area. A host computer may be configured (e.g., by means of stored program instructions) to dynamically update programmable registers of the graphics system to reallocate the sample buffer in the frame buffer in response to user input specifying a change in one or more window size parameters.

67. 发明授权

US06975322B2 Dynamically adjusting a number of rendering passes in a graphics system 有权
标题翻译：动态调整图形系统中的渲染通过次数
公开(公告)号：US06975322B2
公开(公告)日：2005-12-13
申请号：US10383234
申请日：2003-03-06
申请人： Michael G. Lavelle
发明人： Michael G. Lavelle
IPC分类号： G06T15/00 , G06F12/02 , G09G5/399
CPC分类号： G06T15/005
摘要： A graphics system includes a hardware accelerator and a frame buffer. The frame buffer includes a sample storage area and a double-buffered display pixel area. The hardware accelerator is operable to (a) render a stream of primitives into samples, (b) store the samples into the sample storage area of the frame buffer, (c) read the samples from the sample storage area, (d) filter the samples to generate pixels, and (e) store the pixels into a first buffer of the display pixel area of the frame buffer. Furthermore, the hardware accelerator is operable to perform (a), (b), (c), (d) and (e) one or more times on one or more corresponding streams of primitives to complete a frame of an animation before passing control of the first buffer to a video output processor.
摘要翻译：图形系统包括硬件加速器和帧缓冲器。帧缓冲器包括样本存储区域和双缓冲显示像素区域。硬件加速器可操作以（a）将原始流渲染为样本，（b）将样本存储到帧缓冲器的样本存储区域中，（c）从样本存储区域读取样本，（d）过滤用于生成像素的样本，以及（e）将像素存储到帧缓冲器的显示像素区域的第一缓冲器中。此外，硬件加速器可操作地在一个或多个相应的图元流上执行（a），（b），（c），（d）和（e）一次或多次以在通过控制之前完成动画的帧的第一个缓冲区到视频输出处理器。

68. 发明授权

US06847378B2 System and method for performing scale and bias operations by preclamping input image data 有权
标题翻译：通过预压缩输入图像数据进行缩放和偏移操作的系统和方法
公开(公告)号：US06847378B2
公开(公告)日：2005-01-25
申请号：US10093364
申请日：2002-03-07
申请人： Ranjit S. Oberoi , Michael G. Lavelle , Anthony S. Ramirez
发明人： Ranjit S. Oberoi , Michael G. Lavelle , Anthony S. Ramirez
IPC分类号： G06T3/40 , G09G5/36 , G09G5/02
CPC分类号： G06T3/4007 , G09G5/363
摘要： In one embodiment, a scale and bias unit for use in a graphics system includes a preclamping unit configured to receive an input and to responsively generate an output value equal to a first value if the input is within a first input range. The scale and bias unit also includes a processing unit coupled to the preclamping unit and configured to perform a calculation on the input to generate the output value. The processing unit does not perform the calculation if the input is within the first input range.
摘要翻译：在一个实施例中，用于图形系统的比例尺和偏置单元包括预压缩单元，其被配置为接收输入并且如果输入在第一输入范围内则响应地产生等于第一值的输出值。缩放和偏置单元还包括耦合到预压单元并被配置为对输入执行计算以产生输出值的处理单元。如果输入在第一输入范围内，则处理单元不执行计算。

69. 发明授权

US06816161B2 Vertex assembly buffer and primitive launch buffer 有权
标题翻译：顶点汇编缓冲区和原始启动缓冲区
公开(公告)号：US06816161B2
公开(公告)日：2004-11-09
申请号：US10060969
申请日：2002-01-30
申请人： Michael G. Lavelle , Huang Pan , Anthony S. Ramirez
发明人： Michael G. Lavelle , Huang Pan , Anthony S. Ramirez
IPC分类号： G06F1300
CPC分类号： G06T15/005
摘要： A graphics system and method for processing geometry compressed, three-dimensional graphics data are disclosed. After transforming and lighting each vertex, a vertex data stream is decompressed using connectivity information, and vertexes are reassembled into geometric primitives. The connectivity information may include mesh buffer references, vertex tags, or other types of information. Independent buffers, queues, and/or caches are used to simultaneously store: (a) vertex data for the next several primitives, (b) vertex data that will be reused, (c) vertex tags, (d) control tags, (e) vertex data being assembled into a primitive, and (f) an assembled primitive ready to be launched. The assembled primitive may be clip tested for visibility in a defined viewport, before investing time to have the primitive processed into pixel data for display. The independent buffers, queues, and/or caches may also enable the vertex processing steps to be performed in parallel and at different rates.
摘要翻译：公开了用于处理几何压缩的三维图形数据的图形系统和方法。在对每个顶点进行变换和点亮之后，使用连通性信息解压缩顶点数据流，并将顶点重新组合成几何图元。连接信息可以包括网格缓冲器引用，顶点标签或其他类型的信息。独立缓冲区，队列和/或高速缓存用于同时存储：（a）下一个原语的顶点数据，（b）将被重用的顶点数据，（c）顶点标签，（d）控制标签，（e ）顶点数据被组装成原始图形，（f）准备启动的组合原始图形。在投入时间以将原始图像处理成像素数据进行显示之前，组合的原始图像可以在定义的视口中进行剪辑测试。独立缓冲器，队列和/或高速缓存也可以使顶点处理步骤以并行且不同的速率执行。

70. 发明授权

US06812928B2 Performance texture mapping by combining requests for image data 有权
标题翻译：通过组合图像数据请求来执行纹理映射
公开(公告)号：US06812928B2
公开(公告)日：2004-11-02
申请号：US10060978
申请日：2002-01-30
申请人： Brian D. Emberling , Michael G. Lavelle
发明人： Brian D. Emberling , Michael G. Lavelle
IPC分类号： G09G539
CPC分类号： G09G5/39 , G06T1/60 , G06T15/04 , G09G2320/0285 , G09G2360/122 , G09G2360/128
摘要： An optimizing unit for use with an interleaved memory and suitable for use in a computer graphics system is described. The unit utilizes knowledge of the repetitive and predictable nature of texture buffer accesses to potentially reduce the number of memory fetches. The unit maintains a queue of pending requests for tiles of data from the memory, and predicts the retrieval of redundant data within short sequences of requests. The redundant data is retrieved from the memory once, and repeated as necessary from local temporary storage registers.
摘要翻译：描述了一种用于交错存储器并适用于计算机图形系统的优化单元。该单元利用纹理缓冲器访问的重复性和可预测性质的知识来潜在地减少存储器提取的数量。该单元维护来自存储器的数据块的待处理请求队列，并且预测在短序列请求内检索冗余数据。冗余数据从存储器中检索一次，并根据需要从本地临时存储寄存器重复。

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