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61. 发明申请

US20120002478A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120002478A1
公开(公告)日：2012-01-05
申请号：US13236300
申请日：2011-09-19
申请人： Katsuaki Isobe , Masatsugu Kojima
发明人： Katsuaki Isobe , Masatsugu Kojima
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/30 , G11C16/225
摘要： When a voltage level detector detects that a supply voltage reaches a recovery voltage level that requires a recovery operation, a signal generator generates a recovery operation instructing signal for instructing the recovery operation. The recovery operation instructing signal is invalidated if a certain operation mode is executed and validated in other cases.
摘要翻译：当电压电平检测器检测到电源电压达到需要恢复操作的恢复电压电平时，信号发生器产生用于指示恢复操作的恢复操作指令信号。如果某些操作模式在其他情况下被执行和验证，则恢复操作指令信号无效。

62. 发明授权

US08089818B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08089818B2
公开(公告)日：2012-01-03
申请号：US12580795
申请日：2009-10-16
申请人： Hideo Mukai , Hiroshi Maejima , Katsuaki Isobe
发明人： Hideo Mukai , Hiroshi Maejima , Katsuaki Isobe
IPC分类号： G11C7/10
CPC分类号： G11C8/14 , G11C7/18 , G11C8/12 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0028 , G11C2213/31 , G11C2213/72
摘要： A nonvolatile-semiconductor-memory-device including a cell array having a plurality of MATs (unit-cell-array) disposed in a matrix, the MATs each include a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells being connected between the first and second lines. The device further includes a first and second drive circuit selecting the first and second lines connected to the memory cells of each MAT that are accessed, and driving the selected first and second lines to write or read data. The memory cells form a page by being connected to each first line selected from the MATs. The device also includes a data latch latching the write or the read data in units of pages, where the first and second drive circuit drive the first and second lines multiple times to write or read data for one page in and out of the cell array.
摘要翻译：一种非易失性半导体存储器件，包括具有以矩阵形式设置的多个MAT（单位阵列）的单元阵列，所述MAT各包括多条第一线，与第一线交叉的多条第二线，以及存储单元连接在第一和第二线之间。该装置还包括第一和第二驱动电路，选择连接到每个MAT的存储器单元的第一和第二线，所述存储器单元被访问，并且驱动所选择的第一和第二行来写入或读取数据。存储单元通过连接到从MAT中选择的每个第一行形成页面。该设备还包括以页为单位锁存写入或读取数据的数据锁存器，其中第一和第二驱动电路多次驱动第一和第二行以写入或读取单元阵列中的一页的数据。

63. 发明申请

US20110128775A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND DATA WRITING METHOD THEREFOR 有权
标题翻译：非易失性半导体存储器件及其数据写入方法
公开(公告)号：US20110128775A1
公开(公告)日：2011-06-02
申请号：US13024926
申请日：2011-02-10
申请人： Hiroshi MAEJIMA , Katsuaki Isobe , Hideo Mukai
发明人： Hiroshi MAEJIMA , Katsuaki Isobe , Hideo Mukai
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C7/00 , G11C13/0004 , G11C13/0011 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2213/31 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile semiconductor storage device comprises: a first wire and a second wire intersecting each other; a memory cell which is disposed at each intersection of the first wire and the second wire and electrically rewritable and in which a variable resistor for memorizing a resistance value as data in a nonvolatile manner and a rectifying device are connected in series; and a control circuit which applies a voltage necessary for writing of data to the first and second wires. The control circuit precharges a non-selected second wire up to a standby voltage larger than a reference voltage prior to a set operation for programming only a variable resistor connected to selected first and second wires by supplying the reference voltage to a non-selected first wire and the selected second wire, applying a program voltage necessary for programming of the selected variable resistor based on the reference voltage to the selected first wire and applying a control voltage which prevents the rectifying device from turning ON based on the program voltage to the non-selected second wire.
摘要翻译：非易失性半导体存储装置包括：第一线和彼此交叉的第二线; 存储单元，其配置在所述第一配线和所述第二配线的各交叉点并且是电可重写的，并且其中存储用作非易失性数据的电阻值的可变电阻器和整流装置串联连接; 以及控制电路，其向第一和第二导线施加写入数据所需的电压。控制电路在设置操作之前将未选择的第二线预充电到大于参考电压的待机电压，以仅通过将参考电压提供给未选择的第一线来仅编程连接到所选择的第一和第二线的可变电阻器和所选择的第二线路，基于参考电压将所选择的可变电阻器编程所需的编程电压施加到所选择的第一线路，并施加防止整流装置导通的控制电压，选择第二根线。

64. 发明申请

US20100329026A1 SEMICONDUCTOR MEMORY DEVICE WITH CHARGE ACCUMULATION LAYER 审中-公开
标题翻译：具有充电累积层的半导体存储器件
公开(公告)号：US20100329026A1
公开(公告)日：2010-12-30
申请号：US12822703
申请日：2010-06-24
申请人： Mitsutoshi NAKAMURA , Takeshi Shimane , Michiru Hogyoku , Katsuaki Isobe , Naoyuki Shigyo
发明人： Mitsutoshi NAKAMURA , Takeshi Shimane , Michiru Hogyoku , Katsuaki Isobe , Naoyuki Shigyo
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/26 , G11C7/04 , G11C11/5642 , G11C16/0483 , G11C16/3454 , G11C2211/5621
摘要： According to one embodiment, a semiconductor memory device includes memory cells, first and second selection transistors, a source line, a temperature monitor, and a source line voltage controller. The memory cells are connected in series between a source of the first selection transistor and a drain of the second selection transistor. The temperature monitor monitors a temperature of the semiconductor substrate. The source line voltage controller applies a voltage to the source line, in a read operation, in such a manner that a potential difference between the source line and the semiconductor substrate increases according to a rise in the temperature monitored by the temperature monitor and that a reverse bias is applied between the source of the second selection transistor and the semiconductor substrate.
摘要翻译：根据一个实施例，半导体存储器件包括存储器单元，第一和第二选择晶体管，源极线，温度监视器和源极线电压控制器。存储单元串联连接在第一选择晶体管的源极和第二选择晶体管的漏极之间。温度监视器监视半导体衬底的温度。源极线电压控制器在读取操作中以源极线和半导体衬底之间的电位差随着由温度监视器监测的温度的升高而增加的电压施加电压，在第二选择晶体管的源极和半导体衬底之间施加反向偏压。

65. 发明授权

US07656225B2 Voltage generation circuit and semiconductor memory device including the same 有权
标题翻译：电压产生电路和包括其的半导体存储器件
公开(公告)号：US07656225B2
公开(公告)日：2010-02-02
申请号：US11739397
申请日：2007-04-24
申请人： Katsuaki Isobe , Noboru Shibata
发明人： Katsuaki Isobe , Noboru Shibata
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G11C7/14 , G11C5/147
摘要： A voltage generation circuit comprises a reference voltage generation circuit; a differential amplifier; an output node; a P-channel MOS transistor; a first resistor series; a second resistor series; a third resistor series; and a selection control circuit. A reference voltage generated by the reference voltage generation circuit is input to a first input terminal of the differential amplifier. The first resistor series is connected between a drain of the P-channel MOS transistor and the output node. The second resistor series is connected between the output node and a second input terminal of the differential amplifier. The third resistor array is connected between the second input terminal of the differential amplifier and a ground. The selection control circuit controls such that a sum of the resistances of the first resistor series and the second resistor series is constant.
摘要翻译：电压产生电路包括参考电压产生电路; 差分放大器; 输出节点; P沟道MOS晶体管; 第一个电阻器系列; 第二个电阻器系列; 第三电阻器系列; 和选择控制电路。由参考电压产生电路产生的参考电压被输入到差分放大器的第一输入端。第一个电阻器系列连接在P沟道MOS晶体管的漏极和输出节点之间。第二电阻器系列连接在差分放大器的输出节点和第二输入端子之间。第三电阻阵列连接在差分放大器的第二输入端和地之间。选择控制电路控制使得第一电阻器系列和第二电阻器系列的电阻之和恒定。

66. 发明申请

US20090237979A1 SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM 有权
标题翻译：半导体存储器件和半导体存储器系统
公开(公告)号：US20090237979A1
公开(公告)日：2009-09-24
申请号：US12408232
申请日：2009-03-20
申请人： Hideo Mukai , Hiroshi Maejima , Satoru Takase , Naoya Tokiwa , Katsuaki Isobe
发明人： Hideo Mukai , Hiroshi Maejima , Satoru Takase , Naoya Tokiwa , Katsuaki Isobe
IPC分类号： G11C11/00 , G11C7/22
CPC分类号： G11C8/10 , G11C7/18 , G11C7/22 , G11C8/08 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0028 , G11C13/0069 , G11C2013/0076 , G11C2207/2263 , G11C2211/5647 , G11C2213/31 , G11C2213/56 , G11C2213/72
摘要： A semiconduct or memory device comprises a memory cell array including a plurality of memory cells arranged at intersections of word lines and bit lines; a read/write circuit operative to execute data read/write to the memory cell; and an operational circuit operative to compare certain length data read out by the read/write circuit from plural ones of the memory cells with certain length data to be written in the plural memory cells to make a decision, and create a flag representing the decision result. The read/write circuit inverts each bit in the certain length data to be written in the memory cells in accordance with the flag, and writes only rewrite-intended data of the certain length data and the flag. The read/write circuit reads the certain length data together with the flag corresponding thereto, and inverts each bit in the certain length data in accordance with the flag.
摘要翻译：半导体或存储器件包括存储单元阵列，其包括布置在字线和位线的交点处的多个存储单元; 读/写电路，用于执行对存储器单元的数据读/写; 以及操作电路，用于将来自多个存储器单元的读/写电路读出的某些长度数据与要写入多个存储器单元的一定长度数据进行比较，并作出决定，并创建表示决定结果的标志。读/写电路根据该标志反转要写入存储单元的一定长度数据中的每个位，并且仅写入特定长度数据和标志的重写预期数据。读/写电路读取与其对应的标志一定的长度数据，并根据该标志反转一定长度数据中的每一位。

67. 发明申请

US20090174032A1 RESISTANCE CHANGE MEMORY DEVICE 审中-公开
标题翻译：电阻变化存储器件
公开(公告)号：US20090174032A1
公开(公告)日：2009-07-09
申请号：US12351212
申请日：2009-01-09
申请人： Hiroshi MAEJIMA , Katsuaki Isobe , Hideo Mukai
发明人： Hiroshi MAEJIMA , Katsuaki Isobe , Hideo Mukai
IPC分类号： H01L29/00
CPC分类号： G11C13/00 , G11C13/0069 , G11C2013/0073 , G11C2213/71 , G11C2213/72 , H01L27/24
摘要： A resistance change memory device includes: a semiconductor substrate; a three dimensional cell array formed by a plurality of unit cell array blocks of two dimensional arrangement on the semiconductor substrate, the unit cell array block being formed by stacking a plurality of unit cell arrays including a first wiring, a second wiring crossing with the first wiring, and a variable resistance element connected at an intersection of the both wirings; a reading/writing/driving circuit formed on the semiconductor substrate under the three dimensional cell array; a first via region which is arranged in an end portion of the unit cell array block, and in which a via wiring for connecting the first wiring in each layer to the reading/writing/driving circuit is formed; and a second via region which is arranged in an end portion of the unit cell array block, and in which a via wiring for connecting the second wiring in each layer to the reading/writing/driving circuit is formed. When the first wiring is longer than the second wiring, the number of via arrangements in the first via region is set larger than that in the second via region.
摘要翻译：电阻变化存储器件包括：半导体衬底; 由半导体衬底上的二维排列的多个单元阵列块形成的三维单元阵列，所述单元阵列块通过堆叠多个单元阵列而形成，所述单位阵列包括第一布线，与所述第一布线交叉的第二布线布线和连接在两条布线的交点处的可变电阻元件; 在三维单元阵列下形成在半导体衬底上的读/写/驱动电路; 布置在单元阵列块的端部中的第一通孔区域，其中形成用于将每层中的第一布线连接到读/写/驱动电路的通孔布线; 以及布置在单元阵列块的端部中的第二通孔区域，并且其中形成用于将每层中的第二布线连接到读/写/驱动电路的通孔布线。当第一布线长于第二布线时，第一通孔区域中的通孔布置的数量被设置为大于第二通孔区域中的通孔布置的数量。

68. 发明授权

US07518922B2 NAND type flash memory 有权
标题翻译： NAND型闪存
公开(公告)号：US07518922B2
公开(公告)日：2009-04-14
申请号：US11749214
申请日：2007-05-16
申请人： Hiroshi Maejima , Katsuaki Isobe , Takumi Abe , Ken Takeuchi
发明人： Hiroshi Maejima , Katsuaki Isobe , Takumi Abe , Ken Takeuchi
IPC分类号： G11C16/04
CPC分类号： G11C7/1006 , G11C7/02 , G11C7/12 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C2211/5646 , G11C2211/5647
摘要： A NAND type flash memory included with a memory cell array composed of a plurality of electronically rewritable memory cells arranged in a matrix shape, and a data inversion control section which judges whether a polarity of a “1” data or a “0” data is to be inverted based on the number of the “1” data and the “0” data of the data when data is sent to the plurality of memory cells within a simultaneous write data unit and inverts the data and in the case where it is sent to the memory cell array adds an inversion flag bit to the data which shows the inversion of the polarity.
摘要翻译： NAND型闪速存储器，包括由以矩阵形状排列的多个电子可重写存储单元组成的存储单元阵列;以及数据反转控制单元，判定“1”数据或“0”数据的极性是否为当数据被发送到同时写入数据单元内的多个存储单元时，基于“1”数据和“0”数据的数字被反转，并且反转数据，并且在发送的情况下到存储单元阵列向显示极性反转的数据添加反转标志位。

69. 发明授权

US07505314B2 Semiconductor storage device provided with memory cell having charge accumulation layer and control gate 有权
标题翻译：设置有具有电荷累积层和控制栅极的存储单元的半导体存储装置
公开(公告)号：US07505314B2
公开(公告)日：2009-03-17
申请号：US11770199
申请日：2007-06-28
申请人： Katsuaki Isobe , Noboru Shibata
发明人： Katsuaki Isobe , Noboru Shibata
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5635 , G11C16/12 , G11C16/16 , G11C16/3418
摘要： A semiconductor memory device includes memory cell transistors, a first selection transistor, and word lines. Each of the memory cell transistors has a stacked gate including a charge accumulation layer and a control gate, and is configured to retain at least two levels of “0” data and “1” data according to a threshold voltage. The threshold voltage corresponding to the “0” data being the lowest threshold voltage in the levels retained by each of the memory cell transistors. The first selection transistor has a current path connected in series to one of the memory cell transistors. Each of the word lines is connected to the control gate of one of the memory cell transistors. upper limit values of threshold voltages of the memory cell transistors retaining the “0” data being different from one another in each word line.
摘要翻译：半导体存储器件包括存储单元晶体管，第一选择晶体管和字线。每个存储单元晶体管具有包括电荷累积层和控制栅极的堆叠栅极，并且被配置为根据阈值电压保持至少两个级别的“0”数据和“1”数据。对应于“0”数据的阈值电压是由每个存储单元晶体管保持的电平中的最低阈值电压。第一选择晶体管具有与存储单元晶体管之一串联连接的电流通路。每个字线连接到存储单元晶体管之一的控制栅极。保持“0”数据的存储单元晶体管的阈值电压的上限值在每个字线中彼此不同。

70. 发明申请

US20090067245A1 SEMICONDUCTOR MEMORY DEVICE PROVIDED WITH MOS TRANSISTOR HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND DATA WRITE METHOD OF NAND FLASH MEMORY 失效
标题翻译：具有带电荷累积层的MOS晶体管和NAND闪存的控制门和数据写入方法的半导体存储器件
公开(公告)号：US20090067245A1
公开(公告)日：2009-03-12
申请号：US12208798
申请日：2008-09-11
申请人： Katsuaki Isobe , Noboru Shibata
发明人： Katsuaki Isobe , Noboru Shibata
IPC分类号： G11C16/04 , G11C16/06 , G11C8/08
CPC分类号： G11C16/0483 , G11C8/08 , G11C11/5628 , G11C16/10 , G11C2211/565
摘要： A semiconductor memory device includes a memory cell group, a selection transistor, a page buffer, and a row decoder. The memory cell group includes memory cell transistors connected in series. The selection transistor is connected to the memory cell transistor. The page buffer is adopted to apply first and second voltages to the bit lines connected to the memory cell transistors in which the “0” data and “1” data is to be programmed respectively, when the selection transistor is turned on, in a write operation. The page buffer is adopted to put the bit line into electrically floating after the first voltage and the second voltage are applied. The row decoder is adopted to apply a third voltage to a semiconductor layer on which the memory cell transistors are formed, and apply a program voltage to the selected word line when the bit line is in the electrically floating.
摘要翻译：半导体存储器件包括存储单元组，选择晶体管，页缓冲器和行解码器。存储单元组包括串联连接的存储单元晶体管。选择晶体管连接到存储单元晶体管。采用页缓冲器将第一和第二电压施加到连接到存储单元晶体管的位线，其中当写选择晶体管导通时，分别对“0”数据和“1”数据进行编程操作。在施加第一电压和第二电压之后，采用页面缓冲器将位线置于电浮置中。采用行解码器将第三电压施加到其上形成有存储单元晶体管的半导体层，并且当位线处于电浮置时将编程电压施加到所选择的字线。

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