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61. 发明授权

US5888870A Memory cell fabrication employing an interpoly gate dielectric arranged upon a polished floating gate 失效
标题翻译：使用布置在抛光浮栅上的多晶硅栅极介质的存储单元制造
公开(公告)号：US5888870A
公开(公告)日：1999-03-30
申请号：US955794
申请日：1997-10-22
申请人： Mark I. Gardner , Mark C. Gilmer
发明人： Mark I. Gardner , Mark C. Gilmer
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/78391
摘要： A method is provided for forming a non-volatile memory cell in which the upper surface of the floating gate is polished to reduce surface irregularities, providing for the formation of a gate dielectric having a relatively high breakdown voltage thereon. According to an embodiment, a first gate dielectric is thermally grown upon a semiconductor substrate which later serves as the tunnel dielectric in the ensuing memory cell. A floating gate polysilicon is deposited across the first gate dielectric, followed by ion implantation of dopants and nitrogen therein. The upper surface of the floating gate polysilicon is then polished using, e.g., CMP. A second gate dielectric comprising high quality oxynitride may then be thermally grown across the polished surface of the floating gate polysilicon. Alternately, a ceramic having a relatively high dielectric constant may be formed across the floating gate polysilicon to serve as the second gate dielectric. A control gate polysilicon may be formed across the second gate dielectric. After doping the control gate polysilicon, portions of the layers formed above the substrate may be removed to define sidewall surfaces of a stacked structure. Source and drain regions which are self-aligned to the sidewall surfaces of the stacked structure may then be formed within the substrate.
摘要翻译：提供了一种用于形成非易失性存储单元的方法，其中抛光浮栅的上表面以减少表面不规则性，为栅极电介质的形成提供了较高的击穿电压。根据实施例，第一栅极电介质在半导体衬底上热生长，其后来用作随后的存储单元中的隧道电介质。跨越第一栅极电介质沉积浮栅多晶硅，然后在其中注入掺杂剂和氮。然后使用例如CMP对浮栅多晶硅的上表面进行抛光。然后可以在漂浮栅极多晶硅的抛光表面上热生长包含高质量氮氧化物的第二栅极电介质。或者，可以跨越浮置栅极多晶硅形成具有相对较高介电常数的陶瓷，以用作第二栅极电介质。可以跨越第二栅极电介质形成控制栅多晶硅。在掺杂控制栅极多晶硅之后，可以移除在衬底上形成的层的部分以限定堆叠结构的侧壁表面。然后可以在衬底内形成与层叠结构的侧壁表面自对准的源区和漏区。

62. 发明授权

US06727569B1 Method of making enhanced trench oxide with low temperature nitrogen integration 失效
标题翻译：制备具有低温氮一体化的增强型沟槽氧化物的方法
公开(公告)号：US06727569B1
公开(公告)日：2004-04-27
申请号：US09063081
申请日：1998-04-21
申请人： Mark I. Gardner , Mark C. Gilmer , Robert Paiz
发明人： Mark I. Gardner , Mark C. Gilmer , Robert Paiz
IPC分类号： H01L2900
CPC分类号： H01L21/76235
摘要： A structure and an improved isolation trench between active regions within the semiconductor substrate involves forming on a silicon substrate and forming a nitride layer on the pad layer. Thereafter, a photoresist layer is patterned on the silicon nitride layer such that regions of the nitride layer are exposed where an isolation trench will subsequently be formed. Next, the exposed regions of the nitride layer and the pad layer situated below the exposed regions of the nitride layer are etched away to expose regions of the silicon substrate. Subsequently, isolation trenches are etched into the silicon substrate with a dry etch process. A trench liner is then formed and nitrogen incorporated into a portion of the trench liner to form an oxynitride layer. After formation of the oxynitride layer, the trench is filled with a dielectric preferably comprised of a CVD oxide. Thereafter, the CVD fill dielectric is planarized and the nitride layer is stripped away.
摘要翻译：半导体衬底内的有源区域之间的结构和改进的隔离沟槽包括在硅衬底上形成并在衬垫层上形成氮化物层。此后，在氮化硅层上图案化光致抗蚀剂层，使得随后将形成隔离沟槽的氮化物层的区域被暴露。接下来，蚀刻掉位于氮化物层的暴露区域之下的氮化物层和焊盘层的暴露区域以暴露硅衬底的区域。随后，用干蚀刻工艺将隔离沟槽蚀刻到硅衬底中。然后形成沟槽衬垫，并且氮结合到沟槽衬垫的一部分中以形成氧氮化物层。在形成氮氧化物层之后，用优选由CVD氧化物构成的电介质填充沟槽。此后，CVD填充电介质被平坦化，并且氮化物层被剥离。

63. 发明授权

US06197668B1 Ferroelectric-enhanced tantalum pentoxide for dielectric material applications in CMOS devices 有权
标题翻译：铁电增强五氧化二钽用于CMOS器件中的介电材料应用
公开(公告)号：US06197668B1
公开(公告)日：2001-03-06
申请号：US09187542
申请日：1998-11-06
申请人： Mark I. Gardner , Mark C. Gilmer
发明人： Mark I. Gardner , Mark C. Gilmer
IPC分类号： H01L213205
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/31604 , H01L29/513 , H01L29/517
摘要： In insulated-gate, field effect transistor (IGFET) devices fabricated in integrated circuits, the scaling down of the dimensions of the devices has resulted in structures with dimensions are so small that reproducibility of parameters can become problematic. Specifically, the gate dielectric, typically silicon nitride, silicon oxide or silicon nitride, of a gate structure is nearing the point where the required thickness of the gate dielectric to provide the selected electric field in the channel region is implemented with a few to several atomic layers. In order to improve parameter reproducibility, a dielectric material, such TaO5 or a ferroelectric material, is used as a gate dielectric. TaO5 and the ferroelectric materials have a dielectric constant an order of magnitude higher than the material typically used in the past. Using these materials, the gate dielectric can be proportionately thicker, thereby improving the parameter reproducibility.
摘要翻译：在集成电路中制造的绝缘栅，场效应晶体管（IGFET）器件中，器件尺寸的缩小已经导致尺寸的结构如此之小，使得参数的再现性可能成为问题。具体地说，栅极结构的栅极电介质（通常为氮化硅，氧化硅或氮化硅）接近栅极电介质的所需厚度以在沟道区域中提供所选择的电场的几何到几个原子层。为了提高参数再现性，使用诸如TaO5或铁电材料的介电材料作为栅极电介质。 TaO5和铁电材料的介电常数比过去通常使用的材料高一个数量级。使用这些材料，栅极电介质可以成比例地变厚，从而提高参数的再现性。

64. 发明授权

US06175144B1 Advanced isolation structure for high density semiconductor devices 有权
标题翻译：高密度半导体器件的隔离结构
公开(公告)号：US06175144B1
公开(公告)日：2001-01-16
申请号：US09163795
申请日：1998-09-30
申请人： Mark I. Gardner , Mark C. Gilmer
发明人： Mark I. Gardner , Mark C. Gilmer
IPC分类号： H01L2900
CPC分类号： H01L21/76224
摘要： The present invention is directed to a semiconductor device having an improved structure for isolating transistors formed on a semiconductor substrate, and a method for making same. The device is comprised of a semiconductor device having first and second recesses formed in the substrate of the device. The inventive method disclosed herein comprises forming first and second recesses in the substrate of the device. The first width of the first recess is formed such that it is greater than the second width of the second recess, and the second depth of the second recess is formed such that it is greater than the first depth of the first recess.
摘要翻译：本发明涉及具有用于隔离形成在半导体衬底上的晶体管的改进结构的半导体器件及其制造方法。该器件由具有形成在器件的衬底中的第一和第二凹部的半导体器件组成。本文公开的本发明的方法包括在装置的基板中形成第一和第二凹部。第一凹部的第一宽度形成为大于第二凹部的第二宽度，并且第二凹部的第二深度形成为大于第一凹部的第一深度。

65. 发明授权

US6140167A High performance MOSFET and method of forming the same using silicidation and junction implantation prior to gate formation 有权
标题翻译：高性能MOSFET及其形成方法，在栅极形成之前使用盐化和结合注入
公开(公告)号：US6140167A
公开(公告)日：2000-10-31
申请号：US135826
申请日：1998-08-18
申请人： Mark I. Gardner , Mark C. Gilmer , Frederick N. Hause
发明人： Mark I. Gardner , Mark C. Gilmer , Frederick N. Hause
IPC分类号： H01L21/28 , H01L21/336 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/51
CPC分类号： H01L29/513 , H01L21/28079 , H01L21/28229 , H01L29/41775 , H01L29/517 , H01L29/66583 , H01L29/66621 , H01L29/78 , H01L21/28202 , H01L21/28211 , H01L29/495 , H01L29/518
摘要： A method is presented for forming a transistor wherein a silicide layer is formed upon an impurity region of a semiconductor substrate. After forming the silicide layer, a gate structure is preferably formed upon an exposed portion of the semiconductor substrate; however, the silicide layer may be formed after forming the gate structure. In order to form the gate structure, a layer of sacrificial material is first formed above the semiconductor substrate. An opening is then patterned through the layer of sacrificial material such that a portion of the semiconductor substrate is exposed. The gate structure preferably includes a metal gate conductor and a metal oxide gate dielectric.
摘要翻译：提出了一种形成晶体管的方法，其中在半导体衬底的杂质区上形成硅化物层。在形成硅化物层之后，优选在半导体衬底的暴露部分上形成栅极结构; 然而，可以在形成栅极结构之后形成硅化物层。为了形成栅极结构，首先在半导体衬底上形成牺牲材料层。然后通过牺牲材料层将开口图案化，使得半导体衬底的一部分被暴露。栅极结构优选地包括金属栅极导体和金属氧化物栅极电介质。

66. 发明授权

US6130164A Semiconductor device having gate oxide formed by selective oxide removal and method of manufacture thereof 失效
标题翻译：具有通过选择性氧化物去除形成的栅极氧化物的半导体器件及其制造方法
公开(公告)号：US6130164A
公开(公告)日：2000-10-10
申请号：US825029
申请日：1997-03-26
申请人： Mark I. Gardner , Mark C. Gilmer
发明人： Mark I. Gardner , Mark C. Gilmer
IPC分类号： H01L21/28 , H01L21/8234 , H01L29/51 , H01L21/316
CPC分类号： H01L21/28185 , H01L21/28202 , H01L29/518 , H01L21/8234
摘要： A semiconductor device having a gate oxide layer formed by selective removal of the gate oxide layer and a process for manufacturing such a device is disclosed. A gate oxide layer is formed on a substrate. The gate oxide layer is selectively removed in a controlled ambient to reduce the thickness of the gate oxide layer. A gate electrode is disposed on the gate oxide layer. In accordance with one particular aspect of the process, the controlled ambient includes an NF.sub.3 bearing gas, which is flowed over the gate oxide layer to remove portions of the oxide layer.
摘要翻译：公开了一种具有通过选择性去除栅极氧化物层形成的栅氧化层的半导体器件及其制造方法。栅极氧化层形成于基板上。在受控的环境中选择性地去除栅极氧化物层以减小栅极氧化物层的厚度。栅电极设置在栅氧化层上。根据该方法的一个特定方面，受控环境包括NF3轴承气体，其流过栅极氧化物层以去除部分氧化物层。

67. 发明授权

US6124620A Incorporating barrier atoms into a gate dielectric using gas cluster ion beam implantation 失效
标题翻译：使用气体团簇离子束注入将势垒原子并入栅极电介质
公开(公告)号：US6124620A
公开(公告)日：2000-09-26
申请号：US78797
申请日：1998-05-14
申请人： Mark I. Gardner , Mark C. Gilmer
发明人： Mark I. Gardner , Mark C. Gilmer
IPC分类号： H01L21/265 , H01L21/28 , H01L21/3215 , H01L21/336 , H01L29/49 , H01L29/51 , H01L31/119 , H01L23/58 , H01L27/01
CPC分类号： H01L21/28185 , H01L21/26506 , H01L21/28088 , H01L21/28194 , H01L21/28202 , H01L21/3215 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6659 , H01L29/495 , H01L29/4966
摘要： An integrated circuit fabrication process is provided for incorporating barrier atoms, preferably N atoms, within a gate dielectric/silicon-based substrate interfacial region using gas cluster ion beam implantation. Gas cluster ion beam implantation involves supercooling a gas to form clusters of atoms from the molecules in the gas. Those clusters of atoms are then ionized and accelerated to a target. Upon striking the target, the clusters of atoms break up into individual atoms. The energy of the ionized cluster is uniformly distributed to the individual atoms. As such, the atoms have a relatively low energy, and thus may be implanted to a shallow depth of less than 100 .ANG.. Barrier atoms positioned within a gate dielectric/substrate interfacial region serve to inhibit the diffusion of metal atoms and impurities from an overlying gate conductor into the substrate. Furthermore, the barrier layer provides protection against hot carrier injection into and entrapment within the gate dielectric.
摘要翻译：提供集成电路制造工艺，用于使用气体簇离子束注入在栅介质/硅基底层界面区域内并入势垒原子，优选N原子。气体簇离子束注入涉及过冷气体，从气体中的分子形成原子簇。然后将这些原子簇电离并加速至靶。撞击目标时，原子簇分解成单独的原子。电离簇的能量均匀分布到各个原子。因此，原子具有相对低的能量，因此可以被植入到小于100安培的浅深度。位于栅极电介质/衬底界面区域内的阻挡原子用于抑制金属原子和杂质从上覆栅极导体扩散到衬底中。此外，阻挡层提供防止热载流子注入到栅极电介质内并陷入其中的保护。

68. 发明授权

US6121094A Method of making a semiconductor device with a multi-level gate structure 失效
标题翻译：制造具有多电平栅极结构的半导体器件的方法
公开(公告)号：US6121094A
公开(公告)日：2000-09-19
申请号：US120246
申请日：1998-07-21
申请人： Mark I. Gardner , Mark C. Gilmer
发明人： Mark I. Gardner , Mark C. Gilmer
IPC分类号： H01L21/28 , H01L29/51 , H01L21/336
CPC分类号： H01L21/28194 , H01L21/28079 , H01L21/28176 , H01L21/28202 , H01L21/28229 , H01L29/513 , H01L29/517 , H01L29/518
摘要： The present invention is directed to a new semiconductor device and a method for making same. The semiconductor device is comprised of a gate dielectric layer, a conductor layer, and a metal oxide layer positioned between the gate dielectric layer and the conductor layer. The method comprises forming a gate dielectric layer, a conductor layer, and a metal oxide layer between the gate dielectric layer and the conductor layer.
摘要翻译：本发明涉及一种新的半导体器件及其制造方法。该半导体器件由位于栅介电层和导体层之间的栅介电层，导体层和金属氧化物层构成。该方法包括在栅极介电层和导体层之间形成栅极电介质层，导体层和金属氧化物层。

69. 发明授权

US6111292A Semiconductor fabrication employing self-aligned sidewall spacers laterally adjacent to a transistor gate 有权
标题翻译：采用横向邻近晶体管栅极的自对准侧壁间隔的半导体制造
公开(公告)号：US6111292A
公开(公告)日：2000-08-29
申请号：US175800
申请日：1998-10-20
申请人： Mark I. Gardner , Mark C. Gilmer
发明人： Mark I. Gardner , Mark C. Gilmer
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/66583 , Y10S257/90
摘要： A method is provided for forming nitride sidewall spacers self-aligned between opposed sidewall surfaces of a gate conductor and a sacrificial dielectric sidewall. In one embodiment, a transistor is formed by first CVD depositing a sacrificial across a semiconductor substrate. An opening is etched through the dielectric to the underlying substrate. A gate oxide is thermally grown across the region of the substrate exposed by the first opening. A polysilicon gate conductor is then formed within the opening upon the gate oxide. Portions of the gate conductor and the gate oxide are removed to expose selective regions of the substrate. In this manner, a pair of opposed sidewall surfaces are defined for the polysilicon gate conductor which are laterally spaced from respective first and second dielectrics. A LDD implant is forwarded into those exposed selective regions of the semiconductor substrate. A dielectric, preferably nitride, is deposited by CVD across the exposed LDD areas of the semiconductor substrate, the sacrificial dielectric, and the gate conductor. The nitride is removed down to a plane level with the upper surface of the gate conductor. The sacrificial dielectric may then be removed from the semiconductor substrate. An ion implantation which is self-aligned to exposed lateral edges of the spacers may then be performed to form heavily doped source/drain regions laterally spaced from the channel.
摘要翻译：提供一种用于形成在栅极导体和牺牲电介质侧壁的相对侧壁表面之间自对准的氮化物侧壁间隔件的方法。在一个实施例中，通过首先在半导体衬底上沉积牺牲形成晶体管。通过电介质将开口蚀刻到下面的衬底上。栅极氧化物在由第一开口暴露的衬底的区域上热生长。然后在栅极氧化物的开口内形成多晶硅栅极导体。去除栅极导体和栅极氧化物的部分以露出衬底的选择性区域。以这种方式，对于多晶硅栅极导体定义一对相对的侧壁表面，其与相应的第一和第二电介质横向间隔开。 LDD注入被转发到半导体衬底的暴露的选择区域中。电介质，优选氮化物，通过CVD沉积在半导体衬底，牺牲电介质和栅极导体的暴露的LDD区域上。将氮化物与栅极导体的上表面下降到平面水平。然后可以从半导体衬底去除牺牲电介质。然后可以执行与间隔物的暴露的横向边缘自对准的离子注入，以形成与沟道横向间隔开的重掺杂的源极/漏极区域。

70. 发明授权

US6100147A Method for manufacturing a high performance transistor with self-aligned dopant profile 失效
标题翻译：用于制造具有自对准掺杂剂分布的高性能晶体管的方法
公开(公告)号：US6100147A
公开(公告)日：2000-08-08
申请号：US61778
申请日：1998-04-16
申请人： Mark I. Gardner , Mark C. Gilmer
发明人： Mark I. Gardner , Mark C. Gilmer
IPC分类号： H01L21/336 , H01L29/417
CPC分类号： H01L29/66575 , H01L29/41766 , H01L29/665 , H01L29/66537 , H01L29/66545
摘要： A process for manufacturing a high performance transistor with self-aligned dopant profile. The process involves forming a source/drain mask pattern on a substrate. With a first implant material, unmasked portions of the substrate are doped to form source/drain regions of the substrate. The source-drain mask is removed and an oxidation layer is grown, where portions of the oxidation layer formed from doped regions of the substrate have heights that are greater than heights of portions of the oxidation layer formed from un-doped regions of the substrate, thereby forming a gate mask. The doped portions of the substrate are self-aligned with gate regions of the substrate. The gate regions are doped, and gate electrodes are formed. The gate mask is removed to expose source/drain regions of the substrate for further fabrication.
摘要翻译：一种用于制造具有自对准掺杂剂分布的高性能晶体管的工艺。该方法包括在衬底上形成源极/漏极掩模图案。利用第一注入材料，衬底的未屏蔽部分被掺杂以形成衬底的源极/漏极区域。去除源极 - 漏极掩模，并且生长氧化层，其中由衬底的掺杂区形成的部分氧化层的高度大于由衬底的未掺杂区域形成的部分氧化层的高度，从而形成栅极掩模。衬底的掺杂部分与衬底的栅极区域自对准。栅区被掺杂，形成栅电极。去除栅极掩模以暴露衬底的源极/漏极区域以进一步制造。

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