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61. 发明授权

US09082714B2 Use of etch process post wordline definition to improve data retention in a flash memory device 有权
标题翻译：使用蚀刻处理后字幕定义来改善闪存设备中的数据保留
公开(公告)号：US09082714B2
公开(公告)日：2015-07-14
申请号：US13993444
申请日：2011-09-22
申请人： Randy J. Koval , Max F. Hineman , Ronald A. Weimer , Vinayak K. Shamanna , Thomas M. Graettinger , William R. Kueber , Christopher Larsen , Alex J. Schrinsky
发明人： Randy J. Koval , Max F. Hineman , Ronald A. Weimer , Vinayak K. Shamanna , Thomas M. Graettinger , William R. Kueber , Christopher Larsen , Alex J. Schrinsky
IPC分类号： H01L21/76 , H01L21/306 , H01L29/51 , H01L29/788 , H01L29/792 , H01L27/115
CPC分类号： H01L21/30604 , H01L21/76 , H01L27/11521 , H01L27/11568 , H01L29/513 , H01L29/788 , H01L29/7881 , H01L29/792
摘要： Embodiments of the present disclosure are directed towards use of an etch process post wordline definition to improve data retention in a flash memory device. In one embodiment, a method includes forming a plurality of wordline structures on a substrate, wherein individual wordline structures of the plurality of wordline structures include a control gate having an electrically conductive material and a cap having an electrically insulative material formed on the control gate, depositing an electrically insulative material to form a liner on a surface of the individual wordline structures, and etching the liner to remove at least a portion of the liner. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例涉及使用蚀刻处理后字幕定义来改善闪存器件中的数据保持。在一个实施例中，一种方法包括在衬底上形成多个字线结构，其中多个字线结构中的各个字线结构包括具有导电材料的控制栅极和在控制栅极上形成有电绝缘材料的盖，沉积电绝缘材料以在单个字线结构的表面上形成衬垫，以及蚀刻衬垫以去除衬垫的至少一部分。可以描述和/或要求保护其他实施例。

62. 发明授权

US08519463B2 Semiconductor constructions containing tubular capacitor storage nodes, and retaining structures along portions of the tubular capacitor storage nodes 有权
标题翻译：包含管状电容器存储节点的半导体结构和沿着管状电容器存储节点的部分的保持结构
公开(公告)号：US08519463B2
公开(公告)日：2013-08-27
申请号：US13413552
申请日：2012-03-06
申请人： H. Montgomery Manning , Thomas M. Graettinger
发明人： H. Montgomery Manning , Thomas M. Graettinger
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/10894 , H01L27/10817 , H01L27/10852 , H01L28/91 , H01L29/945 , Y10S257/906
摘要： The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.
摘要翻译：本发明包括半导体结构，并且还包括形成多个电容器器件的方法。本发明的示例性方法包括在绝缘材料的开口内形成导电储存节点材料以形成导电容器。形成与至少一些容器物理接触的保持结构格子，随后去除绝缘材料以露出容器的外表面。保持结构可以减轻容器结构的结构完整性的倒塌或其它损失。导电容器对应于第一电容器电极。在容器的外侧壁暴露之后，电介质材料形成在容器内并沿外露的外侧壁。随后，在电介质材料上形成第二电容器电极。第一和第二电容器电极与电介质材料一起形成多个电容器器件。

63. 发明授权

US08470716B2 Methods for forming semiconductor constructions, and methods for selectively etching silicon nitride relative to conductive material 有权
标题翻译：用于形成半导体结构的方法以及相对于导电材料选择性地蚀刻氮化硅的方法
公开(公告)号：US08470716B2
公开(公告)日：2013-06-25
申请号：US13288715
申请日：2011-11-03
申请人： Kevin R. Shea , Thomas M. Graettinger
发明人： Kevin R. Shea , Thomas M. Graettinger
IPC分类号： H01L21/302 , H01L21/311 , H01L21/318
CPC分类号： H01L28/92 , H01L21/30625 , H01L21/31116 , H01L21/31144 , H01L21/32139 , H01L27/105 , H01L27/1052 , H01L27/108
摘要： The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.
摘要翻译：本发明包括相对于导电材料选择性地蚀刻绝缘材料支撑件的方法。本发明可以包括相对于金属氮化物选择性地蚀刻氮化硅的方法。金属氮化物可以是在半导体衬底上的容器的形式，其中这种容器具有向上延伸的开口，横向宽度小于或等于约4000埃; 并且氮化硅可以是在容器之间延伸的层的形式。选择性蚀刻可以包括将至少一些氮化硅和容器暴露于Cl2以去除暴露的氮化硅，同时不从容器中去除至少大部分的金属氮化物。在随后的处理中，容器可以并入电容器中。

64. 发明授权

US08228743B2 Memory cells containing charge-trapping zones 有权
标题翻译：含有电荷捕获区的存储单元
公开(公告)号：US08228743B2
公开(公告)日：2012-07-24
申请号：US13024903
申请日：2011-02-10
申请人： Kyu S. Min , Rhett T. Brewer , Tejas Krishnamohan , Thomas M. Graettinger , D. V. Nirmal Ramaswamy , Ronald A Weimer , Arup Bhattacharyya
发明人： Kyu S. Min , Rhett T. Brewer , Tejas Krishnamohan , Thomas M. Graettinger , D. V. Nirmal Ramaswamy , Ronald A Weimer , Arup Bhattacharyya
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , B82Y10/00 , G11C11/5671 , G11C16/0475 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332 , H01L29/42348 , Y10S977/943
摘要： Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.
摘要翻译：一些实施例包括具有通过介电材料彼此间隔开的垂直堆叠的电荷捕获区的存储单元。电介质材料可以包括高k材料。一个或多个电荷捕获区可以包括金属材料。这种金属材料可以作为多个离散的隔离岛存在，例如纳米点。一些实施例包括形成存储器单元的方法，其中在隧道电介质上形成两个电荷捕获区，其中区域相对于彼此垂直位移，并且最靠近隧道电介质的区域具有比另一区更深的陷阱。一些实施例包括包括存储器单元的电子系统。一些实施例包括编程具有垂直堆叠的电荷捕获区的存储器单元的方法。

65. 发明授权

US08076248B2 Methods for forming semiconductor constructions, and methods for selectively etching silicon nitride relative to conductive material 有权
标题翻译：用于形成半导体结构的方法以及相对于导电材料选择性地蚀刻氮化硅的方法
公开(公告)号：US08076248B2
公开(公告)日：2011-12-13
申请号：US12652955
申请日：2010-01-06
申请人： Kevin R. Shea , Thomas M. Graettinger
发明人： Kevin R. Shea , Thomas M. Graettinger
IPC分类号： H01L21/302 , H01L21/318 , H01L21/316
CPC分类号： H01L28/92 , H01L21/30625 , H01L21/31116 , H01L21/31144 , H01L21/32139 , H01L27/105 , H01L27/1052 , H01L27/108
摘要： The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.
摘要翻译：本发明包括相对于导电材料选择性地蚀刻绝缘材料支撑件的方法。本发明可以包括相对于金属氮化物选择性地蚀刻氮化硅的方法。金属氮化物可以是在半导体衬底上的容器的形式，其中这种容器具有向上延伸的开口，横向宽度小于或等于约4000埃; 并且氮化硅可以是在容器之间延伸的层的形式。选择性蚀刻可以包括将至少一些氮化硅和容器暴露于Cl2以去除暴露的氮化硅，同时不从容器中去除至少大部分的金属氮化物。在随后的处理中，容器可以并入电容器中。

66. 发明授权

US07781818B2 Semiconductor constructions containing tubular capacitor storage nodes, and retaining structures along portions of the tubular capacitor storage nodes 有权
标题翻译：包含管状电容器存储节点的半导体结构和沿着管状电容器存储节点的部分的保持结构
公开(公告)号：US07781818B2
公开(公告)日：2010-08-24
申请号：US11595436
申请日：2006-11-09
申请人： H. Montgomery Manning , Thomas M. Graettinger
发明人： H. Montgomery Manning , Thomas M. Graettinger
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/10894 , H01L27/10817 , H01L27/10852 , H01L28/91 , H01L29/945 , Y10S257/906
摘要： The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.
摘要翻译：本发明包括半导体结构，并且还包括形成多个电容器器件的方法。本发明的示例性方法包括在绝缘材料的开口内形成导电储存节点材料以形成导电容器。形成与至少一些容器物理接触的保持结构格子，随后去除绝缘材料以露出容器的外表面。保持结构可以减轻容器结构的结构完整性的倒塌或其它损失。导电容器对应于第一电容器电极。在容器的外侧壁暴露之后，电介质材料形成在容器内并沿外露的外侧壁。随后，在电介质材料上形成第二电容器电极。第一和第二电容器电极与电介质材料一起形成多个电容器器件。

67. 发明授权

US07736987B2 Methods of forming semiconductor constructions 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US07736987B2
公开(公告)日：2010-06-15
申请号：US11742983
申请日：2007-05-01
申请人： H. Montgomery Manning , Thomas M. Graettinger
发明人： H. Montgomery Manning , Thomas M. Graettinger
IPC分类号： H01L21/20
CPC分类号： H01L27/10894 , H01L27/10817 , H01L27/10852 , H01L28/91 , H01L29/945 , Y10S257/906
摘要： The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.
摘要翻译：本发明包括半导体结构，并且还包括形成多个电容器器件的方法。本发明的示例性方法包括在绝缘材料的开口内形成导电储存节点材料以形成导电容器。形成与至少一些容器物理接触的保持结构格子，随后去除绝缘材料以露出容器的外表面。保持结构可以减轻容器结构的结构完整性的倒塌或其它损失。导电容器对应于第一电容器电极。在容器的外侧壁暴露之后，电介质材料形成在容器内并沿外露的外侧壁。随后，在电介质材料上形成第二电容器电极。第一和第二电容器电极与电介质材料一起形成多个电容器器件。

68. 发明申请

US20090097320A1 Memory Cells, Electronic Systems, Methods Of Forming Memory Cells, And Methods of Programming Memory Cells 有权
标题翻译：记忆单元，电子系统，形成记忆单元的方法，以及编程记忆单元的方法
公开(公告)号：US20090097320A1
公开(公告)日：2009-04-16
申请号：US11871339
申请日：2007-10-12
申请人： Kyu S. Min , Rhett T. Brewer , Tejas Krishnamohan , Thomas M. Graettinger , D. V. Ramaswamy , Ronald A. Weimer , Arup Bhattacharyya
发明人： Kyu S. Min , Rhett T. Brewer , Tejas Krishnamohan , Thomas M. Graettinger , D. V. Ramaswamy , Ronald A. Weimer , Arup Bhattacharyya
IPC分类号： G11C16/04 , H01L29/792
CPC分类号： G11C16/0483 , B82Y10/00 , G11C11/5671 , G11C16/0475 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332 , H01L29/42348 , Y10S977/943
摘要： Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.
摘要翻译：一些实施例包括具有通过介电材料彼此间隔开的垂直堆叠的电荷捕获区的存储单元。电介质材料可以包括高k材料。一个或多个电荷捕获区可以包括金属材料。这种金属材料可以作为多个离散的隔离岛存在，例如纳米点。一些实施例包括形成存储器单元的方法，其中在隧道电介质上形成两个电荷捕获区，其中区域相对于彼此垂直位移，并且最靠近隧道电介质的区域具有比另一区更深的陷阱。一些实施例包括包括存储器单元的电子系统。一些实施例包括编程具有垂直堆叠的电荷捕获区的存储器单元的方法。

69. 发明授权

US07498629B2 Stud electrode and process for making same 有权
标题翻译：螺柱电极及其制造方法
公开(公告)号：US07498629B2
公开(公告)日：2009-03-03
申请号：US11786219
申请日：2007-04-11
申请人： Thomas M. Graettinger
发明人： Thomas M. Graettinger
IPC分类号： H01L29/92
CPC分类号： H01L28/91 , H01L21/7687 , H01L27/10852 , H01L27/10855 , H01L28/90
摘要： A process of making a stud capacitor structure is disclosed. The process includes embedding the stud in a dielectric stack. In one embodiment, the process includes forming an electrically conductive seed film in a contact corridor of the dielectric stack. A storage cell stud is also disclosed. The storage cell stud can be employed in a dynamic random-access memory device. An electrical system is also disclosed that includes the storage cell stud.
摘要翻译：公开了一种制造双绞电容器结构的工艺。该过程包括将柱嵌入电介质堆叠中。在一个实施例中，该方法包括在电介质堆叠的接触走廊中形成导电种子膜。还公开了存储单元柱。存储单元螺柱可用于动态随机存取存储器件中。还公开了一种包括存储单元螺柱的电气系统。

70. 发明授权

US07495277B2 Memory circuitry 失效
标题翻译：内存电路
公开(公告)号：US07495277B2
公开(公告)日：2009-02-24
申请号：US11481660
申请日：2006-07-05
申请人： Thomas M. Graettinger
发明人： Thomas M. Graettinger
IPC分类号： H01L27/108
CPC分类号： H01L27/10852 , H01L27/10814 , H01L27/10885 , H01L28/60 , H01L28/75 , H01L28/90
摘要： The invention includes memory circuitry. In one implementation, memory circuitry includes a memory array comprising a plurality of memory cell capacitors. Individual of the capacitors include a storage node electrode, a capacitor dielectric region, and a cell electrode. The cell electrode is commonly shared among at least some of the plurality of memory cell capacitors within the memory array. The cell electrode within the memory array includes a conductor metal layer including at least one of elemental tungsten, a tungsten alloy, tungsten silicide and tungsten nitride. Polysilicon is received over the conductor metal layer. The conductor metal layer and the polysilicon are received over the storage node electrodes of said at least some of the plurality of memory cell capacitors. Other aspects and implementations are contemplated.
摘要翻译：本发明包括存储器电路。在一个实现中，存储器电路包括包括多个存储单元电容器的存储器阵列。电容器的个体包括存储节点电极，电容器电介质区域和电池电极。单元电极在存储器阵列内的多个存储单元电容器中的至少一些存储单元电容器中共同共用。存储器阵列内的电池电极包括包括元素钨，钨合金，硅化钨和氮化钨中的至少一种的导体金属层。多晶硅被接收在导体金属层上。导体金属层和多晶硅被接收在多个存储单元电容器中的至少一些的存储节点电极上。考虑了其他方面和实现。

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