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61. 发明授权

US07394277B2 Testing apparatus, testing method, jitter filtering circuit, and jitter filtering method 有权
标题翻译：测试仪器，测试方法，抖动滤波电路和抖动滤波方法
公开(公告)号：US07394277B2
公开(公告)日：2008-07-01
申请号：US11407136
申请日：2006-04-20
申请人： Masahiro Ishida , Kiyotaka Ichiyama , Takahiro Yamaguchi
发明人： Masahiro Ishida , Kiyotaka Ichiyama , Takahiro Yamaguchi
IPC分类号： G01R31/26
CPC分类号： G01R31/31908 , G01R31/31725
摘要： There is provided a testing apparatus for evaluating a device-under-test, having an extracting section for extracting jitter components out of an output signal outputted out of the device-under-test, a filter for passing predetermined frequency components in the jitter components, a phase control section for controlling phase of the output signal based on the jitter components outputted out of the filter and an evaluating section for evaluating the device-under-test based on a signal outputted out of the phase control section.
摘要翻译：提供了一种用于评估被测器件的测试装置，具有提取部分，用于从经测试的器件输出的输出信号中提取抖动分量，用于使抖动分量中的预定频率分量通过的滤波器，相位控制部分，用于基于从滤波器输出的抖动分量来控制输出信号的相位;以及评估部分，用于基于从相位控制部分输出的信号来评估被测器件。

62. 发明申请

US20070236284A1 Calibration apparatus, calibration method, testing apparatus, and testing method 失效
标题翻译：校准装置，校准方法，试验装置和试验方法
公开(公告)号：US20070236284A1
公开(公告)日：2007-10-11
申请号：US11371849
申请日：2006-03-10
申请人： Kiyotaka Ichiyama , Masahiro Ishida , Takahiro Yamaguchi
发明人： Kiyotaka Ichiyama , Masahiro Ishida , Takahiro Yamaguchi
IPC分类号： H03K9/00
CPC分类号： G01R29/26 , G01R31/31709 , H04L1/205
摘要： There is provided a calibration apparatus for calibrating an electronic device that outputs a demodulation signal in which a modulated component of a signal to be tested or evaluated is demodulated, having a DC component detecting section for detecting a DC component of the demodulation signal, a gain calculating section for calculating a gain in the electronic device based on the DC component of the demodulation signal and a calibrating section for calibrating the electronic device based on the gain in the electronic device.
摘要翻译：提供了一种用于校准电子装置的校准装置，该电子装置输出其中被测试或评估的信号的调制分量被解调的解调信号，具有用于检测解调信号的DC分量的DC分量检测部分，计算部分，用于基于解调信号的DC分量计算电子设备中的增益;以及校准部分，用于基于电子设备中的增益校准电子设备。

63. 发明申请

US20070203659A1 Measuring apparatus, measuring method, testing apparatus, testing method, and electronics device 有权
标题翻译：测量仪器，测量方法，测试仪器，测试方法和电子设备
公开(公告)号：US20070203659A1
公开(公告)日：2007-08-30
申请号：US11362536
申请日：2006-02-27
申请人： Takahiro Yamaguchi , Satoshi Iwamoto , Masakatsu Suda , Masahiro Ishida
发明人： Takahiro Yamaguchi , Satoshi Iwamoto , Masakatsu Suda , Masahiro Ishida
IPC分类号： G06F19/00
CPC分类号： G01R31/31709
摘要： There is provided a measuring apparatus for measuring a signal-under-test, having a comparator for sequentially comparing voltage values of the signal-under-test with a reference voltage value fed thereto at timing of strobe signals sequentially fed thereto, a strobe timing generator for sequentially generating the strobe signals placed almost at equal time intervals, a capture memory for storing the comparison result of the comparator and a digital signal processing section for calculating jitter of the signal-under-test based on the comparison result stored in the capture memory.
摘要翻译：提供了一种用于测量被测信号的测量装置，具有一个比较器，用于在顺序地馈送到其中的选通信号的定时顺序地比较被测信号的电压值与馈送给它的基准电压值，选通定时发生器用于顺序地产生几乎以相等的时间间隔放置的选通信号，用于存储比较器的比较结果的捕获存储器和用于基于存储在捕获存储器中的比较结果来计算待测信号的抖动的数字信号处理部分。

64. 发明申请

US20060031731A1 Generating test patterns used in testing semiconductor integrated circuit 失效
公开(公告)号：US20060031731A1
公开(公告)日：2006-02-09
申请号：US11238821
申请日：2005-09-28
申请人： Masahiro Ishida , Takahiro Yamaguchi
发明人： Masahiro Ishida , Takahiro Yamaguchi
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/2882 , G01R31/31813 , G01R31/3183 , G01R31/318328 , G01R31/31917 , G06F11/263
摘要： A test pattern sequence which is used to test a delay fault or an open fault which accompanies a delay occurring in an IC is easily and rapidly generated. A list of locations such as logic gates and signal lines within the circuit where a fault is likely to occur is prepared (101). One of the faults is selected, and an initialization test pattern v1 which establishes an initial value for activating the fault at the location of a fault is determined by the implication operation (103), and a propagation test pattern v2 which causes a stuck-at fault to be propagated to a following gate is determined by the implication operation (105). A sequence formed by v1 and v2 is registered with a test pattern list (107), and the described operations are repeated until there remains no unprocessed fault in the fault list.

65. 发明授权

US06801049B2 Method and apparatus for defect analysis of semiconductor integrated circuit 失效
公开(公告)号：US06801049B2
公开(公告)日：2004-10-05
申请号：US09980891
申请日：2001-12-03
申请人： Masahiro Ishida , Takahiro Yamaguchi , Yoshihiro Hashimoto
发明人： Masahiro Ishida , Takahiro Yamaguchi , Yoshihiro Hashimoto
IPC分类号： G01R3126
CPC分类号： G01R31/3004 , G01R31/3181
摘要： A fault analysis method and apparatus which is able to improve the reliability of fault analysis of semiconductor integrated circuit. In case of supplying a test pattern sequence having a plurality of test patterns to the semiconductor IC, an analysis point whose electric potential changes according to the change of supplied test pattern is placed corresponding to the test pattern sequence. Then, a transient power supply current generated on the semiconductor IC according to the change of the test pattern is measured and determined whether the measured transient power supply current is abnormal or not. A defection point is presumed based on the test pattern sequence where the transient power supply current is abnormal, and the analysis point placed corresponding to the test pattern sequence.

66. 发明授权

US06461882B2 Fault simulation method and fault simulator for semiconductor integrated circuit 失效
标题翻译：半导体集成电路的故障模拟方法和故障模拟器
公开(公告)号：US06461882B2
公开(公告)日：2002-10-08
申请号：US09880976
申请日：2001-06-13
申请人： Masahiro Ishida , Takahiro Yamaguchi
发明人： Masahiro Ishida , Takahiro Yamaguchi
IPC分类号： G01R3126
CPC分类号： G01R31/318342
摘要： A transient power supply current testing technique which affords a high level of observability is used to prepare a list of detectable faults including a gate delay fault, an open fault and a path delay fault. A test pattern sequence formed by two or more test patterns is obtained (202), a train of transition signal values which occur on various signal lines within the circuit when the pattern sequence is applied to operate IC under test is determined by a transition simulation (203), and the train of transition signal values occurring on various signal lines is used to prepare a fault list which are detectable by the transient power supply current testing when the pattern sequence is used to operate the IC under test (204).
摘要翻译：使用提供高水平可观察性的瞬态电源电流测试技术来准备可检测故障的列表，包括门延迟故障，开路故障和路径延迟故障。获得由两个或多个测试图案形成的测试图案序列（202），当应用图案序列来操作测试中的IC时，在电路内的各种信号线上发生的一系列转变信号值通过转换模拟（ 203），并且使用在各种信号线上发生的转变信号值串来准备故障列表，当使用模式序列来操作被测IC（204）时，可以通过瞬态电源电流测试来检测该故障列表。

67. 发明申请

US20100106468A1 DETERMINISTIC COMPONENT MODEL IDENTIFYING APPARATUS, IDENTIFYING METHOD, PROGRAM, RECORDING MEDIUM, TEST SYSTEM AND ELECTRONIC DEVICE 有权
标题翻译：确定组件模型识别装置，识别方法，程序，记录介质，测试系统和电子设备
公开(公告)号：US20100106468A1
公开(公告)日：2010-04-29
申请号：US12257395
申请日：2008-10-24
申请人： Takahiro Yamaguchi , Masahiro Ishida , Kiyotaka Ichiyama
发明人： Takahiro Yamaguchi , Masahiro Ishida , Kiyotaka Ichiyama
IPC分类号： G06F7/60 , G06F17/18
CPC分类号： G01R31/31919 , G01R29/26 , G01R31/2837 , G01R31/2894
摘要： There is provided a deterministic component model identifying apparatus for determining a type of a deterministic component contained in a probability density function supplied thereto. The deterministic component model identifying apparatus includes a spectrum calculating section that calculates a spectrum of the probability density function on an axis of a predetermined variable, a null value detecting section that detects a null value on the axis of the predetermined variable in the calculated spectrum, a theoretical value calculating section that calculates a theoretical value of a spectrum of the deterministic component in association with each of a plurality of predetermined deterministic component types, based on the null value detected by the null value detecting section, and a model determining section that determines, as the type of the deterministic component contained in the probability density function, a deterministic component type associated with a logarithmic magnitude spectrum difference most similar to a logarithmic magnitude spectrum of a Gaussian distribution, where the logarithmic magnitude spectrum difference is produced by subtracting the theoretical value of the spectrum of the deterministic component calculated in association with each of the plurality of predetermined deterministic component types from the spectrum calculated by the spectrum calculating section.
摘要翻译：提供了一种用于确定包含在提供给它的概率密度函数中的确定性分量的类型的确定性分量模型识别装置。确定性分量模型识别装置包括频谱计算部分，其计算预定变量的轴上的概率密度函数的频谱;空值检测部分，其检测所计算的频谱中的预定变量的轴上的零值; 理论值计算部，基于由空值检测部检测出的空值，与多个预定确定部分类型中的每一个相关联地计算确定性分量的频谱的理论值;以及模型确定部，其确定，作为包含在概率密度函数中的确定性分量的类型，与与高斯分布的对数幅度谱最相似的对数幅度谱差相关的确定性分量类型，其中通过减去理论产生对数幅度谱差根据由频谱计算部分计算的频谱，与多个预定确定性分量类型中的每一个相关联地计算出的确定性分量的频谱的等级值。

68. 发明申请

US20080077342A1 JITTER MEASUREMENT APPARATUS, JITTER MEASUREMENT METHOD, AND RECORDING MEDIUM 失效
标题翻译：抖动测量装置，抖动测量方法和记录介质
公开(公告)号：US20080077342A1
公开(公告)日：2008-03-27
申请号：US11535279
申请日：2006-09-26
申请人： Kiyotaka ICHIYAMA , Masahiro Ishida , Takahiro Yamaguchi
发明人： Kiyotaka ICHIYAMA , Masahiro Ishida , Takahiro Yamaguchi
IPC分类号： G06F19/00 , G06F17/40
CPC分类号： G01R29/26 , G01R31/31709
摘要： There is provided a jitter measurement apparatus for measuring a jitter of a data signal having a substantially constant data rate. The jitter measurement apparatus includes therein a signal converting section that converts the data signal into a clock signal, where the clock signal retains timings of data transition edges of the data signal at which a data value of the data signal transits and has edges whose cycle is substantially equal to the data rate, an analytic signal generating section that converts the clock signal into an analytic signal of a complex number, and a jitter measuring section that measures the jitter of the data signal based on the analytic signal.
摘要翻译：提供了一种用于测量具有基本上恒定的数据速率的数据信号的抖动的抖动测量装置。抖动测量装置包括信号转换部分，其将数据信号转换成时钟信号，其中时钟信号保持数据信号的数据值的数据转换边沿的定时，数据信号的数据值在该周期为基本上等于数据速率，将时钟信号转换为复数分析信号的分析信号生成部分，以及基于分析信号测量数据信号的抖动的抖动测量部分。

69. 发明授权

US07254764B2 Generating test patterns used in testing semiconductor integrated circuit 失效
标题翻译：生成用于测试半导体集成电路的测试图案
公开(公告)号：US07254764B2
公开(公告)日：2007-08-07
申请号：US11238821
申请日：2005-09-28
申请人： Masahiro Ishida , Takahiro Yamaguchi
发明人： Masahiro Ishida , Takahiro Yamaguchi
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/2882 , G01R31/31813 , G01R31/3183 , G01R31/318328 , G01R31/31917 , G06F11/263
摘要： Selected test pattern sequences to be used in transient power supply current testing to detect path delay faults in an IC are easily and rapidly generated. A stored fault list of path delay faults is prepared. A train of transition signal values is calculated by simulation of transitions occurring in the IC when a test pattern sequence is applied to the IC, and respective path delay fault in the stored fault list is determined whether it is a detectable fault that is capable of being detected by the transient power supply current testing by using the transition signal values. Those detectable faults that exist in the stored fault list are deleted from the stored fault list and those test pattern sequences that are used to detect the detectable faults existing in the stored fault list are registered in a test pattern sequence list as the selected test pattern sequence.
摘要翻译：用于瞬态电源电流测试中用于检测IC中的路径延迟故障的所选测试图案序列容易且快速地产生。准备存储路径延迟故障的故障列表。当测试图案序列施加到IC时，通过模拟IC中发生的转换来计算转移信号值串，并且确定存储的故障列表中的各个路径延迟故障是否是可检测的故障，其可以是通过使用过渡信号值的瞬态电源电流测试来检测。存储的故障列表中存在的可检测故障从存储的故障列表中删除，并且用于检测存在故障列表中存在的可检测故障的那些测试模式序列作为所选择的测试模式序列被登记在测试模式序列表中。

70. 发明授权

US07185254B2 Method and apparatus for generating test patterns used in testing semiconductor integrated circuit 失效
标题翻译：用于生成用于测试半导体集成电路的测试图案的方法和装置
公开(公告)号：US07185254B2
公开(公告)日：2007-02-27
申请号：US09876389
申请日：2001-06-06
申请人： Masahiro Ishida , Takahiro Yamaguchi
发明人： Masahiro Ishida , Takahiro Yamaguchi
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/2882 , G01R31/31813 , G01R31/3183 , G01R31/318328 , G01R31/31917 , G06F11/263
摘要： A test pattern sequence which is used to test a delay fault or an open fault which accompanies a delay occurring in an IC is easily and rapidly generated. A list of locations such as logic gates and signal lines within the circuit where a fault is likely to occur is prepared. One of the faults is selected, and an initialization test pattern v1 which establishes an initial value for activating the fault at the location of a fault is determined by the implication operation, and a propagation test pattern v2 which causes a stuck-at fault to be propagated to a following gate is determined by the implication operation. A sequence formed by v1 and v2 is registered with a test pattern list, and the described operations are repeated until there remains no unprocessed fault in the fault list.
摘要翻译：用于测试伴随IC发生的延迟的延迟故障或开路故障的测试模式序列容易且快速地产生。准备了可能发生故障的电路内诸如逻辑门和信号线之类的位置列表。选择其中一个故障，并且通过暗示操作确定用于激活故障位置处的故障的初始值的初始化测试模式v 1以及导致卡住故障的传播测试模式v 2 通过含义操作确定传播到后门。由v 1和v 2形成的序列用测试模式列表注册，并且重复所描述的操作，直到在故障列表中不存在未处理的故障。

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