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    • 62. 发明授权
      US4929991A Rugged lateral DMOS transistor structure 失效
    • Rugged lateral DMOS transistor structure
    • 坚固的横向DMOS晶体管结构
    • US4929991A
    • 1990-05-29
    • US334806
    • 1989-04-05
    • Richard A. Blanchard
    • Richard A. Blanchard
    • H01L27/02 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/40 , H01L29/78
    • H01L29/404 , H01L27/0251 , H01L29/0847 , H01L29/1087 , H01L29/7835
    • A lateral DMOS transistor includes a high conductivity substrate having an epitaxial layer grown thereon to have a resistivity suitable for the transistor body. A highly doped topside body contact is diffused into the epitaxial layer along with an abutting heavily doped source. The source is self-aligned with a conductive polysilicon gate lying on top of a thin gate oxide. After source diffusion the gate is oxide coated so as to be fully insulated. A main drain electrode portion is diffused near the opposing side of the gate spaced a distance away. A lightly doped drain region portion extends between the main drain region and the edge of the gate providing the required surface breakdown behavior. The main drain diffusion portion is extended into the epitaxial layer so that the spacing between the heavily doped substrate and the drain diffusion produces depletion region reach through at a voltage that is lower than the drain avalanche voltage. Several embodiments are set forth for practicing the invention.
    • 横向DMOS晶体管包括具有在其上生长的具有适合于晶体管体的电阻率的外延层的高电导率衬底。 高度掺杂的顶侧体接触与邻接的重掺杂源一起扩散到外延层中。 源极与位于薄栅极氧化物顶部的导电多晶硅栅极自对准。 在源极扩散之后，栅极被氧化物涂覆以便完全绝缘。 主漏电极部分在距栅极间隔一定距离的相对侧附近扩散。 轻掺杂漏区部分在主漏极区域和栅极边缘之间延伸，提供所需的表面击穿行为。 主漏极扩散部分延伸到外延层中，使得重掺杂衬底和漏极扩散之间的间隔产生耗尽区域到达低于漏极雪崩电压的电压。 阐述了实施本发明的几个实施例。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 63. 发明授权
      US4916509A Method for obtaining low interconnect resistance on a grooved surface and the resulting structure 失效
    • Method for obtaining low interconnect resistance on a grooved surface and the resulting structure
    • 在槽形表面上获得低互连电阻的方法及其结果
    • US4916509A
    • 1990-04-10
    • US336619
    • 1989-04-07
    • Richard A. Blanchard , Adrian I. Cogan
    • Richard A. Blanchard , Adrian I. Cogan
    • H01L23/528 , H01L29/06
    • H01L29/0657 , H01L23/5283 , H01L2924/0002
    • In accordance with the teachings of this invention, a novel electrical interconnect structure is taught, together with the process for forming this structure. In accodance with the teachings of this invention, this structure includes an electrical interconnect layer which is formed on a grooved portion of the surface of a semiconductor device. Thus, the effective cross-sectional area of the electrical interconnect layer is increased because the electrical interconnect material is formed into the grooves. With the thickness of the electrical interconnect layer thus increased as compared with the thickness of prior art electrical interconnect layers, the sheet resistance of the electrical interconnect layer of this invention is reduced over the sheet resistance of prior art electrical interconnect layers. With a lower sheet resistance, a given length of electrical interconnect can be formed of the same resistance as in the prior art with a smaller width. Alternatively, for a given length and a given width, an electrical interconnect can be fabricated in accordance with the teachings of this invention having a lower resistance than in the prior art.
    • 根据本发明的教导，教导了一种新颖的电互连结构以及用于形成该结构的方法。 根据本发明的教导，该结构包括形成在半导体器件的表面的沟槽部分上的电互连层。 因此，电互连层的有效截面积增加，因为电互连材料形成为凹槽。 与现有技术的电互连层的厚度相比，随着电互连层的厚度增加，本发明的电互连层的薄层电阻比现有技术的电互连层的薄层电阻降低。 具有较低的薄层电阻，给定长度的电互连可以由具有较小宽度的现有技术中相同的电阻形成。 或者，对于给定的长度和给定的宽度，可以根据本发明的教导制造具有比现有技术更低的电阻的电互连。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 64. 发明授权
      US4851366A Method for providing dielectrically isolated circuit 失效
    • Method for providing dielectrically isolated circuit
    • 提供介电隔离电路的方法
    • US4851366A
    • 1989-07-25
    • US120343
    • 1987-11-13
    • Richard A. Blanchard
    • Richard A. Blanchard
    • H01L21/762
    • H01L21/76264 , H01L21/76297 , H01L21/76275 , H01L21/76286 , Y10S148/05
    • A novel process and structure is taught which provides discrete semiconductor islands located in a semiconductor substrate, the islands being electrically isolated from each other. Certain of these islands, in addition to being electrically isolated from other islands, are also electrically isolated from the substrate. Yet other ones of these islands are electrically isolated from other islands, but are electrically connected to the substrate. In accordance with the teachings of this invention, a substrate is used and a layer of electrical insulation is formed over only a portion of the surface of the substrate. Grooves are then formed to serve as vertical isolation regions. The grooves are filled with a non-conductive material, or covered with a layer of insulation on their sides and bottom, and filled with any convenient material, such as polycrystalline silicon. A second semiconductor substrate is then bonded to the first, and serves as the ultimate substrate of the finished device. The surface of the first substrate opposite said second substrate is etched to the vertical grooves, thereby providing a surface having vertical grooves serving as vertical isolation. The insulation layer formed on the surface of the first substrate serves as isolation between the islands and second substrate, a while the absence of such insulation layer causes certain other islands to be electrically connected to the second substrate.
    • 教导了一种新颖的工艺和结构，其提供位于半导体衬底中的离散半导体岛，这些岛彼此电隔离。 除了与其他岛电隔离之外，这些岛中的某些还与基底电隔离。 这些岛中的其他岛屿与其他岛电隔离，但是电连接到基底。 根据本发明的教导，使用基板，并且仅在基板表面的一部分上形成电绝缘层。 然后形成槽以用作垂直隔离区。 凹槽填充有非导电材料，或者在其侧面和底部被绝缘层覆盖，并且填充有任何方便的材料，例如多晶硅。 然后将第二半导体衬底接合到第一半导体衬底，并且用作最终器件的最终衬底。 与第二基板相对的第一基板的表面被蚀刻到垂直槽，从而提供具有用作垂直隔离的垂直槽的表面。 形成在第一衬底的表面上的绝缘层用作岛和第二衬底之间的隔离，同时不存在这种绝缘层使得某些其他岛电连接到第二衬底。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 65. 发明授权
      US4794436A High voltage drifted-drain MOS transistor 失效
    • High voltage drifted-drain MOS transistor
    • 高压漂漏MOS晶体管
    • US4794436A
    • 1988-12-27
    • US195436
    • 1988-05-16
    • Richard A. Blanchard
    • Richard A. Blanchard
    • H01L29/06 , H01L29/08 , H01L29/78 , H01L27/02 , H01L29/72
    • H01L29/0847 , H01L29/0615 , H01L29/7835
    • A heavily doped P region is formed at the end of a lightly doped P- drain extension adjacent to the channel of a P channel MOS transistor. If the PMOS transistor is fabricated in an N-well surrounded by P- type material, a parasitic vertical transistor is formed which may be undesireably biased into its active mode if the voltage at the P+ drain of the PMOS transistor causes the P+ drain and N- body to be forward biased. When this vertical transistor conducts, power is wasted. The addition of the P region formed at the end of the lightly doped drain greatly increases the current gain of the parasitic lateral transistor, which is biased into its active mode under the same conditions which bias the vertical transistor into its active mode. The current through the lateral parasitic transistor, which may be recaptured, is thus much greater than the current through the vertical parasitic transistor, resulting in less power loss when the parasitic transistors are biased into their active modes under abnormal conditions.
    • 在与P沟道MOS晶体管的沟道相邻的轻掺杂P漏极延伸的末端形成重掺杂P区。 如果PMOS晶体管制造在由P-型材料包围的N阱中，则形成寄生垂直晶体管，如果PMOS晶体管的P +漏极处的电压导致P +漏极和N - 身体向前偏见。 当这个垂直晶体管导通时，浪费电能。 添加形成在轻掺杂漏极末端的P区极大地增加了寄生横向晶体管的电流增益，寄生横向晶体管在将垂直晶体管偏置成其有源模式的相同条件下被偏置到其有源模式。 因此，通过横向寄生晶体管的电流可能会被重新捕获，因此比通过垂直寄生晶体管的电流大得多，当寄生晶体管在异常条件下被偏置到其有源模式时，导致更小的功率损耗。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 68. 发明授权
      US4345265A MOS Power transistor with improved high-voltage capability 失效
    • MOS Power transistor with improved high-voltage capability
    • MOS功率晶体管具有改善的高压能力
    • US4345265A
    • 1982-08-17
    • US139654
    • 1980-04-14
    • Richard A. Blanchard
    • Richard A. Blanchard
    • H01L29/06 , H01L29/10 , H01L29/78
    • H01L29/7802 , H01L29/0696 , H01L29/1095
    • Device means for reducing latch-back breakdown thus raising the reverse-biased power capability of a DMOS transistor or the like. A DMOS transistor is an MOS field effect transistor comprising a lightly-doped (usually diffused) body region formed in a drain region; a heavily-doped source region is located in the body region in proximity to the drain. Since such a device structure also exhibits substantial bipolar transistor action, it is prone to latch-back breakdown. Means for reducing latch-back breakdown include providing a distributed diode with a lower breakdown voltage than the DMOS transistor to non-destructively absorb reverse transients or by providing shunt conductance means for the diffused channel region to reduce both the voltage and the voltage gradient in the base of the parasitic bipolar device. These means may be used singly or in combination.
    • 用于减小闩锁反击的装置，从而提高DMOS晶体管等的反向偏置功率能力。 DMOS晶体管是包括在漏极区域中形成的轻掺杂（通常是扩散的）体区的MOS场效应晶体管; 重掺杂源极区域位于靠近漏极的体区中。 由于这种器件结构也表现出巨大的双极晶体管作用，所以容易产生闭锁故障。 用于减少闭锁回击的装置包括提供具有比DMOS晶体管更低的击穿电压的分布二极管以非破坏性地吸收反向瞬变，或者通过为扩散通道区域提供并联电导装置来减小电压和电压梯度 寄生双极器件的基极。 这些方法可以单独使用或组合使用。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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