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    • 61. 发明授权
    • Signal processing circuit and signal processing method
    • 信号处理电路及信号处理方法
    • US07932763B2
    • 2011-04-26
    • US12511971
    • 2009-07-29
    • Hsin-Hung ChenChun-Pang WuPing-Ying Wang
    • Hsin-Hung ChenChun-Pang WuPing-Ying Wang
    • H03H11/16
    • H04L27/361
    • A signal processing circuit includes: a first operation circuit for receiving a phase component of an input signal, and generating an adjusted phase component and at least one weighting factor according to the phase component of the input signal; a second operation circuit, coupled to the first operation circuit, for receiving the adjusted phase component and converting the adjusted phase component into a frequency component corresponding to the adjusted phase component; a third operation circuit, coupled to the first operation circuit, for receiving an amplitude component of the input signal, and adjusting the amplitude component according to the at least one weighting factor to generate an adjusted amplitude component; and a fourth operation circuit, coupled to the second operation circuit and the third operation circuit, for generating an output signal according to the frequency component and the adjusted amplitude component.
    • 信号处理电路包括:第一操作电路,用于接收输入信号的相位分量,并根据输入信号的相位分量产生经调整的相位分量和至少一个加权因子; 第二操作电路,耦合到第一操作电路,用于接收经调整的相位分量,并将调整后的相位分量转换成对应于经调整的相位分量的频率分量; 耦合到所述第一操作电路的第三操作电路,用于接收所述输入信号的幅度分量,以及根据所述至少一个加权因子调整所述幅度分量以产生调整的幅度分量; 以及耦合到所述第二操作电路和所述第三操作电路的第四操作电路,用于根据所述频率分量和所述调整的振幅分量来产生输出信号。
    • 65. 发明授权
    • Digital background calibration for time-interlaced analog-to-digital converters
    • 时间隔行模数转换器的数字背景校准
    • US07227479B1
    • 2007-06-05
    • US11315640
    • 2005-12-22
    • Hsin-Hung ChenJaesik Lee
    • Hsin-Hung ChenJaesik Lee
    • H03M1/06
    • H03M1/1004H03M1/1215
    • The present invention provides for background calibration of a time-interleaved analog-to-digital converter (TIADC). In one embodiment, a background calibrator includes a TIADC having a parallel array of time-interleaved main signal processors, each main signal processor including an ADC connected to a corresponding output FIR filter. The background calibrator also includes an auxiliary signal processor having an ADC connected to at least one corresponding output FIR filter. Additionally, the background calibrator further includes a timing calibration circuit, wherein the timing calibration circuit is configured to select one of the main signal processors, exchange the auxiliary signal processor with the selected main signal processor in the TIADC and connect the selected main signal processor to the timing calibration circuit. In an alternative embodiment, the timing calibration circuit is further configured to reduce a timing mismatch of the selected main signal processor.
    • 本发明提供了时间交织的模数转换器(TIADC)的背景校准。 在一个实施例中,背景校准器包括具有时间交错的主信号处理器的并行阵列的TIADC,每个主信号处理器包括连接到对应的输出FIR滤波器的ADC。 背景校准器还包括辅助信号处理器,其具有连接到至少一个对应的输出FIR滤波器的ADC。 此外,背景校准器还包括定时校准电路,其中定时校准电路被配置为选择主信号处理器中的一个,将辅助信号处理器与TIADC中选择的主信号处理器交换,并将所选择的主信号处理器连接到 定时校准电路。 在替代实施例中,定时校准电路还被配置为减少所选主信号处理器的定时失配。