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61. 发明授权

US06492071B1 Wafer scale encapsulation for integrated flip chip and surface mount technology assembly 失效
标题翻译：用于集成倒装芯片和表面贴装技术组装的晶圆级封装
公开(公告)号：US06492071B1
公开(公告)日：2002-12-10
申请号：US09670410
申请日：2000-09-26
申请人： William E. Bernier , Mark V. Pierson , Ajit K. Trivedi
发明人： William E. Bernier , Mark V. Pierson , Ajit K. Trivedi
IPC分类号： G03F900
CPC分类号： H01L21/56 , H01L24/81 , H01L2224/274 , H01L2224/81801 , H01L2224/83191 , H01L2924/14 , H05K3/1225 , H01L2924/00
摘要： A device and process for applying mixtures of adhesive formulations combined with solder flux such that flip chips may be rapidly encapsulated with such combinations without interfering with subsequent wafer processing steps are provided. Also provided is a wafer stencil designed in such a manner that the saw kerf lines separating individual chip dies are protected from coming into contact with the formulation. Extrusion screening using such wafer stencil is also provided.
摘要翻译：提供了一种用于施加与焊料助焊剂组合的粘合剂制剂的混合物的装置和方法，使得可以用这种组合快速包封倒装芯片而不干扰后续的晶片加工步骤。还提供了以这样的方式设计的晶片模板，即分离各个芯片模具的锯切线不受制剂的接触。还提供了使用这种晶片模板的挤出筛选。

62. 发明授权

US06429384B1 Chip C4 assembly improvement using magnetic force and adhesive 失效
标题翻译：芯片C4组装改进使用磁力和粘合剂
公开(公告)号：US06429384B1
公开(公告)日：2002-08-06
申请号：US09588836
申请日：2000-06-07
申请人： Francis J. Downes, Jr. , Robert M. Japp , Mark V. Pierson
发明人： Francis J. Downes, Jr. , Robert M. Japp , Mark V. Pierson
IPC分类号： H05K116
CPC分类号： H01L24/81 , B23K2101/40 , H01L2224/81801 , H01L2924/01006 , H01L2924/01033 , H01L2924/0105 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H05K3/303 , H05K3/3436 , Y10T29/4913 , Y10T29/53196
摘要： A structure that adhesively couples a chip to an organic chip carrier. The chip is attached to a top surface of the organic chip carrier by interfacing a solder bump between a C4 solder structure on the chip and a pad on a top surface of the chip carrier. The melting temperature of the solder bump is less than the melting temperature of the C4 solder structure. A block of ferrous material is on a top surface of the chip. A temporary or permanent stiffener of ferrous material is on the top surface of the chip carrier. A permanent magnet is coupled to a bottom surface of the chip carrier. Alternatively, an electromagnetic could be utilized instead of the electromagnet. Due to the permanent magnet or the electromagnet, a magnetic force on the stiffener is directed toward the magnet and substantially flattens the first surface of the chip carrier. Similarly, a magnetic force on the block is directed toward the magnet such that the electronic component and the chip carrier are held in alignment. After the solder bump has been reflowed at a temperature between the melting temperature of the solder bump and the melting temperature of the C4 solder structure, the solder bump is reconfigured. The magnetic force on the block frictionally clamps the reflowed solder between the C4 solder structure and the pad. After the chip and carrier are cooled, the C4 solder structure is adhesively and conductively coupled to the pad.
摘要翻译：将芯片与有机芯片载体粘接的结构。芯片通过在芯片上的C4焊料结构和芯片载体的顶表面上的焊盘之间接合焊料凸块来附接到有机芯片载体的顶表面。焊料凸点的熔化温度小于C4焊料结构的熔化温度。铁质材料块在芯片的顶表面上。铁质材料的临时或永久性加强件位于芯片载体的顶表面上。永磁体耦合到芯片载体的底表面。或者，可以使用电磁来代替电磁体。由于永磁体或电磁体，加强件上的磁力被引向磁体并且基本平坦化芯片载体的第一表面。类似地，块上的磁力指向磁体，使得电子部件和芯片载体保持对准。在焊料凸块的熔化温度和C4焊料结构的熔化温度之间的温度下回流焊料凸点之后，重新配置焊料凸点。块上的磁力摩擦地夹住C4焊料结构和焊盘之间的回流焊料。在芯片和载体被冷却之后，C4焊料结构粘合地并且导电地耦合到焊盘。

63. 发明授权

US06288559B1 Semiconductor testing using electrically conductive adhesives 失效
标题翻译：使用导电胶的半导体测试
公开(公告)号：US06288559B1
公开(公告)日：2001-09-11
申请号：US09050820
申请日：1998-03-30
申请人： William E. Bernier , Michael A. Gaynes , Wayne J. Howell , Mark V. Pierson , Ajit K. Trivedi , Charles G. Woychik
发明人： William E. Bernier , Michael A. Gaynes , Wayne J. Howell , Mark V. Pierson , Ajit K. Trivedi , Charles G. Woychik
IPC分类号： G01R3102
CPC分类号： G01R31/2886 , H01L2224/45144 , H01L2224/81385 , H01L2224/83101 , H05K3/321 , H01L2924/00
摘要： A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium. After the palladium-plated ECA is brought into contact with aluminum pads, palladium-coated aluminum pads, or even C4 solder bumps, conductive dendrites are formed on the palladium-treated ECA bumps.
摘要翻译：一种用于测试和燃烧半导体电路的方法和装置。该方法和装置允许通过使用导电粘合剂（ECA）将晶片临时附接到测试基板来测试整个晶片。 ECA符合晶片和测试基板的接触点的共平面偏差，同时在每个点提供质量电连接。 ECA材料可以沉积在晶片触点或衬底焊盘上。此外，ECA可以沉积在C4凸点或锡盖铅基上。该方法和装置的变化包括用ECA填充非导电插入件的通孔。可以通过在测试焊盘上形成导电枝晶而增加电连接，同时将ECA沉积在晶片触点上。为了进一步增强电连接，可以对ECA材料进行等离子体蚀刻以除去其一些聚合物基质并使一面上的导电颗粒暴露，然后用钯镀覆。在镀钯的ECA与铝焊盘，钯涂覆的铝焊盘或甚至C4焊料凸块接触之后，在钯处理的ECA凸块上形成导电枝晶。

64. 发明授权

US6129804A TFT panel alignment and attachment method and apparatus 失效
标题翻译： TFT面板对准和附接方法和装置
公开(公告)号：US6129804A
公开(公告)日：2000-10-10
申请号：US71675
申请日：1998-05-01
申请人： Michael A. Gaynes , Allan O. Johnson , Ramesh R. Kodnani , Mark V. Pierson , Edward J. Tasillo
发明人： Michael A. Gaynes , Allan O. Johnson , Ramesh R. Kodnani , Mark V. Pierson , Edward J. Tasillo
IPC分类号： B32B37/12 , G02F1/1333 , B32B31/00
CPC分类号： B32B38/18 , G02F1/13336 , B32B37/12 , Y10S345/903 , Y10T156/1089 , Y10T156/109 , Y10T156/1092 , Y10T156/1093 , Y10T156/1754 , Y10T156/1756 , Y10T156/1759
摘要： A system for aligning and attaching together a plurality of thin film transistor tiles for constructing a flat panel display. A coverplate loading station where a coverplate that the tiles are to be attached to is arranged on a coverplate support. A coverplate bonding material dispensing station where a bonding material for bonding the tiles to the coverplate is applied to a surface of the coverplate. A tile placement station where the tiles are arranged on the coverplate. A tile aligning and securing station where the tiles are aligned relative to each other and the coverplate by the tile aligner and where the tiles are at least partially bonded to the coverplate. A tile assembly bonding material dispensing station where a bonding material is applied to a surface of the tiles opposite the side that the coverplate is bonded to. A backplate placement station where a backplate is arranged on the tiles. A backplate aligning and securing station where the backplate is aligned with the tiles and the coverplate and at least partially secured to the tiles A full bonding station where the tiles are fully bonded to the coverplate and the backplate.
摘要翻译：一种用于对准和连接在一起的多个薄膜晶体管瓦片用于构建平板显示器的系统。一个盖板加载站，其中瓦片要附着的盖板布置在盖板支架上。一种覆盖板接合材料分配站，其中用于将瓦片粘合到盖板上的粘合材料施加到盖板的表面。瓦片布置台，其中瓦片布置在盖板上。瓦片对准和固定台，其中瓦片通过瓦片对准器相对于彼此并且盖板对准，并且瓦片至少部分地结合到盖板。一种瓦片组合接合材料分配站，其中粘合材料施加到瓦片与盖板粘合的一侧相反的表面。背板放置台，其中背板设置在瓦片上。背板对准和固定台，其中背板与瓦片和盖板对准并且至少部分地固定到瓦片完全粘合台，其中瓦片完全结合到盖板和背板。

65. 发明授权

US5638597A Manufacturing flexible circuit board assemblies with common heat spreaders 失效
标题翻译：制造具有普通散热器的柔性电路板组件
公开(公告)号：US5638597A
公开(公告)日：1997-06-17
申请号：US476759
申请日：1995-06-07
申请人： Lawrence R. Cutting , Michael A. Gaynes , Eric A. Johnson , Cynthia S. Milkovich , Jeffrey S. Perkins , Mark V. Pierson , Steven E. Poetzinger , Jerzy Zalesinski
发明人： Lawrence R. Cutting , Michael A. Gaynes , Eric A. Johnson , Cynthia S. Milkovich , Jeffrey S. Perkins , Mark V. Pierson , Steven E. Poetzinger , Jerzy Zalesinski
IPC分类号： H01L21/48 , H01L23/367 , H01L23/538 , H05K1/00 , H05K1/02 , H05K1/18 , H05K3/00 , H05K3/12 , H05K3/34 , H05K7/20 , H05K3/36
CPC分类号： H05K7/20454 , H01L21/4857 , H01L21/4867 , H01L23/3672 , H01L23/5387 , H05K1/021 , H05K1/189 , H05K3/0061 , H05K3/1216 , H05K3/4691 , H01L2224/16 , H01L2924/01078 , H01L2924/01322 , H05K1/0298 , H05K1/182 , H05K2201/0154 , H05K2201/09063 , H05K2201/096 , H05K2201/09745 , H05K2201/1056 , H05K2201/2009 , H05K2203/1394 , H05K3/3415 , H05K3/3452 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144
摘要： A multi-layer flexible circuit board has multiple thicker regions to which components are mounted and thinner, more flexible regions with fewer wiring layers through which the board can be bent about a line without bending thicker regions. Surface mount components such as QFP's and flip-chips are mounted on the front side, and surface mount and pin-in-hole components are mounted on the back side of the circuit board at the thick regions. Heat spreaders are laminated to the back sides of thicker regions. The thicker regions have windows in which wire bond chips are mounted on the heat spreader and wire bonded to the front side of the board. A thermally conductive adhesive or grease connects between the tops of the back side components and the bottoms of the cavities. The heat sinks are bolted together and/or to an enclosure frame to improve thermal performance.
摘要翻译：多层柔性电路板具有多个较厚的区域，组件安装在该较厚的区域上，较薄的，更柔性的区域具有较少的布线层，板可围绕线弯曲，而不会弯曲较厚的区域。表面安装部件如QFP和倒装芯片安装在前侧，表面安装和销孔组件安装在电路板的背面，在较厚的区域。散热器层压到较厚区域的背面。较厚的区域具有窗口，其中引线接合芯片安装在散热器上，并且引线键合到板的前侧。导热粘合剂或油脂连接在后侧部件的顶部和空腔的底部之间。散热器螺栓连接在一起和/或连接到外壳框架以改善热性能。

66. 发明授权

US5545465A Circuit board having a defined volume of solder or conductive adhesive deposited at interconnection sites for electrical circuits 失效
标题翻译：具有限定体积的焊料或导电粘合剂的电路板沉积在用于电路的互连位置处
公开(公告)号：US5545465A
公开(公告)日：1996-08-13
申请号：US449029
申请日：1995-05-24
申请人： Michael A. Gaynes , George D. Oxx , Mark V. Pierson , Jerzy Zalesinski
发明人： Michael A. Gaynes , George D. Oxx , Mark V. Pierson , Jerzy Zalesinski
IPC分类号： B05C5/02 , B23K3/06 , H01L21/48 , H01L21/60 , H05K3/12 , H05K3/32 , H05K3/34 , B32B9/00
CPC分类号： H01L24/27 , B23K3/0692 , H01L21/4853 , H01L21/4867 , H01L24/83 , H05K3/1233 , H05K3/3484 , B23K2201/36 , H01L2224/2919 , H01L2224/8319 , H01L2224/838 , H01L2924/01029 , H01L2924/01033 , H01L2924/01077 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/14 , H01L2924/3025 , H05K2201/0989 , H05K2203/0126 , H05K2203/043 , H05K2203/0568 , H05K2203/0577 , H05K3/321 , H05K3/3452 , Y10T29/49165 , Y10T428/24917
摘要： A method of applying bonding agents, such as solder pastes and conductive adhesives, to pad sites in the manufacture of electronic circuits uses a paste injection head. A permanent mask with cavity openings is applied around conductive pads on a carrier. The conductive pads correspond to chip attachment sites. The injection head is brought into contact with a surface of the mask, and pressure is applied to a bonding agent in the injection head. The injection head is then moved over the surface of the mask, filling cavity openings with the bonding agent. The injection head is then removed from the surface of the mask. If a solder paste is used, infrared radiation is applied to filled cavity openings to evaporate a paste flux and reflow solder to form solder balls within the cavity openings projecting above the mask. If a conductive adhesive is used, a stencil is applied to the surface of the mask prior to contacting the mask with said injection head. When the cavity openings are filled, stencil is removed from the mask and the conductive adhesive filling the cavity openings is dried.
摘要翻译：在电子电路的制造中将焊接剂和导电粘合剂等粘合剂施加到焊盘部位的方法使用糊剂注入头。具有腔体开口的永久性掩模施加在载体上的导电焊盘周围。导电垫对应于芯片附接位置。使注射头与掩模的表面接触，并且将压力施加到注射头中的粘合剂。然后将注射头移动到掩模的表面上，用粘合剂填充空腔开口。然后将注射头从掩模的表面去除。如果使用焊膏，则将红外线辐射施加到填充的空腔开口，以蒸发浆料焊剂并回流焊料，以在突出在掩模上方的空腔开口内形成焊球。如果使用导电粘合剂，则在将掩模与所述注射头接触之前，将模板施加到掩模的表面。当腔开口被填充时，将模板从掩模中取出，并且填充空腔开口的导电粘合剂被干燥。

67. 发明授权

US5528159A Method and apparatus for testing integrated circuit chips 失效
公开(公告)号：US5528159A
公开(公告)日：1996-06-18
申请号：US454458
申请日：1995-05-30
申请人： Richard G. Charlton , George C. Correia , Mark A. Couture , Gary R. Hill , Kibby B. Horsford , Anthony P. Ingraham , Michael D. Lowell , Voya R. Markovich , Gordon C. Osborne, Jr. , Mark V. Pierson
发明人： Richard G. Charlton , George C. Correia , Mark A. Couture , Gary R. Hill , Kibby B. Horsford , Anthony P. Ingraham , Michael D. Lowell , Voya R. Markovich , Gordon C. Osborne, Jr. , Mark V. Pierson
IPC分类号： G01R1/04 , G01R1/073 , G01R31/28
CPC分类号： G01R31/2863 , G01R1/0483 , G01R1/07307 , G01R31/2886
摘要： A method and apparatus for testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O contacts. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relative loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts. Testing of the chip is then performed. The tests may include heating of the chip as well as the application of signals to the chip contacts. After testing the chip is removed from the substrate.

68. 发明授权

US5420520A Method and apparatus for testing of integrated circuit chips 失效
标题翻译：用于集成电路芯片测试的方法和装置
公开(公告)号：US5420520A
公开(公告)日：1995-05-30
申请号：US76069
申请日：1993-06-11
申请人： Morris Anschel , Anthony P. Ingraham , Charles R. Lamb , Michael D. Lowell , Voya R. Markovich , Wolfgang Mayr , Richard G. Murphy , Mark V. Pierson , Tamar A. Powers , Timothy S. Reny , Scott D. Reynolds , Bahgat G. Sammakia , Wayne R. Storr
发明人： Morris Anschel , Anthony P. Ingraham , Charles R. Lamb , Michael D. Lowell , Voya R. Markovich , Wolfgang Mayr , Richard G. Murphy , Mark V. Pierson , Tamar A. Powers , Timothy S. Reny , Scott D. Reynolds , Bahgat G. Sammakia , Wayne R. Storr
IPC分类号： G01R31/26 , G01R31/28 , H01L21/66 , H01R13/02 , G01R1/073 , G01R31/02
CPC分类号： G01R31/2863 , G01R31/2886 , G01R31/2862 , G01R31/287 , G01R31/2877 , G01R31/2879
摘要： A method of testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip test fixture system is provided. The chip test fixture system has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into electrically conductive contact with the conductor pads on the chip test fixture system. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing the chip is removed from the substrate.
摘要翻译：公开了一种测试半导体芯片的方法。单个半导体芯片具有I / O，电源和接地触点。在本发明的方法中，提供了一种芯片测试夹具系统。芯片测试夹具系统具有对应于半导体芯片上的触点的触点。载体触点具有树枝状表面。芯片触点与芯片测试夹具系统上的导体焊盘导电接触。测试信号输入矢量被施加到半导体芯片的输入，从半导体芯片恢复输出信号矢量。测试后，芯片从基板上取下。

69. 发明授权

US4030180A Longitudinally fed component insertion apparatus 失效
标题翻译：纵向进给部件插入装置
公开(公告)号：US4030180A
公开(公告)日：1977-06-21
申请号：US689249
申请日：1976-05-24
申请人： Mark V. Pierson
发明人： Mark V. Pierson
IPC分类号： H01L23/32 , H05K13/04 , H05K3/30
CPC分类号： H05K13/0439 , Y10T29/53183
摘要： An electronic component insertion apparatus having an inserter assembly rotatable from a drive position to a feed position where a feeding subassembly feeds a component along the longitudinal axis of the inserter assembly into the inserter and subsequently the inserter assembly is rotated back to the drive position where it is driven along its longitudinal axis to insert the component into a circuit board.
摘要翻译：一种电子部件插入装置，具有可从驱动位置旋转到进给位置的插入器组件，其中进给子组件沿着插入器组件的纵向轴线将部件馈送到插入器中，随后将插入器组件旋转回驱动位置，沿着其纵向轴线被驱动以将部件插入电路板。

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