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61. 发明授权

US5652723A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5652723A
公开(公告)日：1997-07-29
申请号：US869917
申请日：1992-04-15
申请人： Katsumi Dosaka , Masaki Kumanoya , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Konishi , Katsumitsu Himukashi , Yasuhiro Ishizuka , Tsukasa Saiki
发明人： Katsumi Dosaka , Masaki Kumanoya , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Konishi , Katsumitsu Himukashi , Yasuhiro Ishizuka , Tsukasa Saiki
IPC分类号： G06F12/08 , G11C7/00 , G11C7/10 , G11C7/22 , G11C8/00 , G11C8/12 , G11C11/00 , G11C13/00
CPC分类号： G11C8/00 , G11C11/005 , G11C11/4076 , G11C11/4097 , G11C11/413 , G11C7/10 , G11C7/1018 , G11C7/1045 , G11C7/22 , G11C8/12 , G06F12/0893 , G11C2207/002 , G11C2207/2227 , G11C2207/2245 , Y02B60/1225
摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.
摘要翻译：半导体存储器件包括DRAM，SRAM和设置在SRAM和DRAM之间的双向传输门电路。 SRAM阵列包括多组字线。在SRAM阵列的每行中提供每组，并且每组中的每个字线连接到相关行的不同组的存储单元。 SRAM的地址信号和DRAM的地址信号分别应用于地址缓冲器。半导体存储器件还包括用于实现突发模式和睡眠模式的附加功能控制电路。从DRAM到SRAM的数据传输路径以及从SRAM到DRAM的数据传输路径分别设置在双向传输门电路中。数据写入路径和数据读取路径分别设置在DRAM阵列中。通过上述结构，在睡眠模式中停止缓冲电路的动作，降低功耗。由于数据写入路径和数据读取路径分别设置在DRAM阵列中，所以可以以非多路复用的方式应用DRAM阵列的地址，从而数据可以从DRAM阵列以高速传输到SRAM阵列，使得能够高高速运行即使在缓存未命中。

62. 发明授权

US5592434A Synchronous semiconductor memory device 失效
标题翻译：同步半导体存储器件
公开(公告)号：US5592434A
公开(公告)日：1997-01-07
申请号：US548285
申请日：1995-10-25
申请人： Hisashi Iwamoto , Yasuhiro Konishi , Katsumi Dosaka , Yasumitsu Murai
发明人： Hisashi Iwamoto , Yasuhiro Konishi , Katsumi Dosaka , Yasumitsu Murai
IPC分类号： G11C11/409 , G11C7/10 , G11C11/401 , G11C11/407 , G11C7/00
CPC分类号： G11C7/1048 , G11C7/1072
摘要： To one memory array, global signal input/output line pairs in two systems, a switch for connecting the global IO line pairs to a write buffer group alternately on a clock cycle basis, and another switch for connecting the global IO line pairs to an equalize circuit alternately on a clock cycle basis are provided. During one clock cycle, writing of data through one global IO line pair and equalization of the other global IO line pair can be carried out in parallel. Therefore, data can be written easily at a high frequency.
摘要翻译：对于一个存储器阵列，两个系统中的全局信号输入/输出线对，用于以时钟周期交替地将全局IO线对连接到写缓冲器组的开关，以及用于将全局IO线对连接到等于提供了基于时钟周期的交替电路。在一个时钟周期内，可以并行执行通过一个全局IO线对写入数据和对另一个全局IO线对进行均衡。因此，可以高频地容易地写入数据。

63. 发明授权

US5587950A Test circuit in clock synchronous semiconductor memory device 失效
公开(公告)号：US5587950A
公开(公告)日：1996-12-24
申请号：US461907
申请日：1995-06-05
申请人： Seiji Sawada , Yasuhiro Konishi
发明人： Seiji Sawada , Yasuhiro Konishi
IPC分类号： G11C11/401 , G11C11/407 , G11C11/409 , G11C29/00 , G11C29/26 , G11C29/34 , G11C29/40 , G11C7/00
CPC分类号： G11C29/40 , G11C29/26
摘要： In order to reduce a test time for a synchronous type memory device, a compression circuit compresses a plurality of memory cell data which are inputted in a plurality of read registers provided for a data output terminal to 1-bit data. A bank selection circuit selects an output of the compression circuit of either a bank #A or a bank #B. A tristate inverter buffer passes the 1-bit compression data selected by the bank selection circuit in accordance with a test mode command signal. The data output terminal outputs compressed data of a plurality of bits of memory cells. Thus, it is possible to simultaneously determine pass/fail of a plurality of memory cells, thereby reducing the test time.

64. 发明授权

US5559750A Semiconductor memory device 失效
公开(公告)号：US5559750A
公开(公告)日：1996-09-24
申请号：US465472
申请日：1995-06-05
申请人： Katsumi Dosaka , Masaki Kumanoya , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Konishi , Katsumitsu Himukashi , Yasuhiro Ishizuka , Tsukasa Saiki
发明人： Katsumi Dosaka , Masaki Kumanoya , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Konishi , Katsumitsu Himukashi , Yasuhiro Ishizuka , Tsukasa Saiki
IPC分类号： G06F12/08 , G11C7/00 , G11C7/10 , G11C7/22 , G11C8/00 , G11C8/12 , G11C11/00 , G11C13/00
CPC分类号： G11C8/00 , G11C11/005 , G11C11/4076 , G11C11/4097 , G11C11/413 , G11C7/10 , G11C7/1018 , G11C7/1045 , G11C7/22 , G11C8/12 , G06F12/0893 , G11C2207/002 , G11C2207/2227 , G11C2207/2245 , Y02B60/1225
摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

65. 发明授权

US5471430A Test circuit for refresh counter of clock synchronous type semiconductor memory device 失效
标题翻译：时钟同步型半导体存储器件刷新计数器的测试电路
公开(公告)号：US5471430A
公开(公告)日：1995-11-28
申请号：US245784
申请日：1994-05-19
申请人： Seiji Sawada , Yasuhiro Konishi
发明人： Seiji Sawada , Yasuhiro Konishi
IPC分类号： G11C11/401 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/409 , G11C29/00 , G11C29/02 , G11C29/08 , G11C11/34
CPC分类号： G11C29/02 , G11C11/406
摘要： A synchronous semiconductor memory device includes an automatic refresh detection circuit for detecting that an automatic refresh mode is specified in accordance with an automatic refresh command, an address counter for generating a refresh address, a refresh execution unit for refreshing a memory array in accordance with an automatic refresh detection signal and the refresh address, an inactivation circuit for inactivating the refresh execution unit after a lapse of a prescribed time in accordance with the automatic refresh detection signal, a counter check mode detection circuit for bringing the inactivation circuit into an inoperable state in accordance with a counter check mode command, and a second inactivation circuit for inactivating the refresh execution unit in accordance with a precharge detection signal generated in response to a precharge command. Thus synchronous semiconductor memory device with an operation mode which can test the function of an internal refresh address counter is provided.
摘要翻译：同步半导体存储器件包括自动刷新检测电路，用于检测根据自动刷新命令指定自动刷新模式，用于产生刷新地址的地址计数器，用于根据存储器阵列刷新存储器阵列的刷新执行单元自动刷新检测信号和刷新地址，用于根据自动刷新检测信号在经过规定时间之后使刷新执行单元失活的灭活电路，用于使灭活电路处于不可操作状态的计数器检查模式检测电路根据计数器检查模式命令，以及第二失活电路，用于根据预充电命令产生的预充电检测信号，使刷新执行单元失效。因此，提供了具有可以测试内部刷新地址计数器的功能的操作模式的同步半导体存储器件。

66. 发明授权

US5359215A Semiconductor memory cell for holding data with small power consumption 失效
标题翻译：用于保存具有小功耗的数据的半导体存储单元
公开(公告)号：US5359215A
公开(公告)日：1994-10-25
申请号：US795865
申请日：1991-11-22
申请人： Yasuhiro Konishi
发明人： Yasuhiro Konishi
IPC分类号： G11C11/402 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10808
摘要： A DRAM includes an N-type well formed on a main surface of a P-type semiconductor substrate, an N-type impurity region formed on the main surface of the P-type semiconductor substrate, a P-type impurity region formed in the N-type well to be a storage node of a memory capacitor, and a polycrystalline silicon layer for connecting the P-type impurity region and the N-type impurity region. The N-type impurity layer, the P-type impurity layer, and the polycrystalline silicon layer constitute the storage node of the memory capacitor, and electrons of minority carriers flowing from the substrate to the N-type impurity layer are recombined with holes flowing from the N-type well to the P-type impurity layer.
摘要翻译： DRAM包括在P型半导体衬底的主表面上形成的N型阱，形成在P型半导体衬底的主表面上的N型杂质区，形成在N型杂质区中的N型杂质区型是存储电容器的存储节点，以及用于连接P型杂质区域和N型杂质区域的多晶硅层。 N型杂质层，P型杂质层和多晶硅层构成存储电容器的存储节点，并且从衬底流到N型杂质层的少数载流子的电子与从 N型阱到P型杂质层。

67. 发明授权

US5270977A Dynamic random access memory device capable of performing test mode operation and method of operating such memory device 失效
标题翻译：能够执行测试模式操作的动态随机存取存储器件以及操作该存储器件的方法
公开(公告)号：US5270977A
公开(公告)日：1993-12-14
申请号：US751934
申请日：1991-09-03
申请人： Hisashi Iwamoto , Masaki Kumanoya , Katsumi Dosaka , Yasuhiro Konishi , Akira Yamazaki
发明人： Hisashi Iwamoto , Masaki Kumanoya , Katsumi Dosaka , Yasuhiro Konishi , Akira Yamazaki
IPC分类号： G01R31/28 , G11C7/00 , G11C11/401 , G11C11/406 , G11C29/00 , G11C29/14 , G11C29/46 , H01L21/66 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： G11C11/4072 , G11C11/46 , G11C29/46
摘要： Disclosed is a DRAM including a test mode operation capable of testing whether a plurality of memory cells are defective or not in a short time. The DRAM includes a power-on detection signal generator, a power-on reset signal generator, and a test mode instruction signal generator. The power-on detection signal generator detects application of a power supply voltage and generates a power-on detection signal. The power-on reset signal generator is reset by a power-on reset signal, counts at least once an external RAS signal applied after reset and generates a power-on reset signal. The test mode instruction signal generator detects logic states of an internal RAS signal, an internal CAS signal and an internal W signal applied after the power-on reset and generates a test mode instructing signal.
摘要翻译：公开了一种包括能够在短时间内测试多个存储单元是否有故障的测试模式操作的DRAM。 DRAM包括上电检测信号发生器，上电复位信号发生器和测试模式指令信号发生器。上电检测信号发生器检测电源电压的应用并产生上电检测信号。上电复位信号发生器由上电复位信号复位，至少在复位后施加一次外部和上升沿和R信号并产生上电复位信号。测试模式指令信号发生器检测内部RAS信号，内部CAS信号和上电复位后施加的内部W信号的逻辑状态，并产生测试模式指令信号。

68. 再颁专利

USRE34463E Semiconductor memory device with active pull up 失效
标题翻译：具有主动上拉功能的半导体存储器件
公开(公告)号：USRE34463E
公开(公告)日：1993-11-30
申请号：US662663
申请日：1991-02-28
申请人： Yasuhiro Konishi , Kazuyasu Fujishima , Masaki Kumanoya , Hideshi Miyatake , Hideto Hidaka , Katsumi Dosaka
发明人： Yasuhiro Konishi , Kazuyasu Fujishima , Masaki Kumanoya , Hideshi Miyatake , Hideto Hidaka , Katsumi Dosaka
IPC分类号： G11C11/4076 , G11C11/4094 , G11C7/00 , G11C11/40
CPC分类号： G11C11/4094 , G11C11/4076
摘要： A MOS dynamic type RAM comprises memory cells (10), dummy cells (11), bit line pairs (BL, BL), word lines (WL), dummy word lines (DWL) and sense amplifiers (12). In a non-active cycle, the potentials of each pair of bit lines (BL, BL) are precharged at 1/2 of a supply potential V.sub.CC. Each sense amplifier (12) operates in an active cycle following the non-active cycle, while each active pull-up circuit (13) pulls up the potential of a higher level one of the pair of bit lines to V.sub.CC. This active cycle is defined by an internal RAS internal signal, which is generated by a NAND circuit (27) in response to an external RAS signal and an RPW signal obtained by delaying the external RAS signal by a delay circuit (20) and having a trailing edge obtained by delaying the trailing edge of the external RAS signal by a prescribed period.

69. 发明授权

US5010259A Voltage boosting circuit and operating method thereof 失效
标题翻译：升压电路及其工作方法
公开(公告)号：US5010259A
公开(公告)日：1991-04-23
申请号：US454580
申请日：1989-12-21
申请人： Yoshinori Inoue , Masaki Kumanoya , Takahiro Komatsu , Yasuhiro Konishi , Katsumi Dosaka
发明人： Yoshinori Inoue , Masaki Kumanoya , Takahiro Komatsu , Yasuhiro Konishi , Katsumi Dosaka
IPC分类号： G11C11/407 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H02M3/07 , H03K5/02 , H03K19/017 , H03K19/094
CPC分类号： H03K19/01714
摘要： An input signal is inverted by a CMOS inverter and provided for an output signal line. The CMOS inverter is provided between a power supply and a ground, and its node on the side of the power supply is charged all the time to prevent the potential thereof from being lowered. An output signal provided for the output signal line is delayed by a delay circuit to be applied to a boosting capacitor. The potential of the node is further boosted by this boosting capacitor. Consequently, the potential of the output signal is also boosted. When the potential of the node is raised higher than a supply voltage, an N channel MOSFET for charging is turned off to prevent a reverse flow of a charge.
摘要翻译：输入信号由CMOS反相器反相并提供给输出信号线。 CMOS反相器设置在电源和地之间，并且其电源侧的节点一直被充电以防止其电位降低。为输出信号线提供的输出信号被延迟电路延迟以施加到升压电容器。该升压电容器进一步提升了节点的电位。因此，输出信号的电位也得到提升。当节点的电位升高到高于电源电压时，用于充电的N沟道MOSFET关闭，以防止电荷反向流动。

70. 发明授权

US4843596A Semiconductor memory device with address transition detection and timing control 失效
标题翻译：具有地址转换检测和定时控制的半导体存储器件
公开(公告)号：US4843596A
公开(公告)日：1989-06-27
申请号：US124554
申请日：1987-11-24
申请人： Hideshi Miyatake , Masaki Kumanoya , Hideto Hidaka , Yasuhiro Konishi , Katsumi Dosaka , Hiroyuki Yamasaki , Masaki Shimoda , Yuto Ikeda , Kazuhiro Tsukamoto
发明人： Hideshi Miyatake , Masaki Kumanoya , Hideto Hidaka , Yasuhiro Konishi , Katsumi Dosaka , Hiroyuki Yamasaki , Masaki Shimoda , Yuto Ikeda , Kazuhiro Tsukamoto
IPC分类号： G11C11/401 , G11C7/22 , G11C8/18
CPC分类号： G11C8/18 , G11C7/22
摘要： A novel semiconductor memory device includes an address detection circuit that produces a short-width pulse in response to the detection of an address change. A column decoder-activating signal generator detects the start of the short-width pulse and in response generates a column decoder-activating signal. A second detection circuit detects the conclusion of the short-width pulse and generates a second pulse that triggers a preamplifier-activating signal that activates a preamplifier and latches the data that is present on the input/output line. A reset signal generator produces a reset signal to deactivate the column decoder-activating signal and to delay the preamplifier-activating signal. The preamplifier-activating signal generator and the reset signal generator are reset while the first pulse is output.
摘要翻译：一种新颖的半导体存储器件包括响应于地址变化的检测而产生短宽度脉冲的地址检测电路。列解码器激活信号发生器检测短宽度脉冲的开始，并且响应于产生列解码器激活信号。第二检测电路检测短宽度脉冲的结论，并产生触发前置放大器激活信号的第二脉冲，其激活前置放大器并锁存输入/输出线上存在的数据。复位信号发生器产生复位信号以停用列解码器激活信号并延迟前置放大器激活信号。当输出第一个脉冲时，前置放大器激活信号发生器和复位信号发生器被复位。

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