专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US5774679A Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgement 失效
公开(公告)号：US5774679A
公开(公告)日：1998-06-30
申请号：US774614
申请日：1996-12-30
申请人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
发明人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
IPC分类号： G06F13/362 , G06F13/00 , G06F13/12 , G06F13/364 , G06F13/38 , G06F13/42 , G06F13/14
CPC分类号： G06F13/364
摘要： An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before. Thus, the address to be transferred can be transferred to the module ready to accept the address, in only one cycle.

62. 发明授权

US5754802A Increasing data transfer efficiency for a read operation in a non-split transaction bus environment by substituting a write operation for the read operation 失效
标题翻译：通过将读取操作替换为读取操作，在非分割事务总线环境中提高数据传输效率
公开(公告)号：US5754802A
公开(公告)日：1998-05-19
申请号：US648424
申请日：1996-05-15
申请人： Koichi Okazawa , Hideki Osaka , Kenichi Saitou
发明人： Koichi Okazawa , Hideki Osaka , Kenichi Saitou
IPC分类号： G06F13/36 , G06F13/12 , G06F13/40 , G06F13/42 , G06F13/00
CPC分类号： G06F13/423 , G06F13/126 , G06F13/4027 , G06F13/4036
摘要： A method and apparatus for increasing data transfer efficiency for a read operation in a non-split transaction bus environment by substituting a write operation for the read operation. The data transfer efficiency is increased and deadlocking is reduced by substituting two write operations (one from an I/O device to a bus controller and the other from the bus controller to the I/O device) for one read operation. Further, the present invention improves the efficiency of data transfer by maintaining the compatibility of a bus specification when DMA of an I/O bus having no split transfer function, such as a PCI bus or inter-I/O transfer, is executed. A processor instructs a data transfer operation to an I/O device or bus conversion adapter. The I/O device or bus conversion adapter connected to a bus outputs a write access, and a bus connection controller connected to the bus receives the write access and reads data in a main memory. The bus connection controller then transfers read data to the I/O device or the bus conversion adapter. Such an operation may also be performed between two I/O devices or bus conversion adapters.
摘要翻译：一种用于通过将写入操作替换为读取操作来增加在非分割事务总线环境中的读取操作的数据传输效率的方法和装置。通过将两个写入操作（一个从I / O设备到总线控制器，另一个从总线控制器到I / O设备）替换为一次读取操作，数据传输效率提高并且死锁降低。此外，本发明通过在不执行诸如PCI总线或I / O转移之类的分离传递功能的I / O总线的DMA执行时，通过维持总线规格的兼容性来提高数据传输的效率。处理器指示对I / O设备或总线转换适配器的数据传输操作。连接到总线的I / O设备或总线转换适配器输出写访问，连接到总线的总线连接控制器接收写入访问并读取主存储器中的数据。总线连接控制器然后将读取的数据传送到I / O设备或总线转换适配器。这样的操作也可以在两个I / O设备或总线转换适配器之间执行。

63. 发明授权

US4943857A Synchronizing circuit for an external signal and an internal sampling clock signal 失效
标题翻译：外部信号同步电路和内部采样时钟信号
公开(公告)号：US4943857A
公开(公告)日：1990-07-24
申请号：US184394
申请日：1988-04-21
申请人： Nobuaki Izuno , Yasuo Kurosu , Koichi Okazawa , Yoshihiro Yokoyama , Kensuke Ooyu
发明人： Nobuaki Izuno , Yasuo Kurosu , Koichi Okazawa , Yoshihiro Yokoyama , Kensuke Ooyu
IPC分类号： H03L7/081 , H04N5/04
CPC分类号： H04N5/04 , H03L7/0814
摘要： A video signal and a horizontal synchronizing signal provided from a work station are delayed by a plurality of delay circuits having different delay amounts, and phase differences between a sampling clock signal and the delayed signals are detected. A clock generator generates two kinds of clock pulses having opposite phases and the same frequency. A clock selector selects one of the clock pulses as a sampling pulse signal in response to the phase differences. Further, a phase difference between the horizontal synchronizing signal and the video signal is detected so that the phase difference between the horizontal synchronizing signal and the video signal is maintained constant.
摘要翻译：从工作站提供的视频信号和水平同步信号由具有不同延迟量的多个延迟电路延迟，并且检测采样时钟信号和延迟信号之间的相位差。时钟发生器产生具有相反相位和相同频率的两种时钟脉冲。时钟选择器响应于相位差选择时钟脉冲之一作为采样脉冲信号。此外，检测水平同步信号和视频信号之间的相位差，使得水平同步信号和视频信号之间的相位差保持恒定。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式