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61. 发明授权

US08327235B2 Error-floor mitigation of error-correction codes by changing the decoder alphabet 有权
标题翻译：通过更改解码器字母表错误地减轻纠错码
公开(公告)号：US08327235B2
公开(公告)日：2012-12-04
申请号：US12420535
申请日：2009-04-08
申请人： Kiran Gunnam
发明人： Kiran Gunnam
IPC分类号： G06F11/00
CPC分类号： H03M13/1111 , H03M13/09 , H03M13/1142 , H03M13/3707 , H03M13/3738 , H03M13/3753 , H03M13/451
摘要： In one embodiment, an LDPC decoder has one or more reconfigurable adders that generate variable-node messages and one or more reconfigurable check-node units (CNUs) that generate check-node messages. The LDPC decoder has a five-bit precision mode in which the reconfigurable adders and CNUs are configured to process five-bit variable-node and check-node messages, respectively. If the LDPC decoder is unable to properly decode codewords in five-bit precision mode, then the decoder can be reconfigured in real time into a ten-bit precision mode in which the reconfigurable adders and CNUs are configured to process ten-bit variable-node and check-node messages, respectively. By increasing the size of the variable-node and check-node messages from five bits to ten bits, the probability that the LDPC decoder will decode the codeword correctly may be increased.
摘要翻译：在一个实施例中，LDPC解码器具有生成可变节点消息的一个或多个可重构加法器和产生校验节点消息的一个或多个可重新配置的校验节点单元（CNU）。 LDPC解码器具有五位精度模式，其中可配置加法器和CNU被配置为分别处理五位可变节点和校验节点消息。如果LDPC解码器不能以五比特精度模式正确地解码码字，则可以将解码器实时重新配置为十位精度模式，其中可配置加法器和CNU被配置为处理十位可变节点和检查节点消息。通过将可变节点和校验节点消息的大小从5比特增加到10比特，可以增加LDPC解码器正确地解码码字的概率。

62. 发明授权

US08291292B1 Optimizing error floor performance of finite-precision layered decoders of low-density parity-check (LDPC) codes 有权
标题翻译：优化低密度奇偶校验（LDPC）码的有限精密分层解码器的误码性能
公开(公告)号：US08291292B1
公开(公告)日：2012-10-16
申请号：US12350052
申请日：2009-01-07
申请人： Nedeljko Varnica , Gregory Burd , Kiran Gunnam
发明人： Nedeljko Varnica , Gregory Burd , Kiran Gunnam
IPC分类号： H03M13/00
CPC分类号： G06F11/073 , H03M13/1102 , H03M13/1114 , H03M13/1117 , H03M13/114 , H03M13/116 , H03M13/6577 , H03M13/6591
摘要： Systems and methods are provided for selecting precisions during iterative decoding with a low-density parity check (LDPC) decoder in order to maximize LDPC code's performance in the error floor region. The selection of the precision of the messages may be done in such a way as to avoid catastrophic errors and to minimize the number of near-codeword errors during the decoding process. Another system and method to avoid catastrophic errors in the layered (serial) LDPC decoder is provided. Lastly, a system and method that select precisions and provide circuitry that optimizes the exchange of information between a soft-input, soft-output (SISO) channel detector and an error correction code (ECC) decoder for channels with memory is provided.
摘要翻译：提供了用于在利用低密度奇偶校验（LDPC）解码器的迭代解码期间选择精度的系统和方法，以便最大化LDPC码在错误楼层区域的性能。消息的精确度的选择可以以避免灾难性错误并且在解码过程期间最小化近似码字错误的数量的方式来完成。提供了在分层（串行）LDPC解码器中避免灾难性错误的另一种系统和方法。最后，提供了一种系统和方法，其提供优化软输入，软输出（SISO）信道检测器和用于具有存储器的信道的纠错码（ECC）解码器）之间的信息交换的精度和提供电路。

63. 发明申请

US20120099670A1 COMMUNICATIONS SYSTEM SUPPORTING MULTIPLE SECTOR SIZES 有权
标题翻译：通信系统支持多个扇区尺寸
公开(公告)号：US20120099670A1
公开(公告)日：2012-04-26
申请号：US12910993
申请日：2010-10-25
申请人： Kiran Gunnam
发明人： Kiran Gunnam
IPC分类号： H04L27/00
CPC分类号： H04L1/0067 , H04L1/0052 , H04L1/007
摘要： In one embodiment, a configurable communications system accommodates a plurality of different transmission word sizes. In a transmit path, the system inserts a number of padding bits corresponding to missing user-data bits onto the end of an input data sequence to generate a set of data having N bits. The N bits are interleaved and error-correction (EC) encoded to generate parity bits corresponding to an EC codeword. The parity bits are de-interleaved and multiplexed with the input data stream to generate a transmission word. In a receive path, a channel detector recovers channel values corresponding to the transmission word. Padding values, corresponding to the missing-bit locations, are inserted among the channel values. The resulting channel values are interleaved and EC decoded to recover the EC codeword. The data bits of the codeword are de-interleaved, and the padding bits corresponding to the missing channel values are discarded.
摘要翻译：在一个实施例中，可配置通信系统容纳多个不同的传输字大小。在发送路径中，系统将对应于丢失的用户数据比特的多个填充比特插入到输入数据序列的末尾以产生具有N比特的数据集合。 N位被交织和纠错（EC）编码，以产生对应于EC码字的奇偶校验位。奇偶校验位与输入数据流进行解交织和多路复用以产生传输字。在接收路径中，信道检测器恢复对应于传输字的信道值。对应于丢失位位置的填充值插入通道值之间。所得到的信道值被交织和EC解码以恢复EC码字。码字的数据位被解交织，并且丢弃与丢失的信道值对应的填充位。

64. 发明申请

US20120030539A1 ERROR-FLOOR MITIGATION OF CODES USING WRITE VERIFICATION 有权
标题翻译：使用写入验证错误地减少代码
公开(公告)号：US20120030539A1
公开(公告)日：2012-02-02
申请号：US12994288
申请日：2009-04-21
申请人： Nils Graef , Kiran Gunnam
发明人： Nils Graef , Kiran Gunnam
IPC分类号： H03M13/05 , G06F11/10 , H03M13/29
CPC分类号： H03M13/1102 , G06F11/1012 , G11B20/1833 , G11B2020/1823 , G11B2020/185 , G11B2220/2516 , G11B2220/61 , H03M13/1108 , H03M13/1142 , H03M13/455
摘要： Executed when a channel input (e.g., LDPC) codeword is written to a storage medium, a write-verification method (i) compares the channel input codeword to the written codeword, (ii) identifies any erroneous too bits, and (iii) stores the erroneous-bit indices to a record in a table. At some later time, the written codeword is read and sent to a decoder. If the decoder fails with a near codeword, a write-error recovery process searches the table and retrieves the erroneous-bit information. The codeword bits at those indices are adjusted, and the modified codeword is submitted to further processing.
摘要翻译：当将信道输入（例如，LDPC）码字写入存储介质时执行，写入验证方法（i）将信道输入码字与写入的码字进行比较，（ii）识别任何错误的位，以及（iii）存储表中的记录的错误位索引。在稍后的时间，写入的码字被读取并发送到解码器。如果解码器出现接近码字失败，则写入错误恢复过程将搜索表并检索错误位信息。调整这些索引处的码字比特，并且修改的码字被提交进一步处理。

65. 发明申请

US20110264987A1 Systems and Methods for Low Density Parity Check Data Encoding 有权
标题翻译：低密度奇偶校验数据编码系统与方法
公开(公告)号：US20110264987A1
公开(公告)日：2011-10-27
申请号：US12767761
申请日：2010-04-26
申请人： Zongwang Li , Kiran Gunnam , Shaohua Yang
发明人： Zongwang Li , Kiran Gunnam , Shaohua Yang
IPC分类号： H03M13/07 , G06F11/10 , H03M13/05
CPC分类号： H03M13/118 , H03M13/116 , H03M13/611
摘要： Various embodiments of the present invention provide systems and methods for encoding data. As an example, a data encoding circuit is disclosed that includes a first stage data encoder circuit and a second stage data encoder circuit. The first stage data encoder circuit is operable to provide a first stage output. The first stage data encoder circuit includes a first vector multiplier circuit operable to receive a data input and to multiply the data input by a first sparse matrix to yield a first interim value. The second stage encoder circuit includes a second vector multiplier circuit operable to multiply the first stage output by a second sparse matrix to yield a second interim value.
摘要翻译：本发明的各种实施例提供了用于编码数据的系统和方法。作为示例，公开了包括第一级数据编码器电路和第二级数据编码器电路的数据编码电路。第一级数据编码器电路可操作以提供第一级输出。第一级数据编码器电路包括第一向量乘法器电路，其可操作以接收数据输入，并将输入的数据乘以第一稀疏矩阵以产生第一临时值。第二级编码器电路包括第二矢量乘法器电路，其可操作以将第一级输出乘以第二稀疏矩阵以产生第二中间值。

66. 发明申请

US20110131462A1 MATRIX-VECTOR MULTIPLICATION FOR ERROR-CORRECTION ENCODING AND THE LIKE 有权
标题翻译：用于错误校正编码的矩阵矢量多项式和类似
公开(公告)号：US20110131462A1
公开(公告)日：2011-06-02
申请号：US12644161
申请日：2009-12-22
申请人： Kiran Gunnam
发明人： Kiran Gunnam
IPC分类号： H03M13/13 , G06F5/01 , G06F17/16 , G06F11/10
CPC分类号： H03M13/1102 , G06F17/16 , H03M13/616
摘要： In one embodiment, a matrix-vector multiplication (MVM) component generates a product vector based on (i) an input matrix and (ii) an input vector. The MVM component has a permuter, memory, and an XOR gate array. The permuter permutates, for each input sub-vector of the input vector, the input sub-vector based on a set of permutation coefficients to generate a set of permuted input sub-vectors. The memory stores a set of intermediate product sub-vectors corresponding to the product vector. The XOR gate array performs, for each input sub-vector, exclusive disjunction on (i) the set of permuted input sub-vectors and (ii) the set of intermediate product sub-vectors to update the set of intermediate product subvectors, such that all of the intermediate product sub-vectors in the set are updated based on a current input sub-vector before updating any of the intermediate product sub-vectors in the set based on a subsequent input sub-vector.
摘要翻译：在一个实施例中，矩阵向量乘法（MVM）分量基于（i）输入矩阵和（ii）输入向量生成乘积向量。 MVM组件具有permuter，memory和XOR门阵列。对于输入向量的每个输入子向量，置换器基于一组置换系数来输入输入子向量，以生成一组经排列的输入子向量。存储器存储对应于乘积向量的一组中间乘积子向量。 XOR门阵列对于每个输入子向量执行（i）置换的输入子向量集合的独占分离，以及（ii）用于更新所述一组中间乘积子向量的集合，使得基于随后的输入子向量，在更新集合中的任何中间乘积子向量之前，基于当前输入子向量来更新集合中的所有中间乘积子向量。

67. 发明申请

US20110119056A1 SUBWORDS CODING USING DIFFERENT INTERLEAVING SCHEMES 有权
标题翻译：使用不同的交互方案进行子码的编码
公开(公告)号：US20110119056A1
公开(公告)日：2011-05-19
申请号：US12644314
申请日：2009-12-22
申请人： Kiran Gunnam
发明人： Kiran Gunnam
IPC分类号： G10L21/02
CPC分类号： H03M13/2957 , H03M13/1102 , H03M13/116 , H03M13/27 , H03M13/2757 , H03M13/6331 , H03M13/6343 , H04L1/0041 , H04L1/0057 , H04L1/0071
摘要： In a communications system that demultiplexes user data words into multiple sub-words for encoding and decoding within different subword-processing paths, the minimum distance between bit errors in an extrinsic codeword can be increased by having corresponding interleavers/deinterleavers in the different subword-processing paths use different interleaving/deinterleaving algorithms.
摘要翻译：在将用户数据字分解为多个子字以在不同子字处理路径内进行编码和解码的通信系统中，可以通过在不同的子字处理中具有对应的交织器/解交织器来增加外部码字中的位错误之间的最小距离路径使用不同的交织/去交织算法。

68. 发明申请

US20100042906A1 ADJUSTING SOFT-OUTPUT VALUES IN TURBO EQUALIZATION SCHEMES TO BREAK TRAPPING SETS 有权
标题翻译：在涡轮均衡方案中调整软输出值以打破陷阱
公开(公告)号：US20100042906A1
公开(公告)日：2010-02-18
申请号：US12540078
申请日：2009-08-12
申请人： Kiran Gunnam , Shaohua Yang , Changyou Xu
发明人： Kiran Gunnam , Shaohua Yang , Changyou Xu
IPC分类号： H03M13/45 , H03M13/05
CPC分类号： H03M13/1111 , H03M13/09 , H03M13/1142 , H03M13/3707 , H03M13/3738 , H03M13/3753 , H03M13/451
摘要： In one embodiment, a turbo equalizer has an LDPC decoder, a channel detector, and one or more adjustment blocks for recovering an LDPC codeword from a set of input samples. The decoder attempts to recover the codeword from an initial set of channel soft-output values and generates a set of extrinsic soft-output values, each corresponding to a bit of the codeword. If the decoder converges on a trapping set, then the channel detector performs detection on the set of input samples to generate a set of updated channel soft-output values, using the extrinsic soft-output values to improve the detection. The one or more adjustment blocks adjust at least one of (i) the extrinsic soft-output values before the channel detection and (ii) the updated channel soft-output values. Subsequent decoding is then performed on the updated and possibly-adjusted channel soft-output values to attempt to recover the codeword.
摘要翻译：在一个实施例中，turbo均衡器具有LDPC解码器，信道检测器和用于从一组输入采样中恢复LDPC码字的一个或多个调整块。解码器尝试从初始的信道软输出值集合中恢复码字，并产生一组非本征软输出值，每个对应于码字的位。如果解码器收敛于捕获集合，则信道检测器对输入样本集执行检测，以使用外部软输出值来生成一组更新的信道软输出值，以改善检测。一个或多个调整块调整（i）信道检测之前的非本征软输出值和（ii）更新的信道软输出值中的至少一个。然后对更新的和可能调整的信道软输出值执行随后的解码，以尝试恢复码字。

69. 发明申请

US20100042896A1 ERROR-FLOOR MITIGATION OF LAYERED DECODERS USING NON-STANDARD LAYERED-DECODING SCHEDULES 有权
标题翻译：使用非标准层次解码方案的层状解码器的错误地面缓解
公开(公告)号：US20100042896A1
公开(公告)日：2010-02-18
申请号：US12510722
申请日：2009-07-28
申请人： Kiran Gunnam
发明人： Kiran Gunnam
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1111 , H03M13/09 , H03M13/1142 , H03M13/3707 , H03M13/3738 , H03M13/3753 , H03M13/451
摘要： A layered decoder that uses a non-standard schedule, where a non-standard schedule is a schedule where the frequency of one or more layers in the schedule is greater than one. When the layered decoder converges on a near codeword using an initial schedule, the layered decoder identifies the layer Lmaxb of the near codeword, which layer contains the greatest number of unsatisfied check nodes, and selects a subsequent non-standard schedule from a schedule set. The non-standard schedules in the schedule set are sorted by key layer, where the key layer is a layer that appears in the non-standard schedule with the greatest frequency. The layer decoder selects a non-standard schedule from the schedule set where the key layer of selected non-standard schedule is equal to the identified Lmaxb value.
摘要翻译：使用非标准调度的分层解码器，其中非标准调度是调度中的一个或多个层的频率大于1的调度。当分层解码器使用初始调度收敛在近码字时，分层解码器识别近码字的层Lmaxb，该层包含最大数量的不满足的校验节点，并且从调度集中选择后续非标准调度。调度集中的非标准调度按键层进行排序，其中键层是出现在频率最高的非标准调度中的层。层解码器从所选择的非标准调度的密钥层等于所识别的Lmaxb值的调度集中选择非标准调度。

70. 发明授权

US08768990B2 Reconfigurable cyclic shifter arrangement 有权
标题翻译：可重构循环移位器排列
公开(公告)号：US08768990B2
公开(公告)日：2014-07-01
申请号：US13294332
申请日：2011-11-11
申请人： Kiran Gunnam , Madhusudan Kalluri
发明人： Kiran Gunnam , Madhusudan Kalluri
IPC分类号： G06F5/01
CPC分类号： G06F5/017
摘要： In one embodiment, a reconfigurable cyclic shifter arrangement has first and second reconfigurable cyclic shifters connected in series that are each selectively and independently configurable to operate in any one of three different modes at a time. In a first mode, the reconfigurable cyclic shifter is configured as four 4×4 cyclic shifters to cyclically shift four sets of four input values. In a second mode, the reconfigurable cyclic shifter is configured as two 8×8 cyclic shifters to cyclically shift two sets of eight input values. In a third mode, the reconfigurable cyclic shifter is configured as one 16×16 cyclic shifter to cyclically shift one set of 16 input values. Because the first and second reconfigurable cyclic shifters are independently configurable, there are nine different configurations of the reconfigurable cyclic shifter arrangement.
摘要翻译：在一个实施例中，可重构循环移位器装置具有串联连接的第一和第二可重构循环移位器，每个可选择性循环移位器可选择性地和独立地配置为一次以三种不同模式中的任何一种运行。在第一模式中，可重构循环移位器被配置为四个4×4循环移位器循环移位四组四个输入值。在第二模式中，可重构循环移位器被配置为两个8×8循环移位器，以循环移位两组八个输入值。在第三模式中，可重构循环移位器被配置为一个16×16循环移位器，以循环移位一组16个输入值。因为第一和第二可重构循环移位器是可独立配置的，所以可重构循环移位器装置有九种不同的配置。

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