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61. 发明申请

US20090144673A1 PARTIAL GOOD SCHEMA FOR INTEGRATED CIRCUITS HAVING PARALLEL EXECUTION UNITS 失效
标题翻译：具有并行执行单位的集成电路部分良好示意图
公开(公告)号：US20090144673A1
公开(公告)日：2009-06-04
申请号：US12362541
申请日：2009-01-30
申请人： Kenneth J. Goodnow , Michael R. Ouellette , Stephen G. Shuma , Peter A. Twombly
发明人： Kenneth J. Goodnow , Michael R. Ouellette , Stephen G. Shuma , Peter A. Twombly
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Processing engines (PE's) disposed on the substrate. Each processing engine includes a measurement and storage unit, and a PE controller coupled to each of the processing engines. The processing engines perform self-tests and store the results of the self-tests in the measurement and storage unit. The PE controller reads the results and selects a sub-set of processing engines based on the results and an optimization algorithm.
摘要翻译：处理引擎（PE）设置在基板上。每个处理引擎包括测量和存储单元以及耦合到每个处理引擎的PE控制器。处理引擎执行自检并将测试结果存储在测量和存储单元中。 PE控制器根据结果和优化算法读取结果并选择一组处理引擎。

62. 发明申请

US20090115447A1 Design Structure for an Integrated Circuit Having State-Saving Input-Output Circuitry and a Method of Testing Such an Integrated Circuit 审中-公开
标题翻译：具有省电输入输出电路的集成电路的设计结构和测试这种集成电路的方法
公开(公告)号：US20090115447A1
公开(公告)日：2009-05-07
申请号：US11933646
申请日：2007-11-01
申请人： Theodoros E. Anemikos , Michael R. Ouellette , Anthony D. Polson
发明人： Theodoros E. Anemikos , Michael R. Ouellette , Anthony D. Polson
IPC分类号： H03K19/003
CPC分类号： G06F17/505 , G01R31/3016 , G01R33/072 , G06F2217/14
摘要： A design structure for an integrated circuit that includes input/output (I/O) state saving circuitry capable of stabilizing the I/O states during any predicted I/O disturbance event. The I/O state saving circuitry includes a plurality of transparent latches arranged between the output of a plurality of respective I/O receivers and the internal digital, analog, or mixed-signal circuitry of the integrated circuit. The transparent latches are transitioned between a pass-through mode and a state-saving mode via a common control signal. In anticipation of, for example, a predicted I/O signal disturbance generating event, the transparent latches are set to the state-saving mode. Consequently, the outputs of the transparent latches are held stable and glitchless during the disturbance event, which ensures that the internal logic of the integrated circuit does not lose state.
摘要翻译：一种用于集成电路的设计结构，其包括能够在任何预测的I / O干扰事件期间稳定I / O状态的输入/输出（I / O）状态保存电路。 I / O状态保存电路包括布置在多个相应I / O接收器的输出端与集成电路的内部数字，模拟或混合信号电路之间的多个透明锁存器。透明锁存器通过公共控制信号在通过模式和状态保存模式之间转换。在预期的例如预测的I / O信号干扰发生事件中，透明锁存器被设置为状态保存模式。因此，在干扰事件期间，透明锁存器的输出保持稳定和无毛刺，这确保了集成电路的内部逻辑不会失去状态。

63. 发明申请

US20080256405A1 COMPILABLE MEMORY STRUCTURE AND TEST METHODOLOGY FOR BOTH ASIC AND FOUNDRY TEST ENVIRONMENTS 审中-公开
标题翻译：可编程存储器结构和测试方法用于两个ASIC和基准测试环境
公开(公告)号：US20080256405A1
公开(公告)日：2008-10-16
申请号：US12143007
申请日：2008-06-20
申请人： Steven M. Eustis , James A. Monzel , Steven F. Oakland , Michael R. Ouellette
发明人： Steven M. Eustis , James A. Monzel , Steven F. Oakland , Michael R. Ouellette
IPC分类号： G01R31/3185 , G06F11/25 , G01R31/3187
CPC分类号： G11C29/48 , G11C29/1201 , G11C2029/3202
摘要： A method of implementing a compilable memory structure configured for supporting multiple test methodologies includes configuring a first plurality of multiplexers for selectively coupling at least one data input path and at least one address path between an external customer connection and a corresponding internal memory connection associated therewith. A second multiplexer is configured for selectively coupling an input of a test latch between a functional memory array connection and a memory logic connection, the memory logic connection coupled to the at least one data input path, with an output of the test latch defining a data out customer connection. Flush logic is configured to direct data from the memory logic connection to the data out customer connection during a test of logic associated with a customer chip, facilitating observation of the memory logic connection at the customer chip.
摘要翻译：实现被配置为支持多个测试方法的可编译存储器结构的方法包括配置第一多个多路复用器，用于选择性地耦合至少一个数据输入路径和外部客户连接与与其相关联的对应内部存储器连接之间的至少一个地址路径。第二多路复用器被配置为选择性地耦合功能存储器阵列连接和存储器逻辑连接之间的测试锁存器的输入，存储器逻辑连接耦合到至少一个数据输入路径，测试锁存器的输出定义数据客户连接。冲洗逻辑被配置为在与客户芯片相关联的逻辑的测试期间将数据从存储器逻辑连接引导到数据输出客户连接，以便于观察客户芯片上的存储器逻辑连接。

64. 发明申请

US20080101145A1 Method Of Providing Optimal Field Programming Of Electronic Fuses 失效
标题翻译：提供电子保险丝最优现场编程的方法
公开(公告)号：US20080101145A1
公开(公告)日：2008-05-01
申请号：US11555323
申请日：2006-11-01
申请人： Troy J. Perry , Michael R. Ouellette
发明人： Troy J. Perry , Michael R. Ouellette
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G11C17/165 , G11C29/02 , G11C29/021 , G11C29/027 , G11C29/028 , G11C2029/5006
摘要： A method of providing optimal fuse programming conditions by which an integrated circuit chip customer may program electronic fuses in the field, i.e., outside of the manufacturing test environment. An optimal fuse programming identifier, which is correlated to optimal fuse programming conditions, may be provided to the customer in readable fashion on the customer's IC chip. Accessing the optimal fuse programming identifier on the customer's IC chip, the customer may apply a fuse programming process in the field according to one or more correlated optimal fuse programming conditions.
摘要翻译：一种提供最佳熔丝编程条件的方法，集成电路芯片客户可以通过该条件来编程现场的电子熔丝，即在制造测试环境之外。可以以客户的IC芯片的可读方式向客户提供与最佳熔丝编程条件相关的最佳熔丝编程标识符。访问客户IC芯片上的最佳熔丝编程标识符，客户可以根据一个或多个相关的最佳熔丝编程条件在现场应用熔丝编程过程。

65. 发明申请

US20080002451A1 SYSTEM AND METHOD FOR DIFFERENTIAL EFUSE SENSING WITHOUT REFERENCE FUSES 有权
标题翻译：没有参考熔丝的差分EFUSE感应系统和方法
公开(公告)号：US20080002451A1
公开(公告)日：2008-01-03
申请号：US11427849
申请日：2006-06-30
申请人： Darren L. Anand , John A. Fifield , Michael R. Ouellette
发明人： Darren L. Anand , John A. Fifield , Michael R. Ouellette
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18
摘要： A differential fuse sensing system includes a fuse leg configured for introducing a sense current through an electrically programmable fuse (eFUSE) to be sensed, and a differential sense amplifier having a first input node coupled to the fuse leg and a second node coupled to a reference voltage. The fuse leg further includes a current supply device controlled by a variable reference current generator configured to generate an output signal therefrom such that the voltage on the first input node of the sense amplifier is equal to the voltage on the second input node of the sense amplifier whenever the resistance value of the eFUSE is equal to the resistance value of a programmable variable resistance device included within the variable reference current generator.
摘要翻译：差分保险丝感测系统包括被配置用于通过要被感测的电可编程熔丝（eFUSE）引入感测电流的熔丝腿，以及具有耦合到熔丝支脚的第一输入节点和耦合到参考的第二节点的差分读出放大器电压。保险丝腿还包括由可变参考电流发生器控制的电流供应装置，其被配置为从其产生输出信号，使得读出放大器的第一输入节点上的电压等于读出放大器的第二输入节点上的电压每当eFUSE的电阻值等于包括在可变参考电流发生器内的可编程可变电阻器件的电阻值时。

66. 发明授权

US07304901B2 Enabling memory redundancy during testing 有权
标题翻译：在测试期间启用内存冗余
公开(公告)号：US07304901B2
公开(公告)日：2007-12-04
申请号：US11160268
申请日：2005-06-16
申请人： Michael R. Ouellette , Jeremy Rowland
发明人： Michael R. Ouellette , Jeremy Rowland
IPC分类号： G11C29/00
CPC分类号： G11C29/4401 , G11C29/14 , G11C29/24 , G11C29/44
摘要： Methods and apparatuses for enabling a redundant memory element (20) during testing of a memory array (14). The memory array (14) includes general memory elements (18) and redundant memory elements (20). The general memory elements (18) are tested and any defective general memory elements (18) are replaced with redundant memory elements (20). The redundant memory elements (20) are tested only when they are enabled.
摘要翻译：用于在存储器阵列（14）的测试期间启用冗余存储元件（20）的方法和装置。存储器阵列（14）包括通用存储元件（18）和冗余存储元件（20）。一般存储器元件（18）被测试，并且任何有缺陷的通用存储器元件（18）被替换为冗余存储元件（20）。冗余存储器元件（20）仅在使能时被测试。

67. 发明授权

US06961276B2 Random access memory having an adaptable latency 失效
公开(公告)号：US06961276B2
公开(公告)日：2005-11-01
申请号：US10664789
申请日：2003-09-17
申请人： Francois Ibrahim Atallah , James Norris Dieffenderfer , Jeffrey H. Fischer , Michael Thomas Fragano , Daniel Stephen Geise , Jeffery Howard Oppold , Michael R. Ouellette , Neelesh Govindaraya Pai , William Robert Reohr , Joel Abraham Silberman , Thomas Philip Speier
发明人： Francois Ibrahim Atallah , James Norris Dieffenderfer , Jeffrey H. Fischer , Michael Thomas Fragano , Daniel Stephen Geise , Jeffery Howard Oppold , Michael R. Ouellette , Neelesh Govindaraya Pai , William Robert Reohr , Joel Abraham Silberman , Thomas Philip Speier
IPC分类号： G11C7/02 , G11C7/06 , G11C7/10 , G11C7/22 , G11C11/22
CPC分类号： G11C7/22 , G11C7/06 , G11C7/1045
摘要： A random access memory circuit comprises a plurality of memory cells and at least one decoder coupled to the memory cells, the decoder being configurable for receiving an input address and for accessing one or more of the memory cells in response thereto. The random access memory circuit further comprises a plurality of sense amplifiers operatively coupled to the memory cells, the sense amplifiers being configurable for determining a logical state of one or more of the memory cells. A controller coupled to at least a portion of the sense amplifiers is configurable for selectively operating in at least one of a first mode and a second mode. In the first mode of operation, the controller enables one of the sense amplifiers corresponding to the input address and disables the sense amplifiers not corresponding to the input address. In the second mode of operation, the controller enables substantially all of the sense amplifiers. The memory circuit advantageously provides an adaptable latency by controlling the mode of operation of the circuit.

68. 发明授权

US06928377B2 Self-test architecture to implement data column redundancy in a RAM 有权
公开(公告)号：US06928377B2
公开(公告)日：2005-08-09
申请号：US10658940
申请日：2003-09-09
申请人： Steven M. Eustis , Krishnendu Mondal , Michael R. Ouellette , Jeremy P. Rowland
发明人： Steven M. Eustis , Krishnendu Mondal , Michael R. Ouellette , Jeremy P. Rowland
IPC分类号： G01R31/28 , G01R31/00 , G06F19/00 , G11C29/00 , G11C29/12 , G11C29/44
CPC分类号： G11C29/846 , G11C29/44 , G11C29/4401 , G11C29/72 , G11C2029/1208
摘要： Self-test architectures are provided to implement data column and row redundancy with a totally integrated self-test and repair capability in a Random Access Memory (RAM), either a Dynamic RAM (DRAM) or a Static Ram (SRAM), and are particularly applicable to compileable memories and to embedded RAM within microprocessor or logic chips. The invention uses two passes of self-test of a memory. The first pass of self-test determines the worst failing column, the column with the largest number of unique failing row addresses. After completion of the first pass of self-test, the spare column is allocated to replace the worst failing column. In the second pass of self-test, the BIST (Built In Self-Test) collects unique failing row addresses as it does today for memories with spare rows only. At the completion of the second pass of self-test, the spare rows are then allocated. Once the second pass of self-test is completed, the column and unique failing row addresses are transported to the e-fuse macros and permanently stored in the chip.

69. 发明授权

US06552920B2 Saving content addressable memory power through conditional comparisons 有权
标题翻译：通过条件比较保存内容可寻址的内存电源
公开(公告)号：US06552920B2
公开(公告)日：2003-04-22
申请号：US09892396
申请日：2001-06-27
申请人： Thomas B. Chadwick , Tarl S. Gordon , Eric Jasinski , Rahul Nadkarni , Michael R. Ouellette
发明人： Thomas B. Chadwick , Tarl S. Gordon , Eric Jasinski , Rahul Nadkarni , Michael R. Ouellette
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： A method and structure for improving a content addressable memory array has a plurality of serially connected memory sub-arrays (which include at least one memory cell), a matchline connected to each of the sub-arrays, a valid memory cell, a comparator receiving input from the matchline and valid memory cell, a sinkline output from the comparator, and a precharge device. The sinkline and matchline are reset from a first voltage to a second voltage depending upon the results of a compare operation of the input data to the data in the storage device. When the second voltage appears on the matchline and the first voltage appears on the sinkline this indicates a match between the data within all of the sub-arrays and the input data.
摘要翻译：用于改善内容可寻址存储器阵列的方法和结构具有多个串联的存储器子阵列（其包括至少一个存储器单元），连接到每个子阵列的匹配线，有效存储器单元，比较器接收来自匹配线和有效存储器单元的输入，来自比较器的漏线输出和预充电器件。取决于输入数据与存储装置中的数据的比较操作的结果，汇流线和匹配线从第一电压复位到第二电压。当匹配线上出现第二个电压，并且第一个电压出现在漏极线上时，这表示所有子阵列中的数据和输入数据之间的匹配。

70. 发明授权

US6002633A Performance optimizing compiler for building a compiled SRAM 失效
标题翻译：用于构建编译的SRAM的性能优化编译器
公开(公告)号：US6002633A
公开(公告)日：1999-12-14
申请号：US225075
申请日：1999-01-04
申请人： Jeffery H. Oppold , Michael R. Ouellette , Michael J. Sullivan
发明人： Jeffery H. Oppold , Michael R. Ouellette , Michael J. Sullivan
IPC分类号： G11C8/12 , G11C8/00 , G11C11/00
CPC分类号： G11C8/12
摘要： A compiler for building at least one compilable SRAM including at least one compilable sub-block. A global control clock generation circuit generates a global control signal. At least one local control logic and speed control circuit controls the at least one compilable sub-block. The local control logic and speed control circuit is controlled by the global control signal. An algorithm receives an input capacity and configuration for the sub-block of the SRAM array. An algorithm determines a number of wordlines and bitlines required to create the sub-block of the input capacity. An algorithm optimizes a cycle time of the sub-block by determining global control clock circuits based upon the number of wordlines and bitlines in the sub-block. An algorithm optimizes access time of the sub-block by determining local speed control circuits based upon the number of wordlines and bitlines.
摘要翻译：一种用于构建至少一个可编译SRAM（包括至少一个可编译子块）的编译器。全局控制时钟产生电路产生全局控制信号。至少一个本地控制逻辑和速度控制电路控制该至少一个可编译子块。本地控制逻辑和速度控制电路由全局控制信号控制。算法接收SRAM阵列的子块的输入容量和配置。算法确定创建输入容量的子块所需的字数和位线数。算法通过基于子块中的字线和位线的数量确定全局控制时钟电路来优化子块的周期时间。算法通过基于字线和位线的数量确定本地速度控制电路来优化子块的访问时间。

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