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61. 发明授权

US5923862A Processor that decodes a multi-cycle instruction into single-cycle micro-instructions and schedules execution of the micro-instructions 失效
标题翻译：将多周期指令解码为单周期微指令并计划执行微指令的处理器
公开(公告)号：US5923862A
公开(公告)日：1999-07-13
申请号：US789574
申请日：1997-01-28
申请人： Le Trong Nguyen , Heonchul Park
发明人： Le Trong Nguyen , Heonchul Park
IPC分类号： G06F9/22 , G06F9/28 , G06F9/30 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3017 , G06F9/28 , G06F9/30145 , G06F9/30167 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： An instruction decoder in a processor decodes an instruction by creating a decode buffer entry that includes global fields, operand fields, and a set of micro-instructions. Each micro-instruction represent an operation that an associated execution unit can execute in a single clock cycle. A scheduler issues the micro-instructions from one or more entries to the execution units for possible parallel and out-of-order execution. Each execution unit completes an operation, typically, in one clock cycle and does not monitor instructions that may block a pipeline. The execution units do not need separate decoding for multiple stages. One global field indicates which micro-instructions are execute first. Further, micro-instructions have fields that indicate an execution sequence. The scheduler issues operations in the order indicated by the global fields and the micro-instructions. When the last operation for an instruction is completed, the instruction is retired and removed from the decode buffer.
摘要翻译：处理器中的指令解码器通过创建包括全局字段，操作数字段和一组微指令的解码缓冲器条目来解码指令。每个微指令表示相关执行单元可以在单个时钟周期内执行的操作。调度器将微指令从一个或多个条目发送到执行单元，以实现可能的并行和无序执行。每个执行单元通常在一个时钟周期内完成一个操作，并且不监视可能阻塞流水线的指令。执行单元不需要对多个阶段进行单独的解码。一个全局字段指示哪个微指令首先执行。此外，微指令具有指示执行顺序的字段。调度器按照全局字段和微指令指示的顺序发布操作。当指令的最后一个操作完成时，指令被退出并从解码缓冲器中移除。

62. 发明授权

US5889986A Instruction fetch unit including instruction buffer and secondary or branch target buffer that transfers prefetched instructions to the instruction buffer 失效
标题翻译：指令提取单元包括指令缓冲器和将预取指令传送到指令缓冲器的辅助或分支目标缓冲器
公开(公告)号：US5889986A
公开(公告)日：1999-03-30
申请号：US790028
申请日：1997-01-28
申请人： Le Trong Nguyen , Heonchul Park
发明人： Le Trong Nguyen , Heonchul Park
IPC分类号： G06F9/38 , G06F9/06
CPC分类号： G06F9/3806 , G06F9/3804
摘要： An instruction fetch unit includes a program buffer for sequential instructions being decoded and a target buffer for an instruction sequence including the target of the next branch instruction. Scan logic coupled to the program buffer scans the program buffer for branch instructions. A target for the first branch instruction is determined and a request to external memory fills the target buffer with a sequence of instructions including a target instruction before sequential decoding reaches the branch instruction. If the branch is subsequently taken, the instructions from the branch target buffer are transferred to the program buffer. The program buffer may be divided into a main and a secondary buffer that have the same size as the target buffer, and an instruction bus between the instruction fetch unit and external memory is sufficiently wide to fill the main, secondary, or target buffer in a single write operation.
摘要翻译：指令提取单元包括用于正在解码的顺序指令的程序缓冲器和用于包括下一个分支指令的目标的指令序列的目标缓冲器。耦合到程序缓冲区的扫描逻辑扫描程序缓冲区以获得分支指令。确定第一分支指令的目标，并且对外部存储器的请求在序列解码到达分支指令之前用包括目标指令的指令序列填充目标缓冲器。如果随后采取分支，则来自分支目标缓冲器的指令被传送到程序缓冲器。程序缓冲器可以被划分为与目标缓冲器具有相同大小的主缓冲器和辅助缓冲器，并且指令提取单元和外部存储器之间的指令总线足够宽以填充主缓冲器，辅助缓冲器或目标缓冲器单写操作。

63. 发明授权

US5438668A System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer 失效
标题翻译：将CISC指令提取，对齐和解码为纳入指令桶以供RISC计算机执行的系统和方法
公开(公告)号：US5438668A
公开(公告)日：1995-08-01
申请号：US857599
申请日：1992-03-31
申请人： Brett Coon , Yoshiyuki Miyayama , Le Trong Nguyen , Johannes Wang
发明人： Brett Coon , Yoshiyuki Miyayama , Le Trong Nguyen , Johannes Wang
IPC分类号： C10G1/00 , C10G17/02 , G06F9/22 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/76 , G06F9/312 , G06F9/315
CPC分类号： G06F9/30101 , C10G1/00 , C10G17/02 , G06F9/30145 , G06F9/30149 , G06F9/30152 , G06F9/30163 , G06F9/30167 , G06F9/3017 , G06F9/30174 , G06F9/30185 , G06F9/3816 , G06F9/382 , G06F9/3853
摘要： A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.
摘要翻译：一种用于从复杂指令流中提取复杂的可变长度计算机指令的系统和方法，每个细分流被分成可变数量的指令字节，并且对齐复杂指令中各个指令的指令字节。系统接收复指令流的一部分，并使用提取移位器从第一指令字节开始提取第一组指令字节。然后将该组指令字节传递到对齐锁存器，在该锁存器中它们对准并输出到下一个指令检测器。下一个指令检测器基于所述指令字节集来确定第一指令的结束。提取移位器用于提取并提供下一组指令字节到对齐移位器，对准移位器对齐并输出下一条指令。然后对复杂指令流中的剩余指令字节重复该过程。孤立的复杂指令被解码成由RISC处理器核心处理的纳米指令。

64. 发明授权

US07941635B2 High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distribution 失效
标题翻译：高性能超标量计算机系统，具有无序指令执行和并发结果分配
公开(公告)号：US07941635B2
公开(公告)日：2011-05-10
申请号：US11640967
申请日：2006-12-19
申请人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
发明人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
IPC分类号： G06F9/38
CPC分类号： G06F9/30167 , G06F9/30054 , G06F9/30101 , G06F9/30105 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30141 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3824 , G06F9/3828 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3857 , G06F9/3861 , G06F9/3865 , G06F9/3885
摘要： The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of instructions in an instruction buffer. The execution unit includes an instruction selection unit, coupled to the instruction buffer, for selecting instructions for execution, and a plurality of functional units for performing instruction specified functional operations. A unified instruction scheduler, within the instruction selection unit, initiates the processing of instructions through the functional units when instructions are determined to be available for execution and for which at least one of the functional units implementing a necessary computational function is available. Unified scheduling is performed across multiple execution data paths, where each execution data path, and corresponding functional units, is generally optimized for the type of computational function that is to be performed on the data: integer, floating point, and boolean. The number, type and computational specifics of the functional units provided in each data path, and as between data paths, are mutually independent.
摘要翻译：高性能的基于RISC核心的微处理器架构包括用于从指令存储器取出指令集的指令获取单元和通过并行的功能单元阵列实现多个指令的并发执行的执行单元。提取单元通常在指令缓冲器中保持预定数量的指令。执行单元包括指令选择单元，耦合到指令缓冲器，用于选择用于执行的指令;以及多个功能单元，用于执行指令指定的功能操作。在指令选择单元内的统一指令调度器，当确定可用于执行的指令并且实现必要的计算功能的功能单元中的至少一个可用时，通过功能单元启动对指令的处理。在多个执行数据路径上执行统一调度，其中每个执行数据路径和相应的功能单元通常针对要在数据上执行的计算函数类型进行优化：整数，浮点和布尔值。在每个数据路径中以及数据路径之间提供的功能单元的数量，类型和计算细节是相互独立的。

65. 发明授权

US07664935B2 System and method for translating non-native instructions to native instructions for processing on a host processor 失效
标题翻译：用于将非本机指令转换为本地指令以在主机处理器上进行处理的系统和方法
公开(公告)号：US07664935B2
公开(公告)日：2010-02-16
申请号：US12046318
申请日：2008-03-11
申请人： Brett Coon , Yoshiyuki Miyayama , Le Trong Nguyen , Johannes Wang
发明人： Brett Coon , Yoshiyuki Miyayama , Le Trong Nguyen , Johannes Wang
IPC分类号： G06F9/30
CPC分类号： G06F9/30101 , G06F9/30145 , G06F9/30149 , G06F9/30152 , G06F9/30163 , G06F9/30167 , G06F9/3017 , G06F9/30174 , G06F9/30185 , G06F9/3816 , G06F9/382 , G06F9/3853
摘要： A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.
摘要翻译：一种用于从复杂指令流中提取复杂的可变长度计算机指令的系统和方法，每个细分流被分成可变数量的指令字节，并且对齐复杂指令中各个指令的指令字节。系统接收复指令流的一部分，并使用提取移位器从第一指令字节开始提取第一组指令字节。然后将该组指令字节传递到对齐锁存器，在该锁存器中它们对准并输出到下一个指令检测器。下一个指令检测器基于所述指令字节集来确定第一指令的结束。提取移位器用于提取并提供下一组指令字节到对齐移位器，对准移位器对齐并输出下一条指令。然后对复杂指令流中的剩余指令字节重复该过程。孤立的复杂指令被解码成由RISC处理器核心处理的纳米指令。

66. 发明授权

US07555632B2 High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution 失效
标题翻译：高性能超标量计算机系统，具有无序指令执行和并发结果分配
公开(公告)号：US07555632B2
公开(公告)日：2009-06-30
申请号：US11316814
申请日：2005-12-27
申请人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
发明人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
IPC分类号： G06F9/38
CPC分类号： G06F9/30167 , G06F9/30054 , G06F9/30101 , G06F9/30105 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30141 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3824 , G06F9/3828 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3857 , G06F9/3861 , G06F9/3865 , G06F9/3885
摘要： The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of instructions in an instruction buffer. The execution unit includes an instruction selection unit, coupled to the instruction buffer, for selecting instructions for execution, and a plurality of functional units for performing instruction specified functional operations. A unified instruction scheduler, within the instruction selection unit, initiates the processing of instructions through the functional units when instructions are determined to be available for execution and for which at least one of the functional units implementing a necessary computational function is available. Unified scheduling is performed across multiple execution data paths, where each execution data path, and corresponding functional units, is generally optimized for the type of computational function that is to be performed on the data: integer, floating point, and boolean. The number, type and computational specifics of the functional units provided in each data path, and as between data paths, are mutually independent.
摘要翻译：高性能的基于RISC核心的微处理器架构包括用于从指令存储器取出指令集的指令获取单元和通过并行的功能单元阵列实现多个指令的并发执行的执行单元。提取单元通常在指令缓冲器中保持预定数量的指令。执行单元包括指令选择单元，耦合到指令缓冲器，用于选择用于执行的指令;以及多个功能单元，用于执行指令指定的功能操作。在指令选择单元内的统一指令调度器，当确定可用于执行的指令并且实现必要的计算功能的功能单元中的至少一个可用时，通过功能单元启动对指令的处理。在多个执行数据路径上执行统一调度，其中每个执行数据路径和相应的功能单元通常针对要在数据上执行的计算函数类型进行优化：整数，浮点和布尔值。在每个数据路径中以及数据路径之间提供的功能单元的数量，类型和计算细节是相互独立的。

67. 发明授权

US07343473B2 System and method for translating non-native instructions to native instructions for processing on a host processor 失效
标题翻译：用于将非本机指令转换为本地指令以在主机处理器上进行处理的系统和方法
公开(公告)号：US07343473B2
公开(公告)日：2008-03-11
申请号：US11167289
申请日：2005-06-28
申请人： Brett Coon , Yoshiyuki Miyayama , Le Trong Nguyen , Johannes Wang
发明人： Brett Coon , Yoshiyuki Miyayama , Le Trong Nguyen , Johannes Wang
IPC分类号： G06F9/30
CPC分类号： G06F9/30101 , G06F9/30145 , G06F9/30149 , G06F9/30152 , G06F9/30163 , G06F9/30167 , G06F9/3017 , G06F9/30174 , G06F9/30185 , G06F9/3816 , G06F9/382 , G06F9/3853
摘要： A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.
摘要翻译：一种用于从复杂指令流中提取复杂的可变长度计算机指令的系统和方法，每个细分流被分成可变数量的指令字节，并且对齐复杂指令中各个指令的指令字节。系统接收复指令流的一部分，并使用提取移位器从第一指令字节开始提取第一组指令字节。然后将该组指令字节传递到对齐锁存器，在该锁存器中它们对准并输出到下一个指令检测器。下一个指令检测器基于所述指令字节集来确定第一指令的结束。提取移位器用于提取并提供下一组指令字节到对齐移位器，对准移位器对齐并输出下一条指令。然后对复杂指令流中的剩余指令字节重复该过程。孤立的复杂指令被解码成由RISC处理器核心处理的纳米指令。

68. 发明授权

US07028161B2 High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution 失效
公开(公告)号：US07028161B2
公开(公告)日：2006-04-11
申请号：US09850416
申请日：2001-05-08
申请人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
发明人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
IPC分类号： G06F15/00
CPC分类号： G06F9/30167 , G06F9/30054 , G06F9/30101 , G06F9/30105 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30141 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3824 , G06F9/3828 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3857 , G06F9/3861 , G06F9/3865 , G06F9/3885
摘要： The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of instructions in an instruction buffer. The execution unit includes an instruction selection unit, coupled to the instruction buffer, for selecting instructions for execution, and a plurality of functional units for performing instruction specified functional operations. A unified instruction scheduler, within the instruction selection unit, initiates the processing of instructions through the functional units when instructions are determined to be available for execution and for which at least one of the functional units implementing a necessary computational function is available. Unified scheduling is performed across multiple execution data paths, where each execution data path, and corresponding functional units, is generally optimized for the type of computational function that is to be performed on the data: integer, floating point, and boolean. The number, type and computational specifics of the functional units provided in each data path, and as between data paths, are mutually independent.

69. 发明授权

US06782521B2 Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip 失效
标题翻译：用于集成电路芯片的指令执行单元的集成结构布局和互连布局
公开(公告)号：US06782521B2
公开(公告)日：2004-08-24
申请号：US10139318
申请日：2002-05-07
申请人： Kevin R. Iadonato , Le Trong Nguyen
发明人： Kevin R. Iadonato , Le Trong Nguyen
IPC分类号： G06F1750
CPC分类号： G06F9/30141 , G06F9/3824 , G06F9/3826 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F17/5068
摘要： An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.
摘要翻译：用于集成电路芯片的功能块和互连的集成结构布局。数据依赖比较器块以行和列排列。这种布置定义行中相邻的数据依赖性比较器块之间的布局区域。标签分配逻辑块被耦合到数据依赖性比较器块以接收依赖性信息。标签分配逻辑块位于一个或多个布局区域中，以便与数据依赖性比较器块集成以节省半导体芯片上的区域，并在空间上定义在一个或多个行中并基本正交的通道。寄存器文件端口多路复用器块耦合到与正交信道相邻的标签分配逻辑块的输出线，以接收标签信息，并将标签信息传递到寄存器文件的地址端口。

70. 发明授权

US06401232B1 Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip 失效
公开(公告)号：US06401232B1
公开(公告)日：2002-06-04
申请号：US09604419
申请日：2000-06-27
申请人： Kevin R. Iadonato , Le Trong Nguyen
发明人： Kevin R. Iadonato , Le Trong Nguyen
IPC分类号： G06F1750
CPC分类号： G06F9/30141 , G06F9/3824 , G06F9/3826 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F17/5068
摘要： An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.

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