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61. 发明授权

US06647485B2 High-performance, superscalar-based computer system with out-of-order instruction execution 失效
公开(公告)号：US06647485B2
公开(公告)日：2003-11-11
申请号：US09852293
申请日：2001-05-10
申请人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
发明人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
IPC分类号： G06F930
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

62. 发明授权

US06360309B1 System and method for assigning tags to control instruction processing in a superscalar processor 失效
公开(公告)号：US06360309B1
公开(公告)日：2002-03-19
申请号：US09574251
申请日：2000-05-19
申请人： Kevin R. Iadonato , Trevor A. Deosaran , Sanjiv Garg
发明人： Kevin R. Iadonato , Trevor A. Deosaran , Sanjiv Garg
IPC分类号： G06F1500
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3885
摘要： A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each instruction. A queue having a plurality of slots containing tags which are used for tagging the instructions. The tags are arranged in the queue in an order specified by the program order of their corresponding instructions. A control unit monitors the completion of executed instructions and advances the tags in the queue upon completion of an executed instruction. The register file stores an instruction's information at a location in the register file defined by the tag assigned to that instruction. The register file also contains a plurality of read address enable ports and corresponding read output ports. Each of the slots from the queue is coupled to a corresponding one of the read address enable ports. Thus, the information for each instruction can be read out of the register file in program order.

63. 发明授权

US06272617B1 System and method for register renaming 失效
标题翻译：用于注册重命名的系统和方法
公开(公告)号：US06272617B1
公开(公告)日：2001-08-07
申请号：US09399000
申请日：1999-09-17
申请人： Trevor A. Deosaran , Sanjiv Garg , Kevin R. Iadonato
发明人： Trevor A. Deosaran , Sanjiv Garg , Kevin R. Iadonato
IPC分类号： G06F1500
CPC分类号： G06F9/3838 , G06F9/384 , G06F9/3857
摘要： A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a location becomes available. A tag is assigned to each instruction in the variable advance instruction window. The tag of each instruction to leave the window is assigned to the next new instruction to be added to it. The results of instructions executed by the processor are stored in a temp buffer according to their corresponding tags to avoid output and anti-dependencies. The temp buffer therefore permits the processor to execute instructions out of order and in parallel. Data dependency checks for input dependencies are performed only for each new instruction added to the variable advance instruction window and register renaming is performed to avoid input dependencies.
摘要翻译：一种用于在具有用于存储要由处理器执行的指令组的可变提前指令窗口的处理器中执行寄存器重命名源寄存器的系统和方法，其中当位置变得可用时将新指令添加到可变提前指令窗口。标签被分配给变量提前指令窗口中的每个指令。离开窗口的每个指令的标签被分配给要添加到其中的下一个新指令。由处理器执行的指令的结果根据其相应的标签存储在临时缓冲器中，以避免输出和反依赖。因此，临时缓冲器允许处理器按顺序并行执行指令。仅对添加到变量提前指令窗口的每个新指令执行输入相关性的数据依赖性检查，并执行寄存器重命名以避免输入依赖关系。

64. 发明授权

US06131157A System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor 失效
公开(公告)号：US06131157A
公开(公告)日：2000-10-10
申请号：US9412
申请日：1998-01-20
申请人： Johannes Wang , Sanjiv Garg , Trevor Dcosaran
发明人： Johannes Wang , Sanjiv Garg , Trevor Dcosaran
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3012 , G06F9/3013 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3885
摘要： An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results. In addition, the retirement control block further controls the retiring of a group of instructions determined to be retirable, by simultaneously transferring their results from the temporary buffer to the register array, and retires instructions executed in order by storing their results directly in the register array. The method comprises the steps of monitoring the status of the instructions to determine which group of instructions have been executed, determining whether each executed instruction is retirable, storing results of instructions executed out of program order in a temporary buffer, storing retirable-instruction results in a register array and retiring a group of retirable instructions by simultaneously transferring their results from the temporary buffer to the register array, and retiring instructions executed in order by storing their results directly in the register array.

65. 发明授权

US5838986A RISC microprocessor architecture implementing multiple typed register sets 失效
公开(公告)号：US5838986A
公开(公告)日：1998-11-17
申请号：US937361
申请日：1997-09-25
申请人： Sanjiv Garg , Derek J. Lentz , Le Trong Nguyen , Sho Long Chen
发明人： Sanjiv Garg , Derek J. Lentz , Le Trong Nguyen , Sho Long Chen
IPC分类号： G06F9/30 , G06F9/305 , G06F9/318 , G06F9/34 , G06F9/38 , G06F9/42 , G06F9/46 , G06F9/48
CPC分类号： G06F9/30029 , G06F9/30036 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30138 , G06F9/30167 , G06F9/30181 , G06F9/3851
摘要： A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA�23:0!) and second (RA�31:24!) subsets, and a shadow subset (RT�31:24!). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively. Boolean comparison instructions specify particular integer or floating point registers for source data to be compared, and specify a particular Boolean register for the result, so there are no dedicated, fixed-location status flags. Boolean combinational instructions combine specified Boolean registers, for performing complex Boolean comparisons without intervening conditional branch instructions, to minimize pipeline disruption.

66. 发明授权

US5809276A System and method for register renaming 失效
公开(公告)号：US5809276A
公开(公告)日：1998-09-15
申请号：US698211
申请日：1996-08-15
申请人： Trevor A. Deosaran , Sanjiv Garg , Kevin R. Iadonato
发明人： Trevor A. Deosaran , Sanjiv Garg , Kevin R. Iadonato
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3838 , G06F9/384 , G06F9/3857
摘要： A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a location becomes available. A tag is assigned to each instruction in the variable advance instruction window. The tag of each instruction to leave the window is assigned to the next new instruction to be added to it. The results of instructions executed by the processor are stored in a temp buffer according to their corresponding tags to avoid output and anti-dependencies. The temp buffer therefore permits the processor to execute instructions out of order and in parallel. Data dependency checks for input dependencies are performed only for each new instruction added to the variable advance instruction window and register renaming is performed to avoid input dependencies.

67. 发明授权

US5689720A High-performance superscalar-based computer system with out-of-order instruction execution 失效
标题翻译：基于高性能超标量计算机系统，执行无序指令
公开(公告)号：US5689720A
公开(公告)日：1997-11-18
申请号：US602021
申请日：1996-02-15
申请人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
发明人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
IPC分类号： G06F9/32 , G06F9/30 , G06F9/34 , G06F9/38 , G06F9/42 , G06F9/22
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches and stores program instruction sets. Each instruction set includes a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instruction sets and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers which are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.
摘要翻译：高性能，基于超标量的计算机系统，具有无序指令执行功能，可提高资源利用率和性能吞吐量。计算机系统获取和存储程序指令集。每个指令集包括具有指定的顺序程序顺序（按顺序）的多个固定长度指令。计算机系统包括指令执行单元，其包括寄存器文件，多个功能单元以及指令控制单元，用于检查指令集并且调度用于由功能单元执行无序执行的指令。寄存器文件包括一组临时数据寄存器，由指令执行控制单元用来接收由功能单元产生的数据结果。每个执行指令的数据结果被存储在临时数据寄存器中，直到所有先前的指令都被执行，从而按顺序退出执行的指令。

68. 发明授权

US5604912A System and method for assigning tags to instructions to control instruction execution 失效
标题翻译：将标签分配给用于控制指令执行的指令的系统和方法
公开(公告)号：US5604912A
公开(公告)日：1997-02-18
申请号：US999648
申请日：1992-12-31
申请人： Kevin R. Iadonato , Trevor A. Deosaran , Sanjiv Garg
发明人： Kevin R. Iadonato , Trevor A. Deosaran , Sanjiv Garg
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/3857 , G06F9/3885
摘要： Tag monitoring system for assigning tags to instructions. A memory unit stores instructions to be executed by an execution unit. Before execution an instruction fetch unit decodes the instructions. A register file stores the decoded instructions. A queue having a plurality of slots containing tags which are used for tagging the decoded instructions. A control unit assigns the tags to decoded instructions, monitors the completion of executed instructions, and advances the tags in the queue upon completion of an executed instruction. The register stores a given decoded instruction at an address location in the register file defined by the tag assigned to that instruction. The register file also contains a plurality of read address enable ports and corresponding read output ports. Each of the slots from the queue is coupled to a corresponding one of the read address enable ports. Thus, a a decoded instruction is read out of a read output port enabled by the tag assigned to that decoded instruction in program order.
摘要翻译：标签监控系统，用于将标签分配给指令。存储单元存储由执行单元执行的指令。执行前，指令取出单元解码指令。寄存器文件存储解码的指令。具有包含用于标记解码指令的标签的多个时隙的队列。控制单元将标签分配给经解码的指令，监视执行指令的完成，并且在完成执行指令时将标签推进队列中。寄存器在由分配给该指令的标签定义的寄存器文件的地址位置处存储给定的解码指令。寄存器文件还包含多个读取地址使能端口和对应的读取输出端口。来自队列的每个时隙被耦合到对应的一个读取地址使能端口。因此，从由分配给该解码指令的标签启用的读取输出端口以编程顺序读出解码指令。

69. 发明授权

US07941635B2 High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distribution 失效
标题翻译：高性能超标量计算机系统，具有无序指令执行和并发结果分配
公开(公告)号：US07941635B2
公开(公告)日：2011-05-10
申请号：US11640967
申请日：2006-12-19
申请人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
发明人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
IPC分类号： G06F9/38
CPC分类号： G06F9/30167 , G06F9/30054 , G06F9/30101 , G06F9/30105 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30141 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3824 , G06F9/3828 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3857 , G06F9/3861 , G06F9/3865 , G06F9/3885
摘要： The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of instructions in an instruction buffer. The execution unit includes an instruction selection unit, coupled to the instruction buffer, for selecting instructions for execution, and a plurality of functional units for performing instruction specified functional operations. A unified instruction scheduler, within the instruction selection unit, initiates the processing of instructions through the functional units when instructions are determined to be available for execution and for which at least one of the functional units implementing a necessary computational function is available. Unified scheduling is performed across multiple execution data paths, where each execution data path, and corresponding functional units, is generally optimized for the type of computational function that is to be performed on the data: integer, floating point, and boolean. The number, type and computational specifics of the functional units provided in each data path, and as between data paths, are mutually independent.
摘要翻译：高性能的基于RISC核心的微处理器架构包括用于从指令存储器取出指令集的指令获取单元和通过并行的功能单元阵列实现多个指令的并发执行的执行单元。提取单元通常在指令缓冲器中保持预定数量的指令。执行单元包括指令选择单元，耦合到指令缓冲器，用于选择用于执行的指令;以及多个功能单元，用于执行指令指定的功能操作。在指令选择单元内的统一指令调度器，当确定可用于执行的指令并且实现必要的计算功能的功能单元中的至少一个可用时，通过功能单元启动对指令的处理。在多个执行数据路径上执行统一调度，其中每个执行数据路径和相应的功能单元通常针对要在数据上执行的计算函数类型进行优化：整数，浮点和布尔值。在每个数据路径中以及数据路径之间提供的功能单元的数量，类型和计算细节是相互独立的。

70. 发明申请

US20090235053A1 System and Method for Register Renaming 失效
标题翻译：用于注册重命名的系统和方法
公开(公告)号：US20090235053A1
公开(公告)日：2009-09-17
申请号：US12472052
申请日：2009-05-26
申请人： Trevor A. Deosaran , Sanjiv Garg , Kevin R. Iadonato
发明人： Trevor A. Deosaran , Sanjiv Garg , Kevin R. Iadonato
IPC分类号： G06F9/312 , G06F12/00 , G06F12/08 , G06F9/30
CPC分类号： G06F9/3838 , G06F9/384 , G06F9/3857
摘要： A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a location becomes available. A tag is assigned to each instruction in the variable advance instruction window. The tag of each instruction to leave the window is assigned to the next new instruction to be added to it. The results of instructions executed by the processor are stored in a temp buffer according to their corresponding tags to avoid output and anti-dependencies. The temp buffer therefore permits the processor to execute instructions out of order and in parallel. Data dependency checks for input dependencies are performed only for each new instruction added to the variable advance instruction window and register renaming is performed to avoid input dependencies.
摘要翻译：一种用于在具有用于存储要由处理器执行的指令组的可变提前指令窗口的处理器中执行寄存器重命名源寄存器的系统和方法，其中当位置变得可用时将新指令添加到可变提前指令窗口。标签被分配给变量提前指令窗口中的每个指令。离开窗口的每个指令的标签被分配给要添加到其中的下一个新指令。由处理器执行的指令的结果根据其相应的标签存储在临时缓冲器中，以避免输出和反依赖。因此，临时缓冲器允许处理器按顺序并行执行指令。仅对添加到变量提前指令窗口的每个新指令执行输入相关性的数据依赖性检查，并执行寄存器重命名以避免输入依赖关系。

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