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61. 发明授权

US07111209B2 Test pattern compression for an integrated circuit test environment 有权
公开(公告)号：US07111209B2
公开(公告)日：2006-09-19
申请号：US10355941
申请日：2003-01-31
申请人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
发明人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G01R31/28
CPC分类号： G01R31/318335 , G01R31/318371 , G01R31/318547
摘要： A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.

62. 发明申请

US20060156134A1 Programmable memory built-in-self-test (MBIST) method and apparatus 有权
标题翻译：可编程存储器内置自检（MBIST）方法和装置
公开(公告)号：US20060156134A1
公开(公告)日：2006-07-13
申请号：US11283527
申请日：2005-11-18
申请人： Nilanjan Mukherjee , Xiaogang Du , Wu-Tung Cheng
发明人： Nilanjan Mukherjee , Xiaogang Du , Wu-Tung Cheng
IPC分类号： G01R31/28
CPC分类号： G01R31/3187 , G01R31/31724 , G01R31/318519 , G11C29/10 , G11C29/1201 , G11C29/16 , G11C29/20 , G11C2029/0401 , G11C2029/0405 , G11C2029/3602 , G11C2029/5604
摘要： Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing.
摘要翻译：公开了可编程存储器内置的自检（MBIST）方法，装置和系统。所公开的技术的示例性实施例可以用于例如在制造测试期间测试位于集成电路上的一个或多个存储器。

63. 发明申请

US20050204231A1 Testing memories using algorithm selection 有权
标题翻译：使用算法选择测试记忆
公开(公告)号：US20050204231A1
公开(公告)日：2005-09-15
申请号：US10861851
申请日：2004-06-04
申请人： Nilanjan Mukherjee , Joseph Rayhawk , Amrendra Kumar
发明人： Nilanjan Mukherjee , Joseph Rayhawk , Amrendra Kumar
IPC分类号： G01R31/28 , G11C29/00
CPC分类号： G11C29/10 , G11C29/14 , G11C29/16 , G11C29/38 , G11C2029/3202
摘要： A method of performing a built-in-self-test (BIST) of at least one memory element of a circuit is disclosed. In a specific example, a determination is made during running of a BIST whether one or more algorithms are to be run. If any algorithm is not designated for running, the particular algorithm is skipped and the test moves to other algorithms to be run. A BIST controller is configured to perform a group of test algorithms. Certain algorithms from the group may be checked to see if they are to be run or bypassed. A delay or skip state is desirably interposed following the inclusion of a particular algorithm and prior to the start of a next algorithm. A determination is made during the delay or skip state whether the next algorithm is to be run. The user may also have the option of running all of the algorithms if desired for performance of a particular BIST.
摘要翻译：公开了一种执行电路的至少一个存储元件的内置自检（BIST）的方法。在具体示例中，在BIST的运行期间确定是否要运行一个或多个算法。如果没有指定运算的算法，跳过特定的算法，并且测试移动到要运行的其他算法。 BIST控制器被配置为执行一组测试算法。可以检查组中的某些算法，以查看它们是要运行还是旁路。期望在包含特定算法之后并且在下一个算法开始之前插入延迟或跳过状态。在延迟或跳过状态期间确定是否要运行下一个算法。如果需要执行特定的BIST，用户还可以选择运行所有算法。

64. 发明授权

US06708192B2 Method for synthesizing linear finite state machines 有权
标题翻译：线性有限状态机的合成方法
公开(公告)号：US06708192B2
公开(公告)日：2004-03-16
申请号：US10346699
申请日：2003-01-16
申请人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
发明人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G06F102
CPC分类号： G06F7/584 , G06F2207/583 , H03K3/84
摘要： Method and apparatus for synthesizing high-performance linear finite state machines (LFSMs) such as linear feedback shift registers (LFSRs) or cellular automata (CA). Given a characteristic polynomial for the circuit, the method obtains an original LFSM circuit such as a type I or type II LFSR. Feedback connections within the original circuit are then determined. Subsequently, a number of transformations that shift the feedback connections can be applied in such a way that properties of the original circuit are preserved in a modified LFSM circuit. In particular, if the original circuit is represented by a primitive characteristic polynomial, the method preserves the maximum-length property of the original circuit in the modified circuit and enables the modified circuit to produce the same m-sequence as the original circuit. Through the various transformations, a modified LFSM circuit can be created that provides higher performance through shorter feedback connection lines, fewer levels of logic, and lower internal fan-out.
摘要翻译：用于合成诸如线性反馈移位寄存器（LFSR）或细胞自动机（CA）的高性能线性有限状态机（LFSM）的方法和装置。给定电路的特征多项式，该方法获得原始的LFSM电路，如I型或II型LFSR。然后确定原始电路内的反馈连接。随后，可以以使原始电路的特性保留在修改的LFSM电路中的方式来应用移动反馈连接的多个变换。特别地，如果原始电路由原始特征多项式表示，则该方法保留修改电路中原始电路的最大长度特性，并使修改电路能够产生与原始电路相同的m序列。通过各种转换，可以创建一个修改后的LFSM电路，通过较短的反馈连接线路提供更高的性能，更低的逻辑电平和更低的内部扇出。

65. 发明授权

US06363506B1 Method for self-testing integrated circuits 有权
标题翻译：集成电路自检方法
公开(公告)号：US06363506B1
公开(公告)日：2002-03-26
申请号：US09291448
申请日：1999-04-13
申请人： Ramesh Karri , Nilanjan Mukherjee
发明人： Ramesh Karri , Nilanjan Mukherjee
IPC分类号： G01R3128
CPC分类号： G01R31/318371
摘要： A versatile testing scheme provides both off-line and on-line integrated circuit testing using common test circuitry. The testing scheme generates test patterns, applies test patterns and compacts test responses to test the integrated circuit. The original design of the integrated circuit may be modified so that the functional units of the original design perform test operations during idle processing cycles in the normal mode of operation. To this end, functional units of the design may be constrained to perform the test function by coordinating the generation and application of the test patterns and the compaction of the test responses with a usage profile of the functional units.
摘要翻译：通用测试方案提供使用常用测试电路的离线和在线集成电路测试。测试方案生成测试模式，应用测试模式和压缩测试响应来测试集成电路。可以修改集成电路的原始设计，使得原始设计的功能单元在正常操作模式中的空闲处理周期期间执行测试操作。为此，设计的功能单元可以被限制为通过协调测试模式的生成和应用以及测试响应的压缩与功能单元的使用简档来执行测试功能。

66. 发明授权

US06327687B1 Test pattern compression for an integrated circuit test environment 有权
标题翻译：用于集成电路测试环境的测试模式压缩
公开(公告)号：US06327687B1
公开(公告)日：2001-12-04
申请号：US09619985
申请日：2000-07-20
申请人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G06F1100
CPC分类号： G01R31/318335 , G01R31/318371 , G01R31/318547
摘要： A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.
摘要翻译：一种用于压缩被测电路中扫描链应用的测试图案的方法。该方法包括生成与扫描链内的扫描单元相关联的符号表达式。通过将变量分配给提供给被测电路的外部输入通道上的位来创建符号表达式。使用符号仿真，将变量应用于解压缩器以获取符号表达式。使用确定性模式创建测试立方体，该模式为扫描单元分配值以测试集成电路中的故障。通过将测试立方体中的分配值与与相应扫描单元相关联的符号表达式进行等价来表示一组方程式。求解等式以获得压缩测试图案。

67. 发明申请

US20220067242A1 MODIFYING A FINITE ELEMENT MESH 有权
公开(公告)号：US20220067242A1
公开(公告)日：2022-03-03
申请号：US17412637
申请日：2021-08-26
申请人： Nilanjan Mukherjee , Jean Cabello , Jonathan Makem , Wafa Daldoul
发明人： Nilanjan Mukherjee , Jean Cabello , Jonathan Makem , Wafa Daldoul
IPC分类号： G06F30/23
摘要： A computer-implemented method of modifying a finite element mesh. The method includes providing an original-input-orphan-mesh, selecting and extracting at least a part of the original-input-orphan-mesh as an orphan-element-patch-object, generating faces on the orphan-element-patch-object as a faces-on-mesh-object geometry, generating a new mesh patch element based on the faces-on-mesh-object-geometry and at least one changed meshing-parameter. The changed meshing-parameter is assigned to generate a new mesh patch element that is different to the corresponding original-input-orphan-mesh. The method further includes generating an amended orphan mesh by replacing the orphan-element-patch-object of the original-input-orphan-mesh by the new mesh patch element.

68. 发明授权

US08832512B2 Low power compression of incompatible test cubes 有权
标题翻译：不兼容的测试立方体的低功率压缩
公开(公告)号：US08832512B2
公开(公告)日：2014-09-09
申请号：US13049829
申请日：2011-03-16
申请人： Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Przemyslaw Szczerbicki , Jerzy Tyszer
发明人： Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Przemyslaw Szczerbicki , Jerzy Tyszer
IPC分类号： G06F11/00
CPC分类号： G06F11/079
摘要： Disclosed are representative embodiments of methods, apparatus, and systems for power aware test applications involving deterministic clustering of test cubes with conflicts. Embodiments of the disclosed technology can be used to generate low toggling parent patterns to reduce power consumption during testing an integrated circuit. The power consumption may be further reduced by generating low toggling control patterns.
摘要翻译：公开了涉及用于具有冲突的测试立方体的确定性聚类的功率感知测试应用的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于产生低切换父模式，以降低测试集成电路期间的功耗。可以通过产生低切换控制模式来进一步降低功耗。

69. 发明授权

US08533547B2 Continuous application and decompression of test patterns and selective compaction of test responses 有权
公开(公告)号：US08533547B2
公开(公告)日：2013-09-10
申请号：US13013712
申请日：2011-01-25
申请人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.

70. 发明授权

US08499209B2 At-speed scan testing with controlled switching activity 有权
标题翻译：具有受控切换活动的高速扫描测试
公开(公告)号：US08499209B2
公开(公告)日：2013-07-30
申请号：US12765530
申请日：2010-04-22
申请人： Janusz Rajski , Elham K. Moghaddam , Nilanjan Mukherjee , Mark A Kassab , Xijiang Lin
发明人： Janusz Rajski , Elham K. Moghaddam , Nilanjan Mukherjee , Mark A Kassab , Xijiang Lin
IPC分类号： G01R31/28 , G06F11/00 , G06F9/455 , G06F17/50 , G06F11/22
CPC分类号： G01R31/318547 , G01R31/318575
摘要： Test patterns for at-speed scan tests are generated by filling unspecified bits of test cubes with functional background data. Functional background data are scan cell values observed when switching activity of the circuit under test is near a steady state. Hardware implementations in EDT (embedded deterministic test) environment are also disclosed.
摘要翻译：通过用功能背景数据填充测试立方体的未指定位来生成速度扫描测试的测试模式。功能背景数据是当被测电路的开关活动接近稳定状态时观察到的扫描单元值。还公布了EDT（嵌入式确定性测试）环境中的硬件实现。

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