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61. 发明申请

US20090254689A1 METHODS AND APPARATUS FOR TWO-DIMENSIONAL MAIN MEMORY 有权
标题翻译：二维主要记忆的方法和装置
公开(公告)号：US20090254689A1
公开(公告)日：2009-10-08
申请号：US12369733
申请日：2009-02-11
申请人： Vijay Karamcheti , Kumar Ganapathy
发明人： Vijay Karamcheti , Kumar Ganapathy
IPC分类号： G06F13/00 , G06F17/30
CPC分类号： G11C16/0408 , G06F7/78 , G06F12/0207 , G06F12/0246 , G06F12/0607 , G06F17/30477 , G06F2212/7201 , G06F2212/7208 , G11C16/06 , Y02D10/13
摘要： In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.
摘要翻译：在本发明的一个实施例中，公开了一种存储器模块，其包括具有边缘连接器的印刷电路板; 耦合到所述印刷电路板的地址控制器; 和多个存储器片。存储器模块的多个存储器片段中的每一个包括耦合到印刷电路板的一个或多个存储器集成电路，以及耦合到印刷电路板和一个或多个存储器集成电路的从存储器控制器。从存储器控制器从地址控制器接收存储器模块的存储器访问请求。从存储器控制器响应于从地址控制器接收到的地址来选择性地激活相应存储器片中的一个或多个存储器集成电路中的一个或多个，以将数据从存储器集成电路中的选择的存储器位置读取或写入数据。

62. 发明授权

US09093150B2 Multi-chip packaged integrated circuit with flash memory and slave memory controller 有权
标题翻译：具有闪存和从属存储器控制器的多芯片封装集成电路
公开(公告)号：US09093150B2
公开(公告)日：2015-07-28
申请号：US14016224
申请日：2013-09-03
申请人： Vijay Karamcheti , Kumar Ganapathy
发明人： Vijay Karamcheti , Kumar Ganapathy
IPC分类号： G11C16/04 , G06F12/06 , G06F17/30 , G06F12/02
CPC分类号： G11C16/0408 , G06F7/78 , G06F12/0207 , G06F12/0246 , G06F12/0607 , G06F17/30477 , G06F2212/7201 , G06F2212/7208 , G11C16/06 , Y02D10/13
摘要： A multi-chip packaged integrated circuit part for mounting to a printed circuit board of a memory module. The multi-chip packaged integrated circuit part comprises an integrated circuit package including a slave memory controller (SMC) die; and pairs of a spacer under the slave memory controller die, and a flash memory die under the spacer. In each pair, the flash memory die may be larger than the spacer so that an opening is provided into a perimeter of the flash memory die to allow electrical connections to be made. A plurality of conductors may be used to electrically couple the slave memory controller die and the flash memory die to one or more pads of a pin-out of the integrated circuit package.
摘要翻译：一种用于安装到存储器模块的印刷电路板的多芯片封装集成电路部件。多芯片封装集成电路部分包括集成电路封装，其包括从存储器控制器（SMC）管芯; 以及在从存储器控制器管芯之下的间隔物对，以及在间隔件下的闪存管芯。在每对中，闪存芯片可以大于间隔件，使得开口设置在闪存芯片的周边中，以允许进行电连接。可以使用多个导体来将从存储器控制器管芯和闪存管芯电耦合到集成电路封装的引脚输出的一个或多个焊盘。

63. 发明申请

US20150032940A1 METHODS OF MANAGING POWER IN NETWORK COMPUTER SYSTEMS 有权
标题翻译：网络计算机系统管理功率的方法
公开(公告)号：US20150032940A1
公开(公告)日：2015-01-29
申请号：US13952567
申请日：2013-07-26
申请人： Vijay Karamcheti , Kenneth A. Okin , Kumar Ganapathy
发明人： Vijay Karamcheti , Kenneth A. Okin , Kumar Ganapathy
IPC分类号： G06F12/02
CPC分类号： G06F1/329 , G06F1/3209 , G06F1/3287 , G06F3/061 , G06F3/0625 , G06F3/0638 , G06F3/0653 , G06F3/0674 , G06F3/0689 , G06F9/5094 , Y02D10/154 , Y02D10/171 , Y02D10/22 , Y02D10/24
摘要： In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.
摘要翻译：在本发明的一个实施例中，公开了一种存储装置。存储装置包括存储器阵列，块读/写控制器和随机存取读存储器控制器。存储器阵列是块读/写可访问和随机读取可访问的。块读/写控制器耦合在存储器阵列和外部互连之间。块读/写控制器对存储器阵列执行块读/写操作，以访问其中的连续存储单元的块。随机访问读存储器控制器与块读/写访问控制器并行地耦合在存储器阵列和外部互连之间。随机存取读取存储器控制器对存储器阵列执行随机读取存储器操作以访问其中的随机存储器位置。

64. 发明授权

US08417873B1 Random read and read/write block accessible memory 有权
标题翻译：随机读取和读取/写入可访问存储器
公开(公告)号：US08417873B1
公开(公告)日：2013-04-09
申请号：US12490914
申请日：2009-06-24
申请人： Vijay Karamcheti , Kenneth A. Okin , Kumar Ganapathy
发明人： Vijay Karamcheti , Kenneth A. Okin , Kumar Ganapathy
IPC分类号： G06F13/00
CPC分类号： G06F12/0246 , G06F12/0866 , G06F13/1694 , G06F2212/211
摘要： In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.
摘要翻译：在本发明的一个实施例中，公开了一种存储装置。存储装置包括存储器阵列，块读/写控制器和随机存取读存储器控制器。存储器阵列是块读/写可访问和随机读取可访问的。块读/写控制器耦合在存储器阵列和外部互连之间。块读/写控制器对存储器阵列执行块读/写操作，以访问其中的连续存储单元的块。随机访问读存储器控制器与块读/写访问控制器并行地耦合在存储器阵列和外部互连之间。随机存取读取存储器控制器对存储器阵列执行随机读取存储器操作以访问其中的随机存储器位置。

65. 发明授权

US08806116B2 Memory modules for two-dimensional main memory 有权
标题翻译：内存模块用于二维主内存
公开(公告)号：US08806116B2
公开(公告)日：2014-08-12
申请号：US12369725
申请日：2009-02-11
申请人： Vijay Karamcheti , Kumar Ganapathy
发明人： Vijay Karamcheti , Kumar Ganapathy
IPC分类号： G06F12/00 , G11C5/14
CPC分类号： G06F12/0246 , G11C5/04 , G11C29/76
摘要： In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.
摘要翻译：在本发明的一个实施例中，公开了一种存储器模块，其包括具有边缘连接器的印刷电路板; 耦合到所述印刷电路板的地址控制器; 和多个存储器片。存储器模块的多个存储器片段中的每一个包括耦合到印刷电路板的一个或多个存储器集成电路，以及耦合到印刷电路板和一个或多个存储器集成电路的从存储器控制器。从存储器控制器从地址控制器接收存储器模块的存储器访问请求。从存储器控制器响应于从地址控制器接收到的地址来选择性地激活相应存储器片中的一个或多个存储器集成电路中的一个或多个，以将数据从存储器集成电路中的选择的存储器位置读取或写入数据。

66. 发明授权

US09251899B2 Methods for upgrading main memory in computer systems to two-dimensional memory modules and master memory controllers 有权
标题翻译：将计算机系统中的主内存升级为二维内存模块和主内存控制器的方法
公开(公告)号：US09251899B2
公开(公告)日：2016-02-02
申请号：US12369733
申请日：2009-02-11
申请人： Vijay Karamcheti , Kumar Ganapathy
发明人： Vijay Karamcheti , Kumar Ganapathy
IPC分类号： G06F12/06 , G06F7/78 , G06F12/02 , G11C16/04 , G06F17/30
CPC分类号： G11C16/0408 , G06F7/78 , G06F12/0207 , G06F12/0246 , G06F12/0607 , G06F17/30477 , G06F2212/7201 , G06F2212/7208 , G11C16/06 , Y02D10/13
摘要： In one embodiment of the invention, a method of upgrading main memory in a computer system is disclosed. The method includes plugging a plurality of two dimensional memory modules into a plurality of memory module sockets and coupling a master memory controller between one or more processors and the plurality of memory modules. Each of the two dimensional memory modules includes memory in a plurality of memory slices and a plurality of slave memory controllers respectively coupled to the memory in the plurality of memory slices. According, the upgrading method further includes buffering and transposing data between a column by column format for the one or more processors and a row by row format for the memory in the plurality of memory slices.
摘要翻译：在本发明的一个实施例中，公开了一种在计算机系统中升级主存储器的方法。该方法包括将多个二维存储器模块插入多个存储器模块插槽中，并将主存储器控制器耦合在一个或多个处理器与多个存储器模块之间。二维存储器模块中的每一个包括多个存储器片中的存储器和分别耦合到多个存储器片中的存储器的多个从存储器控制器。根据该升级方法还包括缓冲和转置用于一个或多个处理器的逐列格式的数据以及多个存储器片中的存储器的逐行格式。

67. 发明授权

US09251061B2 Methods for accessing memory in a two-dimensional main memory having a plurality of memory slices 有权
标题翻译：用于访问具有多个存储器片的二维主存储器中的存储器的方法
公开(公告)号：US09251061B2
公开(公告)日：2016-02-02
申请号：US14016218
申请日：2013-09-02
申请人： Vijay Karamcheti , Kumar Ganapathy
发明人： Vijay Karamcheti , Kumar Ganapathy
IPC分类号： G06F12/02 , G11C5/04 , G11C29/00
CPC分类号： G06F12/0246 , G11C5/04 , G11C29/76
摘要： In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.
摘要翻译：在本发明的一个实施例中，公开了一种存储器模块，其包括具有边缘连接器的印刷电路板; 耦合到所述印刷电路板的地址控制器; 和多个存储器片。存储器模块的多个存储器片段中的每一个包括耦合到印刷电路板的一个或多个存储器集成电路，以及耦合到印刷电路板和一个或多个存储器集成电路的从存储器控制器。从存储器控制器从地址控制器接收存储器模块的存储器访问请求。从存储器控制器响应于从地址控制器接收到的地址来选择性地激活相应存储器片中的一个或多个存储器集成电路中的一个或多个，以将数据从存储器集成电路中的选择的存储器位置读取或写入数据。

68. 发明申请

US20140071755A1 MULTI-CHIP PACKAGED INTEGRATED CIRCUIT WITH FLASH MEMORY 有权
标题翻译：具有闪存存储器的多芯片封装集成电路
公开(公告)号：US20140071755A1
公开(公告)日：2014-03-13
申请号：US14016224
申请日：2013-09-03
申请人： Vijay Karamcheti , Kumar Ganapathy
发明人： Vijay Karamcheti , Kumar Ganapathy
IPC分类号： G11C16/04
CPC分类号： G11C16/0408 , G06F7/78 , G06F12/0207 , G06F12/0246 , G06F12/0607 , G06F17/30477 , G06F2212/7201 , G06F2212/7208 , G11C16/06 , Y02D10/13
摘要： In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.
摘要翻译：在本发明的一个实施例中，公开了一种存储器模块，其包括具有边缘连接器的印刷电路板; 耦合到所述印刷电路板的地址控制器; 和多个存储器片。存储器模块的多个存储器片中的每一个包括耦合到印刷电路板的一个或多个存储器集成电路，以及耦合到印刷电路板和一个或多个存储器集成电路的从存储器控制器。从存储器控制器从地址控制器接收存储器模块的存储器访问请求。从存储器控制器响应于从地址控制器接收到的地址来选择性地激活相应存储器片中的一个或多个存储器集成电路中的一个或多个，以将数据从存储器集成电路中的选择的存储器位置读取或写入数据。

69. 发明授权

US08521967B1 Network computing systems having shared memory clouds with addresses of disk-read-only memories mapped into processor address spaces 有权
标题翻译：具有共享存储器云的网络计算系统与映射到处理器地址空间的只读存储器的地址
公开(公告)号：US08521967B1
公开(公告)日：2013-08-27
申请号：US12490941
申请日：2009-06-24
申请人： Vijay Karamcheti , Kenneth A. Okin , Kumar Ganapathy
发明人： Vijay Karamcheti , Kenneth A. Okin , Kumar Ganapathy
IPC分类号： G06F13/00 , G06F15/167
CPC分类号： G06F12/0246 , G06F12/0866 , G06F13/1694 , G06F2212/211
摘要： Network computing systems are disclosed including a shared memory cloud coupled to one or more processor complexes. The shared memory cloud has an interconnect network coupled to disk-read-only-memories (disk-ROMs) each including a memory array that is read/write block accessible to access blocks of consecutive memory locations and random read memory accessible to access random memory locations. The processor complexes read and write blocks of data from/to the disk-ROMs to provide disk-like access to the shared memory cloud. Each processor complex maps the addresses of one or more of the disk-ROMs into processor address spaces, and reads from random memory locations of one or more of the disk-ROMs to provide main memory-like access to the shared memory cloud. The network computing systems may further include a power controller coupled to the processor complexes. The power controller can keep the disk-ROMS powered on while it powers off inactive processor complexes.
摘要翻译：公开了包括耦合到一个或多个处理器复合体的共享存储器云的网络计算系统。共享存储器云具有耦合到磁盘只读存储器（磁盘 - ROM）的互连网络，每个磁盘 - 只读存储器（磁盘 - ROM）包括可访问连续存储器位置的块的读/写块的存储器阵列和访问随机存储器的随机读取存储器位置。处理器将读/写数据块从/到磁盘-ROM中，以便为共享内存云提供类似磁盘的访问。每个处理器复合体将一个或多个磁盘ROM的地址映射到处理器地址空间中，并从一个或多个磁盘ROM的随机存储器位置读取以提供对共享存储器云的主存储器访问。网络计算系统还可以包括耦合到处理器复合体的功率控制器。电源控制器可以在关闭非活动处理器组合时关闭磁盘ROMS电源。

70. 发明申请

US20090210616A1 MEMORY MODULES FOR TWO-DIMENSIONAL MAIN MEMORY 有权
标题翻译：用于二维主存储器的存储器模块
公开(公告)号：US20090210616A1
公开(公告)日：2009-08-20
申请号：US12369725
申请日：2009-02-11
申请人： Vijay Karamcheti , Kumar Ganapathy
发明人： Vijay Karamcheti , Kumar Ganapathy
IPC分类号： G06F12/00 , G11C5/14 , G06F9/34 , G11C7/00
CPC分类号： G06F12/0246 , G11C5/04 , G11C29/76
摘要： In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.
摘要翻译：在本发明的一个实施例中，公开了一种存储器模块，其包括具有边缘连接器的印刷电路板; 耦合到所述印刷电路板的地址控制器; 和多个存储器片。存储器模块的多个存储器片段中的每一个包括耦合到印刷电路板的一个或多个存储器集成电路，以及耦合到印刷电路板和一个或多个存储器集成电路的从存储器控制器。从存储器控制器从地址控制器接收存储器模块的存储器访问请求。从存储器控制器响应于从地址控制器接收到的地址来选择性地激活相应存储器片中的一个或多个存储器集成电路中的一个或多个，以将数据从存储器集成电路中的选择的存储器位置读取或写入数据。

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