专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US5802390A Data bus circuit and method of changing over termination resistor of the data bus circuit 失效
标题翻译：数据总线电路和数据总线电路终端电阻的切换方法
公开(公告)号：US5802390A
公开(公告)日：1998-09-01
申请号：US411461
申请日：1995-03-28
申请人： Kenji Kashiwagi , Akira Yamagiwa , Masao Inoue
发明人： Kenji Kashiwagi , Akira Yamagiwa , Masao Inoue
IPC分类号： H04L25/02 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4077 , Y02B60/1228 , Y02B60/1235
摘要： A data bus circuit includes a plurality of data buses, a plurality of data processing units connected to each of the data buses for performing transmission and reception of data in response to a transmission control signal, at least a termination resistor connected to termination of the plurality of data buses, the termination resistor including a first resistance circuit for suppressing reflection of signals on the plurality of data buses upon transmission and reception of data of the plurality of data processing units and a second resistance circuit having a resistance value larger than that of the first resistance circuit, an output control circuit for producing the transmission control signal as to whether the plurality of data processing units perform transmission and reception of data or not, and a changing-over circuit for changing over to connect the first resistance circuit to the data buses through which transmission and reception of data is performed when at least one of the plurality of data processing units performs transmission and reception of data in response to the transmission control signal and to connect the second resistance circuit to the data buses through which transmission and reception of data is not performed when any of the plurality of data processing units does not perform transmission and reception of data, whereby a current flowing in the termination resistor can be reduced when data is not transmitted on the data bus and the low power consumption of the data bus circuit can be attained.
摘要翻译：数据总线电路包括多个数据总线，连接到每个数据总线的多个数据处理单元，用于响应于传输控制信号执行数据的发送和接收，至少连接到多个终端的终端电阻器的数据总线，所述终端电阻器包括用于在发送和接收所述多个数据处理单元的数据时抑制所述多个数据总线上的信号的反射的第一电阻电路和具有大于所述多个数据总线的电阻值的电阻值的第二电阻电路第一电阻电路，用于产生关于多个数据处理单元是否执行数据的发送和接收的传输控制信号的输出控制电路和用于切换以将第一电阻电路连接到数据的转换电路当至少其中之一执行数据传输和接收时的总线多个数据处理单元响应于传输控制信号执行数据的发送和接收，并且当多个数据处理单元中的任何一个没有执行时，将第二电阻电路连接到数据总线，通过该数据总线不执行数据的发送和接收执行数据的发送和接收，从而当数据总线上不发送数据时可以减少在终端电阻器中流动的电流，并且可以实现数据总线电路的低功耗。

62. 发明授权

US4812684A Multiphase clock distribution for VLSI chip 失效
标题翻译： VLSI芯片的多相时钟分配
公开(公告)号：US4812684A
公开(公告)日：1989-03-14
申请号：US146864
申请日：1988-01-22
申请人： Akira Yamagiwa , Toshihiro Okabe
发明人： Akira Yamagiwa , Toshihiro Okabe
IPC分类号： H01L27/088 , G06F1/04 , G06F1/10 , G06F15/78 , G06F17/50 , G11C11/401 , H01L21/8234 , H03K5/15 , H03K19/00 , H03K19/003 , H03K19/0175 , H03K19/096
CPC分类号： G06F1/10 , H03K19/00323
摘要： Multi-phase clock signals are delivered to a large number of load circuits scattered on a chip from clock signal input pins through at least three stage buffer circuits. The first stage buffer circuits are arranged in the neighborhood of the input pins, and the second stage buffer circuits are arranged on the central portion of the chip. Equivalent-length wirings are made between the successive two stage buffer circuits and the same number of subsequent stage buffer circuit are connected with each of certain stage buffer circuits for the respective phases so as to provide equal resistances and equal capacitances. Equivalent-length wirings are also made between final stage buffer circuits and the corresponding load circuits, and the same number of load circuits are connected with each final stage buffer circuit. Thus, equal delay times are provided in the clock signal paths from the input pins to the load circuits at the respective phases.
摘要翻译：多相时钟信号通过至少三级缓冲电路从时钟信号输入引脚传送到分散在芯片上的大量负载电路。第一级缓冲电路布置在输入引脚附近，第二级缓冲电路布置在芯片的中心部分。在连续的两级缓冲电路之间进行等效长度布线，并且相同数量的后级缓冲电路与各相的各级缓冲电路连接，以提供相等的电阻和相等的电容。最终级缓冲电路和相应的负载电路之间也有等长线，并且每个最后级缓冲电路连接相同数量的负载电路。因此，在从各个相位的输入引脚到负载电路的时钟信号路径中提供相等的延迟时间。

63. 发明授权

US4516039A Logic circuit utilizing a current switch circuit having a non-threshold transfer characteristic 失效
标题翻译：利用具有非阈值传递特性的电流开关电路的逻辑电路
公开(公告)号：US4516039A
公开(公告)日：1985-05-07
申请号：US343379
申请日：1982-01-27
申请人： Isokazu Matsuzaki , Akira Yamagiwa , Yutaka Watanabe , Takashi Matsumoto , Katsumi Yabe
发明人： Isokazu Matsuzaki , Akira Yamagiwa , Yutaka Watanabe , Takashi Matsumoto , Katsumi Yabe
IPC分类号： H03K19/086 , H03K19/013
CPC分类号： H03K19/086
摘要： A logic circuit (FIGS. 4A, 5A and 6A) comprises a current switch circuit (FIG. 4A) which has a non-threshold transfer characteristic (FIG. 4B), operates in non-saturation region, and is suited to a high speed operation.The current switch circuit is formed by a pair of transistors (6 or 7, and 8), one of which (6 or 7) receives an input signal at its base, and the other (8) has its base and collector connected in d.c. coupling to each other. The pair of transistors are connected with a common constant current source (9) at their emitters, deliver an output from their collectors, and are so biased as to operate in the non-saturation region.In the current switch circuit, due to the d.c. coupling between the base and the collector of the other transistor (8), the voltage level of the collector changes linearly in accordance with the input signal of the current switch circuit. This allows for a transfer characteristic having no threshold and a very small delay time between the input signal and the output signal. Moreover, the operation of transistors in the non-saturation region makes possible a logical operation which is high in speed and short in delay time.
摘要翻译：逻辑电路（图4A，5A和6A）包括具有非阈值传递特性的电流开关电路（图4A）（图4B），在非饱和区域中工作，并且适合于高速操作。电流开关电路由一对晶体管（6或7和8）形成，其中一个晶体管（6或7）在其基极接收输入信号，另一个（8）的基极和集电极连接成直流。相互耦合。该对晶体管在其发射极处与公共恒流源（9）连接，从其集电极输出输出，并被偏置以在非饱和区域中工作。在当前的开关电路中，由于直流耦合在另一个晶体管（8）的基极和集电极之间，集电极的电压根据电流开关电路的输入信号线性变化。这允许在输入信号和输出信号之间没有阈值和非常小的延迟时间的传输特性。此外，在非饱和区域中的晶体管的操作使得可能的速度高和延迟时间短的逻辑运算。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式