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61. 发明授权

US5438220A High breakdown voltage semiconductor device 失效
标题翻译：高击穿电压半导体器件
公开(公告)号：US5438220A
公开(公告)日：1995-08-01
申请号：US085056
申请日：1993-07-02
申请人： Akio Nakagawa , Norio Yasuhara , Tomoko Matsudai , Yoshihiro Yamaguchi , Ichiro Omura , Hideyuki Funaki
发明人： Akio Nakagawa , Norio Yasuhara , Tomoko Matsudai , Yoshihiro Yamaguchi , Ichiro Omura , Hideyuki Funaki
IPC分类号： H01L21/336 , H01L21/74 , H01L21/762 , H01L27/06 , H01L27/092 , H01L27/12 , H01L29/06 , H01L29/08 , H01L29/40 , H01L29/739 , H01L29/74 , H01L29/745 , H01L29/749 , H01L29/78 , H01L29/786 , H01L29/861
CPC分类号： H01L29/404 , H01L21/74 , H01L21/76264 , H01L21/76297 , H01L27/0623 , H01L27/0922 , H01L27/1203 , H01L29/0834 , H01L29/402 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/66772 , H01L29/7394 , H01L29/7436 , H01L29/7455 , H01L29/749 , H01L29/7824 , H01L29/7835 , H01L29/78624 , H01L29/8611 , H01L21/76275 , H01L21/76286 , H01L29/78603 , H01L2924/0002
摘要： A high breakdown voltage semiconductor device includes a semiconductor substrate, an insulating layer formed on the semiconductor substrate, an active layer formed on the insulating layer and made of a high resistance semiconductor of a first conductivity type, a first impurity region of the first conductivity type formed in the active layer, and a second impurity region of a second conductivity type formed in the active layer and spaced apart from the first impurity region by a predetermined distance. The first impurity region is formed of diffusion layers. The diffusion layers are superimposed one upon another and differ in diffusion depth or diffusion window width, or both.
摘要翻译：高耐压半导体器件包括半导体衬底，形成在半导体衬底上的绝缘层，形成在绝缘层上并由第一导电类型的高电阻半导体形成的有源层，第一导电类型的第一杂质区形成在有源层中的第二杂质区和形成在有源层中并与第一杂质区隔开预定距离的第二导电类型的第二杂质区。第一杂质区由扩散层形成。扩散层彼此叠加并且扩散深度或扩散窗宽度不同，或两者均不同。

62. 发明授权

US5428228A Method of operating thyristor with insulated gates 失效
标题翻译：用绝缘栅极操作晶闸管的方法
公开(公告)号：US5428228A
公开(公告)日：1995-06-27
申请号：US164756
申请日：1993-12-10
申请人： Tsuneo Ogura , Kiminori Watanabe , Akio Nakagawa , Yoshihiro Yamaguchi , Norio Yasuhara , Tomoko Matsudai , Shigeru Hasegawa , Kazuya Nakayama
发明人： Tsuneo Ogura , Kiminori Watanabe , Akio Nakagawa , Yoshihiro Yamaguchi , Norio Yasuhara , Tomoko Matsudai , Shigeru Hasegawa , Kazuya Nakayama
IPC分类号： H01L27/06 , H01L29/74 , H01L29/745 , H01L29/749 , H01L29/747
CPC分类号： H01L27/0617 , H01L29/7436 , H01L29/7455 , H01L29/749
摘要： A thyristor with insulated gates includes turn-off and turn-on MOSFETs. The turn-on MOSFET has a turn-on gate employing a p-type base as a channel and extending over an n-type base and an n-type emitter. The turn-off MOSFET has n-type drain and source layers formed in a p-type base layer, and a turn-off gate extending over the drain and source layers. The n-type drain layer is short-circuited with the p-type base layer via a drain electrode. The drain electrode is formed near an n-type emitter layer. When the thyristor is to be turned off, the first voltage is applied to the turn-on gate, and the second voltage is applied to the turn-off gate while the first voltage is applied to the turn-on gate. After the application of the second voltage continues for a predetermined period of time, the application of the first voltage to the turn-on gate is stopped. With this operation, the thyristor can be turned off even with a large current.
摘要翻译：具有绝缘栅极的晶闸管包括关断和导通MOSFET。导通MOSFET具有采用p型基极作为沟道并在n型基极和n型发射极上延伸的导通栅极。关断MOSFET具有形成在p型基极层中的n型漏极和源极层，以及在漏极和源极层上延伸的截止栅极。 n型漏极层经由漏电极与p型基极层短路。在n型发射极层附近形成漏电极。当晶闸管关断时，第一电压被施加到导通栅极，并且第二电压被施加到关断栅极，同时第一电压被施加到导通栅极。在第二电压的施加持续预定时间段之后，停止向导通门施加第一电压。通过这种操作，即使使用大电流，晶闸管也可以关闭。

63. 发明授权

US5294825A High breakdown voltage semiconductor device 失效
标题翻译：高击穿电压半导体器件
公开(公告)号：US5294825A
公开(公告)日：1994-03-15
申请号：US753433
申请日：1991-08-30
申请人： Akio Nakagawa , Norio Yasuhara
发明人： Akio Nakagawa , Norio Yasuhara
IPC分类号： H01L21/336 , H01L21/74 , H01L21/762 , H01L27/06 , H01L27/092 , H01L27/12 , H01L29/06 , H01L29/40 , H01L29/739 , H01L29/74 , H01L29/745 , H01L29/749 , H01L29/78 , H01L29/786 , H01L29/861
CPC分类号： H01L29/7824 , H01L21/74 , H01L21/76264 , H01L21/76297 , H01L27/0623 , H01L27/0922 , H01L27/1203 , H01L29/404 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/66772 , H01L29/7394 , H01L29/7436 , H01L29/7455 , H01L29/749 , H01L29/7835 , H01L29/78624 , H01L29/8611 , H01L21/76275 , H01L21/76286 , H01L29/402
摘要： A high breakdown voltage semiconductor device is disclosed which comprises a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a first semiconductor region formed on the first insulating layer and isolated at its side by an isolating region, a second semiconductor region of a first conductivity type formed in a surface portion of the first semiconductor region and having a higher impurity concentration than that of the first semiconductor region, a third semiconductor region of a second conductivity type formed in the surface region of the first semiconductor region such that it is located between the second semiconductor region and the isolating region in a manner to be spaced apart from the second semiconductor region, the third semiconductor region having a higher impurity concentration than that of the first semiconductor region.
摘要翻译：公开了一种高耐压电压半导体器件，其包括半导体衬底，形成在半导体衬底上的绝缘层，形成在第一绝缘层上并通过隔离区隔离的第一半导体区域，第一半导体区域导电型形成在第一半导体区域的表面部分中并且具有比第一半导体区域的杂质浓度高的第二导电类型的第三半导体区域，形成在第一半导体区域的表面区域中，使得其位于在第二半导体区域和隔离区域之间以与第二半导体区域间隔开的方式，第三半导体区域的杂质浓度高于第一半导体区域。

64. 发明申请

US20100096696A1 SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTOR FOR USE AS A HIGH-SPEED SWITCHING DEVICE AND A POWER DEVICE 有权
标题翻译：包括用作高速开关器件和功率器件的场效应晶体管的半导体器件
公开(公告)号：US20100096696A1
公开(公告)日：2010-04-22
申请号：US12645072
申请日：2009-12-22
申请人： Yusuke Kawaguchi , Norio Yasuhara , Tomoko Matsudai , Kenichi Matsushita
发明人： Yusuke Kawaguchi , Norio Yasuhara , Tomoko Matsudai , Kenichi Matsushita
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.
摘要翻译：在半导体衬底上形成第一导电类型的主体层，并且在主体层的表面区域中形成第二导电类型的源极层。第二导电类型的偏移层形成在半导体衬底上，并且第二导电类型的漏极层形成在偏移层的表面区域中。绝缘膜嵌入形成在源极层和漏极层之间的偏移层的表面区域中的沟槽中。在主体层和源极层与绝缘膜之间的偏移层上形成栅极绝缘膜。在栅极绝缘膜上形成栅电极。偏移层中的杂质浓度分布的第一峰形成在比绝缘膜更深的位置。

65. 发明授权

US07692242B2 Semiconductor device used as high-speed switching device and power device 失效
标题翻译：半导体器件用作高速开关器件和功率器件
公开(公告)号：US07692242B2
公开(公告)日：2010-04-06
申请号：US11505337
申请日：2006-08-17
申请人： Tomoko Matsudai , Norio Yasuhara , Yusuke Kawaguchi , Kenichi Matsushita
发明人： Tomoko Matsudai , Norio Yasuhara , Yusuke Kawaguchi , Kenichi Matsushita
IPC分类号： H01L29/04 , H01L29/06
CPC分类号： H01L29/1045 , H01L21/26586 , H01L29/1083 , H01L29/1087 , H01L29/66659 , H01L29/7835 , H01L29/7838
摘要： A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.
摘要翻译：在半导体衬底上形成低电阻层，形成在低电阻层上的高电阻层。第一导电类型的源区形成在高电阻层的表面区域上。第一导电类型的漏极区域形成在与源极区域一定距离处。在源极区域和漏极区域之间的高电阻层的表面区域中形成第一导电类型的第一再结晶区域。在源极区域和第一再结晶区域之间形成第二导电类型的沟道区域。栅极绝缘膜形成在沟道区上，栅极形成在栅极绝缘膜上。栅电极下方的沟道区域中的杂质浓度从源极区域朝向第一再结晶区域逐渐降低。

66. 发明授权

US07589389B2 Semiconductor device and method of manufacturing the same 失效
公开(公告)号：US07589389B2
公开(公告)日：2009-09-15
申请号：US12264580
申请日：2008-11-04
申请人： Tomoko Matsudai , Norio Yasuhara
发明人： Tomoko Matsudai , Norio Yasuhara
IPC分类号： H01L23/58
CPC分类号： H01L29/7816 , H01L29/063 , H01L29/0878 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/66681 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprising: a base layer of a first conductivity type selectively formed above a semiconductor substrate; a gate electrode formed on the base layer via the insulating film; a source layer of a second conductivity type selectively formed at a surface of the base layer at one side of the gate electrode; an channel implantation layer selectively formed at the surface of the base layer so as to be adjacent to the source layer below the gate electrode, the channel implantation layer having a higher concentration than the base layer; a RESURF layer of the second conductivity type selectively formed at the surface of the base layer at the other side of the gate electrode; and a drain layer of a second conductivity type being adjacent to the RESURF layer, a portion of the drain layer overlapping the base layer, and the drain layer having a higher concentration than the RESURF layer.

67. 发明授权

US07473978B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US07473978B2
公开(公告)日：2009-01-06
申请号：US11502387
申请日：2006-08-11
申请人： Tomoko Matsudai , Norio Yasuhara
发明人： Tomoko Matsudai , Norio Yasuhara
IPC分类号： H01L23/58
CPC分类号： H01L29/7816 , H01L29/063 , H01L29/0878 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/66681 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprising: a base layer of a first conductivity type selectively formed above a semiconductor substrate; a gate electrode formed on the base layer via the insulating film; a source layer of a second conductivity type selectively formed at a surface of the base layer at one side of the gate electrode; an channel implantation layer selectively formed at the surface of the base layer so as to be adjacent to the source layer below the gate electrode, the channel implantation layer having a higher concentration than the base layer; a RESURF layer of the second conductivity type selectively formed at the surface of the base layer at the other side of the gate electrode; and a drain layer of a second conductivity type being adjacent to the RESURF layer, a portion of the drain layer overlapping the base layer, and the drain layer having a higher concentration than the RESURF layer.
摘要翻译：一种半导体器件，包括：选择性地形成在半导体衬底之上的第一导电类型的基极层; 经由所述绝缘膜形成在所述基底层上的栅电极; 选择性地形成在所述基极层的所述栅电极的一侧的表面处的第二导电类型的源极层; 沟道注入层，其选择性地形成在所述基底层的表面处以与所述栅极电极下方的源极层相邻，所述沟道注入层具有比所述基底层更高的浓度; 所述第二导电类型的RESURF层选择性地形成在所述基极层的所述栅极电极的另一侧的表面处; 以及与RESURF层相邻的第二导电类型的漏极层，所述漏极层的一部分与所述基极层重叠，并且所述漏极层具有比所述RESURF层更高的浓度。

68. 发明申请

US20070034985A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070034985A1
公开(公告)日：2007-02-15
申请号：US11502387
申请日：2006-08-11
申请人： Tomoko Matsudai , Norio Yasuhara
发明人： Tomoko Matsudai , Norio Yasuhara
IPC分类号： H01L23/58
CPC分类号： H01L29/7816 , H01L29/063 , H01L29/0878 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/66681 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprising: a base layer of a first conductivity type selectively formed above a semiconductor substrate; a gate electrode formed on the base layer via the insulating film; a source layer of a second conductivity type selectively formed at a surface of the base layer at one side of the gate electrode; an channel implantation layer selectively formed at the surface of the base layer so as to be adjacent to the source layer below the gate electrode, the channel implantation layer having a higher concentration than the base layer; a RESURF layer of the second conductivity type selectively formed at the surface of the base layer at the other side of the gate electrode; and a drain layer of a second conductivity type being adjacent to the RESURF layer, a portion of the drain layer overlapping the base layer, and the drain layer having a higher concentration than the RESURF layer.
摘要翻译：一种半导体器件，包括：选择性地形成在半导体衬底之上的第一导电类型的基极层; 经由所述绝缘膜形成在所述基底层上的栅电极; 选择性地形成在所述基极层的所述栅电极的一侧的表面处的第二导电类型的源极层; 沟道注入层，其选择性地形成在所述基底层的表面处以与所述栅极电极下方的源极层相邻，所述沟道注入层具有比所述基底层更高的浓度; 所述第二导电类型的RESURF层选择性地形成在所述基极层的所述栅极电极的另一侧的表面处; 以及与RESURF层相邻的第二导电类型的漏极层，所述漏极层的一部分与所述基极层重叠，并且所述漏极层具有比所述RESURF层更高的浓度。

69. 发明授权

US07061048B2 Power MOSFET device 失效
公开(公告)号：US07061048B2
公开(公告)日：2006-06-13
申请号：US10790137
申请日：2004-03-02
申请人： Yusuke Kawaguchi , Norio Yasuhara , Syotaro Ono , Shinichi Hodama , Akio Nakagawa
发明人： Yusuke Kawaguchi , Norio Yasuhara , Syotaro Ono , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L27/96
CPC分类号： H01L21/26513 , H01L29/04 , H01L29/0653 , H01L29/0847 , H01L29/0878 , H01L29/1045 , H01L29/1095 , H01L29/41 , H01L29/4175 , H01L29/42372 , H01L29/42376 , H01L29/66659 , H01L29/66712 , H01L29/7802 , H01L29/7835
摘要： A power MOSFET device comprising a low resistance substrate of the first conductivity type, a high resistance epitaxial layer of the first conductivity type formed on the low resistance substrate, a base layer of the second conductivity type formed in a surface region of the high resistance epitaxial layer, a source region of the first conductivity type formed in a surface region of the base layer, a gate insulating film formed on the surface of the base layer so as to contact the source region, a gate electrode formed on the gate insulating film, and an LDD layer of the first conductivity type formed on the surface of the high resistance epitaxial layer oppositely relative to the source region and the gate electrode, wherein the LDD layer and the low resistance substrate are connected to each other by the high resistance epitaxial layer.

70. 发明授权

US5985708A Method of manufacturing vertical power device 失效
标题翻译：垂直功率器件的制造方法
公开(公告)号：US5985708A
公开(公告)日：1999-11-16
申请号：US816596
申请日：1997-03-13
申请人： Akio Nakagawa , Naoharu Sugiyama , Tomoko Matsudai , Norio Yasuhara , Atsusi Kurobe , Hideyuki Funaki , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Akio Nakagawa , Naoharu Sugiyama , Tomoko Matsudai , Norio Yasuhara , Atsusi Kurobe , Hideyuki Funaki , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L27/12 , H01L29/73 , H01L29/739 , H01L29/786 , H01L21/8249
CPC分类号： H01L29/78696 , H01L27/1203 , H01L29/7317 , H01L29/7394 , H01L29/78612 , H01L29/78624 , H01L29/78639 , H01L29/78645 , H01L29/78687
摘要： A semiconductor apparatus comprising a vertical type semiconductor device having a first conducting type semiconductor substrate, a drain layer formed on the surface of the semiconductor substrate, a drain electrode formed on the surface of the drain layer, a second conducting type base layer selectively formed on the surface of the semiconductor substrate opposite to the drain layer, a first conducting type source layer selectively formed on the surface of the second conducting type base layer, a source electrode formed on the first conducting type source layer and the second conducting type base layer, and a gate electrode formed in contact with the first conducting type source layer, the second conducting type base layer and the semiconductor substrate through a gate insulating film and a lateral semiconductor device having an insulating layer formed in a region of the surface of the semiconductor substrate different from the second conducting type base layer, and a polycrystalline semiconductor layer formed on the insulating layer and having a first conducting type region and a second conducting type region, wherein the first conducting type source layer of the vertical semiconductor device and the first conducting type region of the polycrystalline semiconductor layer are simultaneously formed.
摘要翻译：一种半导体装置，包括具有第一导电型半导体衬底的垂直型半导体器件，形成在半导体衬底的表面上的漏极层，形成在漏极层的表面上的漏电极，第二导电型基极层，所述半导体衬底的与所述漏极层相对的表面，选择性地形成在所述第二导电型基极层的表面上的第一导电型源极层，形成在所述第一导电型源极层和所述第二导电型基极层上的源电极，以及通过栅极绝缘膜与第一导电型源极层，第二导电型基极层和半导体基板接触形成的栅电极，以及在半导体基板的表面的区域中形成有绝缘层的侧面半导体装置不同于第二导电型基底层，和多晶半导体层形成在绝缘层上并具有第一导电类型区域和第二导电类型区域，其中垂直半导体器件的第一导电型源极层和多晶半导体层的第一导电类型区域同时形成。

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