专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US07848143B2 Memory controller controlling semiconductor storage device and semiconductor device 失效
标题翻译：存储控制器控制半导体存储器件和半导体器件
公开(公告)号：US07848143B2
公开(公告)日：2010-12-07
申请号：US12687915
申请日：2010-01-15
申请人： Shinichi Kanno , Yosuke Kuroda , Toshio Shirakihara
发明人： Shinichi Kanno , Yosuke Kuroda , Toshio Shirakihara
IPC分类号： G11C16/00
CPC分类号： G11C16/3418
摘要： A memory controller controls a semiconductor storage device including nonvolatile memory cells. The controller includes a generating circuit, and a selection circuit. The generating circuit generates first data based on a second data. The selection circuit retains a cumulative value whose each digit is a cumulative result in each bit of data which is already written in the memory cells. The selection circuit selects one of the first data. A selected first data has a better average of digits in a sum of each bit of the selected first data and each digit of the cumulative value than an unselected first data. The selection circuit retains the sum concerning the selected first data as the new cumulative value.
摘要翻译：存储器控制器控制包括非易失性存储单元的半导体存储器件。控制器包括发生电路和选择电路。生成电路基于第二数据生成第一数据。选择电路保留累积值，其每个数字是已经写入存储器单元的每个数据位的累积结果。选择电路选择第一数据之一。所选择的第一数据在所选择的第一数据的每一比特和累积值的每个数字之和与未选择的第一数据的和中具有更好的数字平均。选择电路将与所选择的第一数据相关的和保持为新的累积值。

62. 发明授权

US07644297B2 Processor, control device for a processor, clock frequency determining method and source voltage controlling method of a processor 失效
标题翻译：处理器，处理器的控制装置，处理器的时钟频率确定方法和源电压控制方法
公开(公告)号：US07644297B2
公开(公告)日：2010-01-05
申请号：US11819417
申请日：2007-06-27
申请人： Masaya Tarui , Shinichi Kanno
发明人： Masaya Tarui , Shinichi Kanno
IPC分类号： G06F1/04 , G06F1/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A processor comprises a clock signal generator generating clock signals; an operational processing part performing data processing which is divided into a plurality of execution units, in accordance with the clock signals; a storage storing data used when each execution unit is executed by the operational processing part; a data amount detector detecting amounts of the data stored in the storage per each execution unit; a clock frequency determining part determining a new clock frequency of the clock signals by using the amounts of the data, said clock signals being supplied newly to the operational processing part.
摘要翻译：处理器包括产生时钟信号的时钟信号发生器; 操作处理部分，根据所述时钟信号执行被分成多个执行单元的数据处理; 当由所述操作处理部执行每个执行单元时使用的存储数据的存储器; 数据量检测器，检测每个执行单元存储在存储器中的数据量; 时钟频率确定部分，通过使用所述数据量确定所述时钟信号的新时钟频率，所述时钟信号被新近提供给所述操作处理部分。

63. 发明授权

US07496811B2 Storage medium reproducing apparatus, storage medium reproducing method, and computer program product for reading information from storage medium 失效
标题翻译：存储介质再现装置，存储介质再现方法和用于从存储介质读取信息的计算机程序产品
公开(公告)号：US07496811B2
公开(公告)日：2009-02-24
申请号：US11360604
申请日：2006-02-24
申请人： Shinichi Kanno
发明人： Shinichi Kanno
IPC分类号： G11C29/00
CPC分类号： G11B20/1833 , G11B20/18 , G11B27/36
摘要： A storage medium reproducing apparatus includes a storage unit, a correction history storage unit, a correction history implementing unit, and a correcting unit. The storage unit includes a plurality of information storage units storing information depending on whether a charge quantity is greater than a predetermined charge quantity threshold value, and a correction code storage unit storing error correction codes for the information stored in the information storage units. The correction history storage unit stores a correction history containing identification information for the information storage unit corrected with an error correction code is performed, and a content of the correction. The correction history implementing unit corrects information in compliance with the content of the correction when the information is read from the information storage unit. The correcting unit performs a correcting operation using an error correction code on the corrected information, and registers the correction history of the corrected information storage unit.
摘要翻译：存储介质再现装置包括存储单元，校正历史存储单元，校正历史实现单元和校正单元。存储单元包括多个信息存储单元，其存储取决于计费量是否大于预定电荷量阈值的信息;以及校正码存储单元，存储存储在信息存储单元中的信息的纠错码。校正历史存储单元存储包含用纠错码校正的信息存储单元的识别信息的校正历史，以及校正的内容。当从信息存储单元读取信息时，校正历史实现单元根据校正的内容校正信息。校正单元使用校正信息上的纠错码执行校正操作，并且登记校正信息存储单元的校正历史。

64. 发明授权

US07330985B2 Logic circuit system and method of changing operating voltage of a programmable logic circuit 失效
标题翻译：逻辑电路系统和可编程逻辑电路的工作电压变化方法
公开(公告)号：US07330985B2
公开(公告)日：2008-02-12
申请号：US10960707
申请日：2004-10-08
申请人： Taku Ohneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto
发明人： Taku Ohneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3243 , G06F1/3296 , H03K19/0008 , H03K19/0016 , H03K19/1736 , H03K19/17752 , H03K19/17756 , H03K19/17784 , H03K19/17788 , Y02D10/126 , Y02D10/152 , Y02D10/172
摘要： A logic circuit system with power consumption that is reduced by automatically varying the clock frequency and operating voltage according to processing capability imposed on programmable logic circuits. The programmable logic circuits are capable of achieving plural circuit functions dynamically and can change realized circuit functions during operation. In addition, the system has a voltage supply portion for supplying a voltage to the programmable logic circuits, a clock signal supply portion for supplying a clock signal to the programmable logic circuits, a change control portion for changing the circuit functions realized by the programmable logic circuits to any one of the circuit functions, an operation time measuring portion for measuring the operation times of the programmable logic circuits to perform processing to achieve the circuit functions, respectively, and a clock-and-voltage determination portion for determining the frequency of the clock signal and the voltage, using the operation times.
摘要翻译：通过根据施加在可编程逻辑电路上的处理能力自动改变时钟频率和工作电压，降低功耗的逻辑电路系统。可编程逻辑电路能够动态地实现多个电路功能，并且可以在操作期间改变实现的电路功能。此外，该系统具有用于向可编程逻辑电路提供电压的电压供应部分，用于向可编程逻辑电路提供时钟信号的时钟信号提供部分，用于改变可编程逻辑实现的电路功能的改变控制部分电路中的任何一个电路功能，操作时间测量部分，用于分别测量可编程逻辑电路的操作时间以执行分别执行电路功能的处理;以及时钟和电压确定部分，用于确定时钟信号和电压，使用操作时间。

65. 发明申请

US20070174740A1 APPARATUS, METHOD AND COMPUTER PROGRAM PRODUCT FOR READING INFORMATION STORED IN STORAGE MEDIUM 有权
标题翻译：存储介质中存储信息的装置，方法和计算机程序产品
公开(公告)号：US20070174740A1
公开(公告)日：2007-07-26
申请号：US11531963
申请日：2006-09-14
申请人： Shinichi Kanno
发明人： Shinichi Kanno
IPC分类号： G06F11/00
CPC分类号： G06F11/1072 , G06F11/1068 , G11C11/5642 , G11C29/00 , G11C2029/0411 , G11C2211/5634
摘要： An apparatus for reproducing information includes a memory unit which stores charge; a reading unit which obtains an amount of the charge stored in the memory unit, and reads information by determining a value based on a comparison of the amount of the charge with a first threshold; an error detection unit which determines whether the information read has an error; and a threshold generation unit which generates a second threshold having a value different from that of the first threshold used in reading the information, when the error detection unit determines that the information has an error, wherein the reading unit further reads the information by determining a value based on a comparison of the amount of the charge with the second threshold after the error detection unit determines that the information has the error.
摘要翻译：一种用于再现信息的装置包括：存储单元，其存储电荷; 读取单元，其获取存储在存储单元中的电荷量，并且通过基于电荷量与第一阈值的比较来确定值来读取信息; 错误检测单元，其确定读取的信息是否具有错误; 以及阈值生成单元，当所述错误检测单元确定所述信息具有错误时，生成具有与用于读取所述信息的所述第一阈值不同的值的第二阈值，其中所述读取单元还通过确定所述信息来读取所述信息基于在错误检测单元确定信息具有错误之后的电荷量与第二阈值的比较的值。

66. 发明授权

US07180934B2 Radio communicating apparatus, radio communicating method, and recording medium 失效
标题翻译：无线电通信装置，无线电通信方法和记录介质
公开(公告)号：US07180934B2
公开(公告)日：2007-02-20
申请号：US10782872
申请日：2004-02-23
申请人： Hiroshi Yoshida , Shinichi Kanno , Takeshi Tomizawa , Minoru Namekata , Hiroshi Tsurumi , Yuzo Tamada
发明人： Hiroshi Yoshida , Shinichi Kanno , Takeshi Tomizawa , Minoru Namekata , Hiroshi Tsurumi , Yuzo Tamada
IPC分类号： H04L5/16
CPC分类号： H04B1/0003 , H04B1/406
摘要： A library is referred to and thus facilities are executed when executing an application program for receiving and transmitting radio signals. That is, the library serving as programs depending on hardware converts commands based on the application program into signal to control the hardware. As a result, the application program is describable by a program independent of an analog device for receiving and transmitting the radio signal, and a common application program can be used even in case of different hardware.
摘要翻译：参考图书馆，因此在执行用于接收和发送无线电信号的应用程序时执行设施。也就是说，作为依赖于硬件的程序的库将基于应用程序的命令转换为信号以控制硬件。结果，可以通过独立于用于接收和发送无线电信号的模拟设备的程序来描述应用程序，并且即使在不同的硬件的情况下也可以使用通用的应用程序。

67. 发明授权

US06741639B1 Radio communicating apparatus radio communicating method and recording medium 失效
标题翻译：无线电通信装置无线电通信方法和记录介质
公开(公告)号：US06741639B1
公开(公告)日：2004-05-25
申请号：US09466929
申请日：1999-12-20
申请人： Hiroshi Yoshida , Shinichi Kanno , Takeshi Tomizawa , Minoru Namekata , Hiroshi Tsurumi , Yuzo Tamada
发明人： Hiroshi Yoshida , Shinichi Kanno , Takeshi Tomizawa , Minoru Namekata , Hiroshi Tsurumi , Yuzo Tamada
IPC分类号： H04L1516
CPC分类号： H04B1/0003 , H04B1/406
摘要： A library is referred to and thus facilities are executed when executing an application program for receiving and transmitting radio signals. That is, the library serving as programs depending on hardware converts commands based on the application program into signal to control the hardware. As a result, the application program is describable by a program independent of an analog device for receiving and transmitting the radio signal, and a common application program can be used even in case of different hardware.
摘要翻译：参考图书馆，因此在执行用于接收和发送无线电信号的应用程序时执行设施。也就是说，作为依赖于硬件的程序的库将基于应用程序的命令转换为信号以控制硬件。结果，可以通过独立于用于接收和发送无线电信号的模拟设备的程序来描述应用程序，并且即使在不同的硬件的情况下也可以使用通用的应用程序。

68. 发明授权

US09164831B2 Memory controller, semiconductor storage device, and decoding method 有权
标题翻译：存储器控制器，半导体存储器件和解码方法
公开(公告)号：US09164831B2
公开(公告)日：2015-10-20
申请号：US14234856
申请日：2012-03-14
申请人： Koji Horisaki , Toshikatsu Hida , Shinichi Kanno , Osamu Torii
发明人： Koji Horisaki , Toshikatsu Hida , Shinichi Kanno , Osamu Torii
IPC分类号： H03M13/00 , G06F11/10 , H03M13/15
CPC分类号： G06F11/1044 , G06F11/1048 , H03M13/1575
摘要： According to an embodiment, a memory interface that includes n number of channels and writes data subjected to an error correction encoding process having capable of correcting t symbols, n number of first error correction decoding units that perform an error correction decoding process of correcting s (s
摘要翻译：根据实施例，一种存储器接口，其包括n个通道并且写入经过可纠正t个符号的纠错编码处理的数据，n个第一纠错解码单元执行纠错解码处理 s

69. 发明申请

US20140173377A1 MEMORY CONTROLLER, SEMICONDUCTOR STORAGE DEVICE, AND DECODING METHOD 有权
标题翻译：存储器控制器，半导体存储器件和解码方法
公开(公告)号：US20140173377A1
公开(公告)日：2014-06-19
申请号：US14234856
申请日：2012-03-14
申请人： Koji Horisaki , Toshikatsu Hida , Shinichi Kanno , Osamu Torii
发明人： Koji Horisaki , Toshikatsu Hida , Shinichi Kanno , Osamu Torii
IPC分类号： G06F11/10
CPC分类号： G06F11/1044 , G06F11/1048 , H03M13/1575
摘要： According to an embodiment, a memory interface that includes n number of channels and writes data subjected to an error correction encoding process having capable of correcting t symbols, n number of first error correction decoding units that perform an error correction decoding process of correcting s (s
摘要翻译：根据实施例，一种存储器接口，其包括n个通道并且写入经过可纠正t个符号的纠错编码处理的数据，n个第一纠错解码单元执行纠错解码处理 s

70. 发明授权

US08219861B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08219861B2
公开(公告)日：2012-07-10
申请号：US13270788
申请日：2011-10-11
申请人： Toshikatsu Hida , Shinichi Kanno , Hirokuni Yano , Kazuya Kitsunai , Shigehiro Asano , Junji Yano
发明人： Toshikatsu Hida , Shinichi Kanno , Hirokuni Yano , Kazuya Kitsunai , Shigehiro Asano , Junji Yano
IPC分类号： G11C29/00
CPC分类号： G06F11/1412 , G06F11/1068 , G06F11/1402 , G06F12/02 , G11C16/0483 , G11C16/3418 , G11C16/3431
摘要： As a semiconductor storage device that can efficiently perform a refresh operation, provided is a semiconductor storage device comprising a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing, and a controlling unit monitoring an error count of data stored in a monitored block selected from the blocks and refreshing data in the monitored block in which the error count is equal to or larger than a threshold value.
摘要翻译：作为可以有效地执行刷新操作的半导体存储装置，提供了一种半导体存储装置，其包括以块为单位存储数据的非易失性半导体存储器，该块是数据擦除单元，以及监视数据的错误计数的控制单元存储在从所述块中选择的监视块和所述监视块中的刷新数据中，其中所述错误计数等于或大于阈值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式