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61. 发明授权

US08193575B2 Flash memory structure with enhanced capacitive coupling coefficient ratio (CCCR) and method for fabrication thereof 失效
标题翻译：具有增强的电容耦合系数比（CCCR）的闪存结构及其制造方法
公开(公告)号：US08193575B2
公开(公告)日：2012-06-05
申请号：US12027496
申请日：2008-02-07
申请人： Louis C. Hsu , Xu Ouyang , Ping-Chuan Wang , Zhijian J. Yang
发明人： Louis C. Hsu , Xu Ouyang , Ping-Chuan Wang , Zhijian J. Yang
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/7881
摘要： A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.
摘要翻译：具有增强的电容耦合系数比（CCCR）的闪速存储器结构可以以自对准方式制造，同时使用半导体衬底，该半导体衬底具有相对于围绕有源区域的隔离区域在孔内凹入的有源区域。闪速存储器结构包括不在隔离区上方升起的浮栅，并且优选地由具有U形的单层组成。 U形有助于增强电容耦合系数比。

62. 发明授权

US08159814B2 Method of operating transistors and structures thereof for improved reliability and lifetime 有权
标题翻译：操作晶体管及其结构的方法，以提高可靠性和寿命
公开(公告)号：US08159814B2
公开(公告)日：2012-04-17
申请号：US12355815
申请日：2009-01-19
申请人： Ping-Chuan Wang , Zhijian Yang , Fernando J. Guarin , J. Edwin Hostetter , Kai D Feng
发明人： Ping-Chuan Wang , Zhijian Yang , Fernando J. Guarin , J. Edwin Hostetter , Kai D Feng
IPC分类号： H01G7/02 , G01R31/04
CPC分类号： H01L23/345 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present invention provide a semiconductor device that includes a transistor device having a first, a second, and a third node; and an interconnect structure having at least one wire and the wire having a first and a second end with the first end of the wire being connected to one of the first, the second, and the third node of the transistor device. The wire is conductive and adapted to provide an operating current in a first direction during a normal operating mode, and adapted to provide a repairing current in a second direction opposite to the first direction during a repair mode of the semiconductor device. In one embodiment the transistor device is a bipolar transistor with the first, second, and third nodes being an emitter, a base, and a collector of the bipolar transistor. The wire is connected to one of the emitter and the collector. Method of operating the semiconductor device and current supplying circuit for the semiconductor device are also disclosed.
摘要翻译：本发明的实施例提供一种半导体器件，其包括具有第一，第二和第三节点的晶体管器件; 以及具有至少一根导线的互连结构，并且所述导线具有第一和第二端，所述导线的第一端连接到晶体管器件的第一，第二和第三节点之一。导线是导电的并且适于在正常操作模式期间在第一方向上提供工作电流，并且适于在半导体器件的修复模式期间在与第一方向相反的第二方向上提供修复电流。在一个实施例中，晶体管器件是双极晶体管，其中第一，第二和第三节点是双极晶体管的发射极，基极和集电极。导线连接到发射极和集电极之一。还公开了用于半导体器件的半导体器件和电流供应电路的操作方法。

63. 发明授权

US08138083B2 Interconnect structure having enhanced electromigration reliability and a method of fabricating same 有权
标题翻译：具有增强的电迁移可靠性的互连结构及其制造方法
公开(公告)号：US08138083B2
公开(公告)日：2012-03-20
申请号：US12534478
申请日：2009-08-03
申请人： Chih-Chao Yang , Ping-Chuan Wang , Yun-Yu Wang
发明人： Chih-Chao Yang , Ping-Chuan Wang , Yun-Yu Wang
IPC分类号： H01L21/768
CPC分类号： H01L21/76847 , H01L23/5226 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure having improved electromigration (EM) reliability is provided. The inventive interconnect structure avoids a circuit dead opening that is caused by EM failure by incorporating a EM preventing liner at least partially within a metal interconnect. In one embodiment, a “U-shaped” EM preventing liner is provided that abuts a diffusion barrier that separates conductive material from the dielectric material. In another embodiment, a space is located between the “U-shaped” EM preventing liner and the diffusion barrier. In yet another embodiment, a horizontal EM liner that abuts the diffusion barrier is provided. In yet a further embodiment, a space exists between the horizontal EM liner and the diffusion barrier.
摘要翻译：提供了具有改进的电迁移（EM）可靠性的互连结构。本发明的互连结构避免了通过将至少部分地在金属互连内部结合EM防止衬垫而由EM故障引起的电路死路。在一个实施例中，提供了一种“U形”防EM衬垫，其与导电材料与电介质材料分离的扩散屏障相邻。在另一个实施例中，空间位于“U形”EM防护衬垫和扩散阻挡层之间。在另一个实施例中，提供了一个与扩散阻挡件相邻的水平EM衬垫。在又一个实施例中，在水平EM衬垫和扩散阻挡层之间存在一个空间。

64. 发明授权

US07961032B1 Method of and structure for recovering gain in a bipolar transistor 有权
标题翻译：双极晶体管中恢复增益的方法和结构
公开(公告)号：US07961032B1
公开(公告)日：2011-06-14
申请号：US12627282
申请日：2009-11-30
申请人： Zhijian Yang , Ping-Chuan Wang , Kai Di Feng
发明人： Zhijian Yang , Ping-Chuan Wang , Kai Di Feng
IPC分类号： H03K17/60
CPC分类号： H03F1/302
摘要： A method of recovering gain in a bipolar transistor includes: providing a bipolar transistor including an emitter, a collector, and a base disposed between junctions at the emitter and the collector; reverse biasing the junction disposed between the emitter and the base with an operational voltage and for an operational time period, so that a current gain β of the transistor is degraded; idling the transistor, and generating a repair current Ibr into the base, while forward biasing the junction disposed between the emitter and the base with a first repair voltage (VEBR), and while at least partly simultaneously reverse biasing the junction disposed between the collector and the base with a second repair voltage (VCBR), for a repair time period (TR), so that the gain is at least party recovered; wherein VEBR, VCBR and TR have the proportional relationship: TR ∝ (Δβ)2×exp [1/(Tam+Rth×le×VCER)], VCER=VBER+VCBR, and le=β×Ibr, β is the normal current gain of the transistor, Δβ is the target recovery gain of the transistor in percentage, Tam is the ambient temperature in degrees K, Ibr is the repair current to the base in μamps, Rth is the self-heating thermal resistance of the transistor in K/W, TR is in seconds. The invention further includes structures for implementing the method.
摘要翻译：一种在双极晶体管中恢复增益的方法，包括：提供一个包括发射极，集电极和设置在发射极和集电极之间的结之间的基极的双极晶体管; 使用工作电压和工作时间周期反向偏置设置在发射极和基极之间的结，使得电流增益＆bgr; 的晶体管劣化; 使晶体管怠速，并产生修复电流Ibr到基极，同时以第一修复电压（VEBR）向前偏置设置在发射极和基极之间的结，并且至少部分地同时反向偏置设置在集电极和具有第二修复电压（VCBR）的基座，用于修复时间段（TR），使得增益至少被回收; 其中VEBR，VCBR和TR具有比例关系：TRα（＆Dgr;＆bgr;）2×exp [1 /（Tam + Rth×le×VCER）]，VCER = VBER + VCBR，和le =＆bgr;×Ibr，＆bgr 是晶体管的正常电流增益，＆Dgr; 是晶体管的目标恢复增益百分比，谭是以K为单位的环境温度，Ibr是以μ为单位的基极修复电流，Rth是晶体管的自热热阻，K / W，TR在秒。本发明还包括用于实现该方法的结构。

65. 发明授权

US07919834B2 Edge seal for thru-silicon-via technology 有权
标题翻译：通过硅通孔技术的边缘密封
公开(公告)号：US07919834B2
公开(公告)日：2011-04-05
申请号：US11949986
申请日：2007-12-04
申请人： Robert Edgar Davis , Robert Daniel Edwards , J. Edwin Hostetter, Jr. , Ping-Chuan Wang , Kimball M. Watson
发明人： Robert Edgar Davis , Robert Daniel Edwards , J. Edwin Hostetter, Jr. , Ping-Chuan Wang , Kimball M. Watson
IPC分类号： H01L29/40 , H01L23/04
CPC分类号： H01L21/76898 , H01L21/6835 , H01L21/76852 , H01L23/481 , H01L24/02 , H01L24/11 , H01L24/12 , H01L24/27 , H01L24/28 , H01L24/94 , H01L2221/68331 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/13099 , H01L2224/274 , H01L2924/0002 , H01L2924/01006 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2224/05552
摘要： One or more multilayer back side metallurgy (BSM) stack structures are formed on thru-silicon-vias (TSV). The multiple layers of metal may include an adhesion layer of chromium on the semiconductor wafer back side, a conductive layer of copper, diffusion barrier layer of nickel and a layer of nobel metal, such as, gold. To prevent edge attack of copper after dicing, the layer of nickel is formed to seal the copper edge. To also prevent edge attack of the layer of nickel after dicing, the layer of gold is formed to seal both the layer of copper and the layer of nickel.
摘要翻译：在硅通孔（TSV）上形成一个或多个多层背面冶金（BSM）堆叠结构。多层金属可以包括在半导体晶片背面上的铬的粘合层，铜的导电层，镍的扩散阻挡层和诸如金的诺贝尔金属层。为了防止切割后铜的边缘侵蚀，形成镍层以密封铜边缘。为了防止切割后镍层的边缘侵蚀，形成金层以密封铜层和镍层。

66. 发明申请

US20110073858A1 Test Structure for Determination of TSV Depth 有权
标题翻译：测定TSV深度的测试结构
公开(公告)号：US20110073858A1
公开(公告)日：2011-03-31
申请号：US12566726
申请日：2009-09-25
申请人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
发明人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H01L23/48 , H01L21/66
CPC分类号： H01L22/34 , H01L21/76898
摘要： A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel. A method of determining a depth of a through-silicon-via (TSV) in a semiconductor chip includes etching a first TSV into the semiconductor chip; forming a first channel, the first channel comprising the first TSV, a first contact electrically connected to the first TSV, and a second contact; connecting a current source to the second contact; determining a resistance across the first channel; and determining a depth of the first TSV based on the resistance of the first channel.
摘要翻译：半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。确定半导体芯片中的硅通孔（TSV）的深度的方法包括将第一TSV蚀刻到半导体芯片中; 形成第一通道，所述第一通道包括第一TSV，电连接到第一TSV的第一触点和第二触点; 将电流源连接到第二触点; 确定跨越第一通道的电阻; 以及基于所述第一通道的电阻确定所述第一TSV的深度。

67. 发明授权

US07904273B2 In-line depth measurement for thru silicon via 有权
标题翻译：通过硅通孔的在线深度测量
公开(公告)号：US07904273B2
公开(公告)日：2011-03-08
申请号：US12371724
申请日：2009-02-16
申请人： Qizhi Liu , Ping-Chuan Wang , Kimball M. Watson , Zhijian J. Yang
发明人： Qizhi Liu , Ping-Chuan Wang , Kimball M. Watson , Zhijian J. Yang
IPC分类号： G06F19/00
CPC分类号： H01L22/34 , H01L2924/3011
摘要： A system, method and device for measuring a depth of a Through-Silicon-Via (TSV) in a semiconductor device region on a wafer during in-line semiconductor fabrication, includes a resistance measurement trench structure having length and width dimensions in a substrate, ohmic contacts on a surface of the substrate disposed on opposite sides of the resistance measurement trench structure, and an unfilled TSV structure in semiconductor device region having an unknown depth. A testing circuit makes contact with the ohmic contacts and measures a resistance therebetween, and a processor connected to the testing circuit calculates a depth of the trench structure and the unfilled TSV structure based on the resistance measurement. The resistance measurement trench structure and the unfilled TSV are created simultaneously during fabrication.
摘要翻译：在线半导体制造期间，用于测量晶片上的半导体器件区域中的硅硅通孔（TSV）的深度的系统，方法和装置包括在衬底中具有长度和宽度尺寸的电阻测量沟槽结构，设置在电阻测量沟槽结构的相对侧的衬底的表面上的欧姆接触，以及具有未知深度的半导体器件区域中的未填充的TSV结构。测试电路与欧姆接触件接触并测量它们之间的电阻，连接到测试电路的处理器基于电阻测量来计算沟槽结构的深度和未填充的TSV结构。在制造期间同时产生电阻测量沟槽结构和未填充TSV。

68. 发明授权

US07861204B2 Structures including integrated circuits for reducing electromigration effect 有权
标题翻译：包括用于降低电迁移效应的集成电路的结构
公开(公告)号：US07861204B2
公开(公告)日：2010-12-28
申请号：US11960853
申请日：2007-12-20
申请人： Anthony Kendall Stamper , Timothy Dooling Sullivan , Ping-Chuan Wang
发明人： Anthony Kendall Stamper , Timothy Dooling Sullivan , Ping-Chuan Wang
IPC分类号： G06F17/50
CPC分类号： H01L23/53223 , H01L23/528 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A design structure including an integrated circuit for reducing the electromigration effect. The IC includes a substrate and a power transistor which has first and second source/drain regions. The IC further includes first, second, and third electrically conductive line segments being (i) directly above the first source/drain region and (ii) electrically coupled to the first source/drain region through first contact regions and second contact regions, respectively. The first and second electrically conductive line segments (i) reside in a first interconnect layer of the integrated circuit and (ii) run in the reference direction. The IC further includes an electrically conductive line being (i) directly above the first source/drain region, (ii) electrically coupled to the first and second electrically conductive line segments through a first via and a second via, respectively, (iii) resides in a second interconnect layer of the integrated circuit, and (iv) runs in the reference direction.
摘要翻译：一种设计结构，包括用于降低电迁移效应的集成电路。 IC包括具有第一和第二源/漏区的衬底和功率晶体管。 IC还包括第一，第二和第三导电线段，其直接在第一源极/漏极区域的上方，以及（ii）分别通过第一接触区域和第二接触区域电耦合到第一源极/漏极区域。第一和第二导电线段（i）驻留在集成电路的第一互连层中，并且（ii）沿参考方向延伸。 IC还包括导电线，其是（i）直接在第一源极/漏极区域上方，（ii）分别通过第一通孔和第二通孔电耦合到第一和第二导电线段，（iii）驻留在集成电路的第二互连层中，以及（iv）在参考方向上延伸。

69. 发明申请

US20100295132A1 PROGRAMMABLE PN ANTI-FUSE 有权
标题翻译：可编程PN防熔丝
公开(公告)号：US20100295132A1
公开(公告)日：2010-11-25
申请号：US12698302
申请日：2010-02-02
申请人： Ping-Chuan Wang , Robert C. Wong , Haining S. Yang
发明人： Ping-Chuan Wang , Robert C. Wong , Haining S. Yang
IPC分类号： H01L27/06 , H01L21/8234 , H01L21/326
CPC分类号： H01L27/0727 , H01L23/5252 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： Structure and method for providing a programmable anti-fuse in a FET structure. A method of forming the programmable anti-fuse includes: providing a p− substrate with an n+ gate stack; implanting an n+ source region and an n+ drain region in the p− substrate; forming a resist mask over the n+ drain region, while leaving the n+ source region exposed; etching the n+ source region to form a recess in the n+ source region; and growing a p+ epitaxial silicon germanium layer in the recess in the n+ source region to form a pn junction that acts as a programmable diode or anti-fuse.
摘要翻译：在FET结构中提供可编程反熔丝的结构和方法。形成可编程反熔丝的方法包括：提供具有n +栅极叠层的p衬底; 在p衬底中注入n +源极区域和n +漏极区域; 在n +漏极区域上形成抗蚀剂掩模，同时使n +源极区域露出; 蚀刻n +源极区域以在n +源极区域中形成凹陷; 以及在n +源极区的凹槽中生长p +外延硅锗层以形成用作可编程二极管或反熔丝的pn结。

70. 发明申请

US20100277210A1 THREE-DIMENSIONAL CHIP-STACK SYNCHRONIZATION 有权
标题翻译：三维芯片堆叠同步
公开(公告)号：US20100277210A1
公开(公告)日：2010-11-04
申请号：US12432801
申请日：2009-04-30
申请人： Ping-Chuan Wang , Anthony R. Bonaccio , Jong-Ru Guo , Louis Lu-Chen Hsu
发明人： Ping-Chuan Wang , Anthony R. Bonaccio , Jong-Ru Guo , Louis Lu-Chen Hsu
IPC分类号： H03L7/06
CPC分类号： H03L7/099 , H03L7/18 , H03L7/22
摘要： a central reference clock is placed in a substantially middle chip of a 3-D chip-stack. The central reference clock is distributed to each child chip of the 3-D chip-stack, so that a plurality of clocks is generated for each individual chip in the 3-D-stack in a synchronous manner. A predetermined number of through-silicon-vias and on-chip wires are employed to form a delay element for each slave clock, ensuring that the clock generated for each child chip is substantially synchronized. Optionally, an on-chip clock trimming circuit is embedded for further precision tuning to eliminate local clock skews.
摘要翻译：中心参考时钟被放置在3-D芯片堆叠的基本上中间的芯片中。中心参考时钟被分配给3-D芯片组的每个子芯片，从而以同步的方式为3-D堆叠中的每个芯片生成多个时钟。采用预定数量的通硅通孔和片上导线来形成每个从时钟的延迟元件，确保为每个子芯片生成的时钟基本上同步。可选地，嵌入式片上时钟微调电路用于进一步精确调谐以消除本地时钟偏移。

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