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61. 发明申请

US20130307076A1 METHOD AND STRUCTURE FOR FORMING FIN RESISTORS 有权
标题翻译：形成电阻率的方法和结构
公开(公告)号：US20130307076A1
公开(公告)日：2013-11-21
申请号：US13472605
申请日：2012-05-16
申请人： Kangguo Cheng , Thomas N. Adam , Ali Khakifirooz , Alexander Reznicek
发明人： Kangguo Cheng , Thomas N. Adam , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L27/12 , H01L21/8234
CPC分类号： H01L21/845 , H01L27/0802 , H01L27/1211 , H01L2924/0002 , H01L2924/00
摘要： A fin resistor and method of fabrication are disclosed. The fin resistor comprises a plurality of fins arranged in a linear pattern with an alternating pattern of epitaxial regions. An anneal diffuses dopants from the epitaxial regions into the fins. Contacts are connected to endpoint epitaxial regions to allow the resistor to be connected to more complex integrated circuits.
摘要翻译：公开了一种鳍式电阻器和制造方法。散热片电阻器包括以具有外延区域的交替图案的线性图案布置的多个散热片。退火将掺杂剂从外延区域扩散到鳍片中。触头连接到端点外延区域，以允许电阻器连接到更复杂的集成电路。

62. 发明授权

US08575698B2 MOSFET with thin semiconductor channel and embedded stressor with enhanced junction isolation 有权
标题翻译：具有薄半导体通道的MOSFET和具有增强的结隔离的嵌入式应力源
公开(公告)号：US08575698B2
公开(公告)日：2013-11-05
申请号：US13283308
申请日：2011-10-27
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L27/12
CPC分类号： H01L29/66636 , H01L29/7848 , H01L29/78654
摘要： A field effect transistor structure that uses thin semiconductor on insulator channel to control the electrostatic integrity of the device. Embedded stressors are epitaxially grown in the source/drain area from a template in the silicon substrate through an opening made in the buried oxide in the source/drain region. In addition, a dielectric layer is formed between the embedded stressor and the semiconductor region under the buried oxide layer, which is located directly beneath the channel to suppress junction capacitance and leakage.
摘要翻译：场效应晶体管结构，其使用薄绝缘体上半导体通道来控制器件的静电完整性。嵌入的应力源在源极/漏极区域中从硅衬底中的模板通过在源极/漏极区域中的掩埋氧化物中形成的开口外延生长。此外，在嵌入式应力器和位于沟道正下方的掩埋氧化物层下面的半导体区域之间形成介电层，以抑制结电容和漏电。

63. 发明申请

US20130285123A1 TRANSISTOR WITH IMPROVED SIGMA-SHAPED EMBEDDED STRESSOR AND METHOD OF FORMATION 失效
标题翻译：具有改进的SIGMA形状嵌入式压力器的晶体管和形成方法
公开(公告)号：US20130285123A1
公开(公告)日：2013-10-31
申请号：US13457980
申请日：2012-04-27
申请人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L29/78 , H01L21/336 , H01L21/20
CPC分类号： H01L21/02609 , H01L21/265 , H01L21/28026 , H01L21/30608 , H01L21/3065 , H01L21/308 , H01L21/3086 , H01L29/165 , H01L29/66431 , H01L29/6653 , H01L29/66575 , H01L29/66636 , H01L29/7848
摘要： A method and structure of an embedded stressor in a semiconductor transistor device having a sigma-shaped channel sidewall and a vertical isolation sidewall. The embedded stressor structure is made by a first etch to form a recess in a substrate having a gate and first and second spacers. The second spacers are removed and a second etch creates a step in the recess on a channel sidewall. An anisotropic etch creates facets in the channel sidewall of the recess. Where the facets meet, a vertex is formed. The depth of the vertex is determined by the second etch depth (step depth). The lateral position of the vertex is determined by the thickness of the first spacers. A semiconductor material having a different lattice spacing than the substrate is formed in the recess to achieve the embedded stressor structure.
摘要翻译：具有西格玛通道侧壁和垂直隔离侧壁的半导体晶体管器件中的嵌入式应力源的方法和结构。嵌入的应力器结构由第一蚀刻制成，以在具有栅极和第一和第二间隔物的衬底中形成凹陷。去除第二间隔物，并且第二蚀刻在通道侧壁上的凹部中形成台阶。各向异性蚀刻在凹槽的通道侧壁中产生刻面。小面相遇时，形成顶点。顶点的深度由第二蚀刻深度（阶梯深度）决定。顶点的横向位置由第一间隔件的厚度决定。在凹部中形成具有与衬底不同的晶格间距的半导体材料，以实现嵌入的应力器结构。

64. 发明授权

US08564040B1 Inversion mode varactor 有权
标题翻译：反转模式变容二极管
公开(公告)号：US08564040B1
公开(公告)日：2013-10-22
申请号：US13570360
申请日：2012-08-09
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L27/108
CPC分类号： H01L29/93 , H01L27/1203 , H01L29/66174
摘要： In one exemplary embodiment of the invention, a method includes: providing an inversion mode varactor having a substrate, a backgate layer overlying the substrate, an insulating layer overlying the backgate layer, a semiconductor layer overlying the insulating layer and at least one metal-oxide semiconductor field effect transistor (MOSFET) device disposed upon the semiconductor layer, where the semiconductor layer includes a source region and a drain region, where the at least one MOSFET device includes a gate stack defining a channel between the source region and the drain region, where the gate stack has a gate dielectric layer overlying the semiconductor layer and a conductive layer overlying the gate dielectric layer; and applying a bias voltage to the backgate layer to form an inversion region in the semiconductor layer at an interface between the semiconductor layer and the insulating layer.
摘要翻译：在本发明的一个示例性实施例中，一种方法包括：提供具有衬底的倒置模式变容二极管，覆盖衬底的背栅层，覆盖在背栅层上的绝缘层，覆盖绝缘层的半导体层和至少一种金属氧化物半导体场效应晶体管（MOSFET）器件，其设置在所述半导体层上，其中所述半导体层包括源极区和漏极区，其中所述至少一个MOSFET器件包括限定所述源极区和所述漏极区之间的沟道的栅极叠层，其中所述栅极堆叠具有覆盖所述半导体层的栅极介电层和覆盖所述栅极介电层的导电层; 以及向所述背栅层施加偏置电压，以在所述半导体层和所述绝缘层之间的界面处在所述半导体层中形成反转区域。

65. 发明申请

US20130249006A1 SELECTIVELY RAISED SOURCE/DRAIN TRANSISTOR 有权
标题翻译：选择性提取源/漏极晶体管
公开(公告)号：US20130249006A1
公开(公告)日：2013-09-26
申请号：US13424787
申请日：2012-03-20
申请人： Ali Khakifirooz , Thomas N. Adam , Kangguo Cheng , Alexander Reznicek
发明人： Ali Khakifirooz , Thomas N. Adam , Kangguo Cheng , Alexander Reznicek
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L27/088 , H01L21/823418 , H01L21/823431 , H01L21/823475 , H01L29/41791 , H01L29/66628 , H01L29/7834
摘要： A lower raised source/drain region is formed on a planar source/drain region of a planar field effect transistor or a surface of a portion of semiconductor fin adjoining a channel region of a fin field effect transistor. At least one contact-level dielectric material layer is formed and planarized, and a contact via hole extending to the lower raised source/drain region is formed in the at least one contact-level dielectric material layer. An upper raised source/drain region is formed on a top surface of the lower raised source/drain region. A metal semiconductor alloy portion and a contact via structure are formed within the contact via hole. Formation of the upper raised source/drain region is limited to a bottom portion of the contact via hole, thereby preventing formation of, and increase of parasitic capacitance by, any additional raised structure in source/drain regions that are not contacted.
摘要翻译：在平面场效应晶体管的平面源极/漏极区域或与鳍状场效应晶体管的沟道区域相邻的半导体鳍片的一部分的表面上形成下部凸起的源极/漏极区域。形成并平坦化至少一个接触层介电材料层，并且在该至少一个接触层电介质材料层中形成延伸到下凸起源/漏区的接触通孔。上凸起的源/漏区形成在下凸起的源/漏区的顶表面上。在接触通孔内形成金属半导体合金部分和接触通孔结构。上部隆起源极/漏极区域的形成被限制在接触通孔的底部，从而通过未被接触的源极/漏极区域中的任何额外的凸起结构来防止寄生电容的形成和增加。

66. 发明授权

US08524592B1 Methods of forming semiconductor devices with self-aligned contacts and low-k spacers and the resulting devices 有权
标题翻译：形成具有自对准触点和低k间隔物的半导体器件的方法以及所得到的器件
公开(公告)号：US08524592B1
公开(公告)日：2013-09-03
申请号：US13584055
申请日：2012-08-13
申请人： Ruilong Xie , Xiuyu Cai, Jr. , Kangguo Cheng , Ali Khakifirooz
发明人： Ruilong Xie , Xiuyu Cai, Jr. , Kangguo Cheng , Ali Khakifirooz
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/78 , H01L21/76897 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： One illustrative method disclosed herein includes removing a portion of a sacrificial sidewall spacer to thereby expose at least a portion of the sidewalls of a sacrificial gate electrode and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode. In this example, the method also includes forming a sacrificial gap fill material above the liner layer, exposing and removing the sacrificial gate electrode to thereby define a gate cavity that is laterally defined by the liner layer, forming a replacement gate structure, removing the sacrificial gap fill material and forming a low-k sidewall spacer adjacent the liner layer. A device is also disclosed that includes a gate cap layer, a layer of silicon nitride or silicon oxynitride positioned on each of two upstanding portions of a gate insulation layer and a low-k sidewall spacer positioned on the layer of silicon nitride or silicon oxynitride.
摘要翻译：本文公开的一种说明性方法包括去除牺牲侧壁间隔物的一部分，从而暴露牺牲栅电极的侧壁的至少一部分，并在牺牲栅电极的暴露的侧壁上形成衬垫层。在该示例中，该方法还包括在衬垫层之上形成牺牲间隙填充材料，暴露和去除牺牲栅极电极，从而限定由衬里层横向限定的栅极腔，形成替代栅极结构，去除牺牲层间隙填充材料并形成邻近衬层的低k侧壁间隔物。还公开了一种器件，其包括栅极覆盖层，位于栅极绝缘层的两个直立部分中的每一个上的氮化硅或氮氧化硅层，以及位于氮化硅或氮氧化硅层上的低k侧壁间隔物。

67. 发明申请

US20130207189A1 INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME 有权
标题翻译：具有降低硅氧烷接触电阻的上升源排水装置的集成电路及其制造方法
公开(公告)号：US20130207189A1
公开(公告)日：2013-08-15
申请号：US13852103
申请日：2013-03-28
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Christian Lavoie
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Christian Lavoie
IPC分类号： H01L29/78
CPC分类号： H01L29/66515 , H01L21/28518 , H01L21/76805 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L23/485 , H01L27/0883 , H01L27/1052 , H01L27/1203 , H01L29/0847 , H01L29/41766 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66636 , H01L29/78 , H01L29/7843 , H01L29/7845 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed.
摘要翻译：结构具有至少一个场效应晶体管，其栅极堆叠设置在与栅极堆叠相邻的凸起的源极漏极结构之间。栅极堆叠和升高的源极漏极结构设置在半导体材料的表面上。该结构还包括覆盖栅极叠层和升高的源极漏极结构的场介电层，以及延伸穿过场电介质层的第一接触金属和第二接触金属。第一接触金属终止在通过第一凸起源极漏极结构的顶表面形成的第一沟槽中，并且第二接触金属终止于通过第二凸起源极漏极结构的顶表面形成的第二沟槽中。每个沟槽具有形成在沟槽的至少一部分的侧壁和底表面上的硅化物。还公开了制造该结构的方法。

68. 发明授权

US08507989B2 Extremely thin semiconductor-on-insulator (ETSOI) FET with a back gate and reduced parasitic capacitance 有权
标题翻译：极薄的绝缘体上半导体（ETSOI）FET，具有背栅极和降低的寄生电容
公开(公告)号：US08507989B2
公开(公告)日：2013-08-13
申请号：US13108282
申请日：2011-05-16
申请人： Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris
发明人： Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris
IPC分类号： H01L27/12 , H01L29/786 , H01L29/66
CPC分类号： H01L27/1203 , H01L21/764 , H01L21/84 , H01L29/42384 , H01L29/4908 , H01L29/78648 , H01L2029/42388
摘要： An extremely thin SOI MOSFET device on an SOI substrate is provided with a back gate layer on a Si substrate superimposed by a thin BOX layer; an extremely thin SOI layer (ETSOI) on top of the thin BOX layer; and an FET device on the ETSOI layer having a gate stack insulated by spacers. The thin BOX is formed under the ETSOI channel, and is provided with a thicker dielectric under source and drain to reduce the source/drain to back gate parasitic capacitance. The thicker dielectric portion is self-aligned with the gate. A void within the thicker dielectric portion is formed under the source/drain region. The back gate is determined by a region of semiconductor damaged by implantation, and the formation of an insulating layer by lateral etch and back filling with dielectric.
摘要翻译：在SOI衬底上的非常薄的SOI MOSFET器件在Si衬底上设置有由薄BOX层叠加的背栅层; 在薄BOX层顶部的非常薄的SOI层（ETSOI）; 并且在ETSOI层上的FET器件具有由间隔物绝缘的栅极堆叠。薄BOX形成在ETSOI通道下面，并在源极和漏极之间提供较厚的电介质，以减少源极/漏极到背栅极寄生电容。较厚的电介质部分与栅极自对准。较厚电介质部分内的空隙形成在源/漏区下。背栅由通过注入损坏的半导体区域确定，并且通过横向蚀刻形成绝缘层并且用电介质反向填充。

69. 发明申请

US20130200459A1 STRAINED CHANNEL FOR DEPLETED CHANNEL SEMICONDUCTOR DEVICES 审中-公开
标题翻译：用于分离通道半导体器件的应变通道
公开(公告)号：US20130200459A1
公开(公告)日：2013-08-08
申请号：US13364850
申请日：2012-02-02
申请人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Davood Shahrjerdi
发明人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Davood Shahrjerdi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/1054 , H01L21/02529 , H01L21/02532 , H01L21/306 , H01L21/31144 , H01L21/324 , H01L29/66545 , H01L29/66553 , H01L29/66772 , H01L29/66795 , H01L29/66803 , H01L29/6681 , H01L29/785 , H01L29/78687
摘要： A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device.
摘要翻译：一种平面半导体器件，包括绝缘体上半导体（SOI）衬底，具有由多层应变通道分离的厚度小于10nm的源极和漏极部分。SOI层的多层应变通道包括第一层其具有存在于SOI衬底的掩埋电介质层上的第一晶格尺寸，以及与多层应变通道部分的第一层直接接触的第二晶格尺寸的第二层。功能栅极结构存在于SOI衬底的多层应变通道部分上。具有多层通道的半导体器件也可以是finFET半导体器件。

70. 发明申请

US20130161694A1 THIN HETEREOSTRUCTURE CHANNEL DEVICE 有权
标题翻译：薄型结构通道设备
公开(公告)号：US20130161694A1
公开(公告)日：2013-06-27
申请号：US13607875
申请日：2012-09-10
申请人： Thomas N. Adam , Kangguo Cheng , Hong He , Ali Khakifirooz , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Hong He , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L21/8238 , H01L29/78 , H01L27/12
CPC分类号： H01L21/02057 , H01L21/02532 , H01L21/0262 , H01L21/3065 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/1211 , H01L29/1054
摘要： A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure.
摘要翻译：一种制造半导体器件的方法，其包括提供在电介质层顶部具有至少第一半导体层的衬底，其中所述第一半导体层具有小于10nm的第一厚度。在小于675℃的温度下用卤化物基气体蚀刻第一半导体层至小于第一厚度的第二厚度。在第一半导体层的蚀刻表面上外延形成第二半导体层。栅极结构直接形成在第二半导体层上。源极区域和漏极区域形成在栅极结构的相对侧上。

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