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61. 发明授权

US06453422B1 Reference voltage distribution for multiload i/o systems 有权
标题翻译：多负载i / o系统的参考电压分布
公开(公告)号：US06453422B1
公开(公告)日：2002-09-17
申请号：US09470686
申请日：1999-12-23
申请人： Sanjay Dabral , Stephen R. Mooney , T. Zale Schoenborn , Sam E. Calvin , Tim Frodsham
发明人： Sanjay Dabral , Stephen R. Mooney , T. Zale Schoenborn , Sam E. Calvin , Tim Frodsham
IPC分类号： G06F126
CPC分类号： H04L12/40032 , H04L12/4013
摘要： According to an embodiment of the invention a circuit that is to be coupled to a reference voltage line. The circuit includes a noise coupling circuit that is to couple noise from the circuit to a reference voltage line based upon whether a driver is driving a data line.
摘要翻译：根据本发明的实施例，要耦合到参考电压线的电路。电路包括噪声耦合电路，其基于驱动器是否驱动数据线，将来自电路的噪声耦合到参考电压线。

62. 发明授权

US09791905B2 Rate scalable IO interface with zero stand-by power and fast start-up 有权
公开(公告)号：US09791905B2
公开(公告)日：2017-10-17
申请号：US13995596
申请日：2011-10-28
申请人： Stephen R. Mooney , Howard L. Heck , James E. Jaussi , Bryan K. Casper
发明人： Stephen R. Mooney , Howard L. Heck , James E. Jaussi , Bryan K. Casper
IPC分类号： G06F1/00 , G06F1/26 , G06F13/14 , G06F1/32 , G09G5/00 , G09G5/18
CPC分类号： G06F1/26 , G06F1/266 , G06F1/3215 , G06F1/324 , G06F1/3265 , G06F1/3278 , G06F1/3296 , G06F13/14 , G09G5/006 , G09G5/18 , G09G2330/021 , Y02D10/126 , Y02D10/153 , Y02D10/157 , Y02D10/172 , Y02D50/20
摘要： Systems and methods of interconnecting devices may include an input/output (IO) interface having one or more clock circuits, a power supply coupled to the one or more clock circuits, and logic to receive a rate adjustment command at the IO interface. The logic may also be configured to adjust a data rate of the IO interface in response to the rate adjustment command, and to adjust an output voltage of the power supply in response to the rate adjustment command.

63. 发明授权

US09312908B2 Universal IO connector and interface capable of both wired and wireless operation 有权
标题翻译：通用IO连接器和能够进行有线和无线操作的接口
公开(公告)号：US09312908B2
公开(公告)日：2016-04-12
申请号：US13995592
申请日：2011-11-11
申请人： Stephen R. Mooney , Howard L. Heck , James E. Jaussi , Bryan K. Casper , Debabani Choudhury , Frank T. Hady
发明人： Stephen R. Mooney , Howard L. Heck , James E. Jaussi , Bryan K. Casper , Debabani Choudhury , Frank T. Hady
IPC分类号： H04B1/38 , H04B1/40 , G06F13/40
CPC分类号： H04B1/40 , G06F13/4068 , G06F2213/0042
摘要： Systems and methods of interconnecting devices may include a connector assembly having a substrate, a set of input/output (IO) contacts, an antenna structure and transceiver logic. In one example, the transceiver logic may process one or more IO signals associated with the antenna structure and process one or more IO signals associated with the set of IO contacts.
摘要翻译：互连设备的系统和方法可以包括具有基板，一组输入/输出（IO）触点，天线结构和收发器逻辑的连接器组件。在一个示例中，收发器逻辑可以处理与天线结构相关联的一个或多个IO信号并且处理与该组IO触点相关联的一个或多个IO信号。

64. 发明授权

US09106217B2 Width scalable connector for high bandwidth IO interfaces 有权
标题翻译：用于高带宽IO接口的宽度可伸缩连接器
公开(公告)号：US09106217B2
公开(公告)日：2015-08-11
申请号：US13977050
申请日：2011-12-06
申请人： James E. Jaussi , Bruce E. Pederson , Howard L. Heck , Stephen R. Mooney
发明人： James E. Jaussi , Bruce E. Pederson , Howard L. Heck , Stephen R. Mooney
IPC分类号： H03K19/0175 , H03K19/00 , H01R13/66 , H01R24/60 , H01R25/00 , H01R12/72
CPC分类号： H03K19/0008 , H01R12/722 , H01R12/727 , H01R13/6658 , H01R24/60 , H01R25/006 , H03K19/0175
摘要： Disclosed is a scalable input/output interface that has multiple bays and includes a housing surrounding a plurality of pairs of substrates. A first substrate of the pair of substrates may have a first contact surface and a second substrate of the pair of substrates may have a second contact surface that opposes the first contact surface, wherein each substrate has a connection edge. At least one integrated buffer can be coupled to either the first side or the second side of each substrate. A plurality of rows of contacts can be coupled to the opposing surfaces of each substrate of the pair of substrates, wherein each row of contacts can be stacked substantially parallel to the connection edge. Each connection edge can also be coupled to a separate integrated buffer.
摘要翻译：公开了具有多个托架并且包括围绕多对基板的壳体的可伸缩输入/输出接口。一对基板中的第一基板可以具有第一接触表面，并且该对基板的第二基板可以具有与第一接触表面相对的第二接触表面，其中每个基板具有连接边缘。至少一个集成缓冲器可以耦合到每个衬底的第一侧或第二侧。可以将多排触点耦合到一对基板的每个基板的相对表面，其中每排触点可以基本上平行于连接边缘堆叠。每个连接边缘也可以耦合到单独的集成缓冲器。

65. 发明申请

US20140357128A1 RATE SCALABLE CONNECTOR FOR HIGH BANDWIDTH CONSUMER APPLICATIONS 有权
标题翻译：用于高带宽消费者应用的速率可调连接器
公开(公告)号：US20140357128A1
公开(公告)日：2014-12-04
申请号：US13997096
申请日：2011-12-14
申请人： James E. Jaussi , Stephen R. Mooney , Howard L. Heck , Bruce E. Pederson , Bryan K. Casper
发明人： James E. Jaussi , Stephen R. Mooney , Howard L. Heck , Bruce E. Pederson , Bryan K. Casper
IPC分类号： H01R13/66 , H01R24/62
CPC分类号： H01R24/64 , H01R12/721 , H01R13/66 , H01R13/6658 , H01R24/28 , H01R24/62 , H01R2107/00
摘要： Methods and systems may include an input/output (IO) interface that has an integrated buffer, a housing and a substrate disposed within the housing. The substrate may include a first side, a second side and a connection edge. The integrated buffer can be coupled to at least one of the first side and the second side of the substrate. A plurality of rows of contacts may be coupled to the first side of the substrate. Each row of contacts can be stacked substantially parallel to the connection edge. The substrate may have power outputs coupled thereto and the integrated buffer can include a voltage regulator that has a supply output coupled to the power outputs.
摘要翻译：方法和系统可以包括具有集成缓冲器的输入/输出（IO）接口，壳体和设置在壳体内的基板。衬底可以包括第一侧，第二侧和连接边缘。集成缓冲器可以耦合到衬底的第一侧和第二侧中的至少一个。多个触点列可以耦合到衬底的第一侧。每排触点可以基本上平行于连接边缘堆叠。衬底可以具有耦合到其上的功率输出，并且集成缓冲器可以包括具有耦合到功率输出的电源输出的电压调节器。

66. 发明申请

US20140197696A1 INTERCHANGEABLE POWER AND SIGNAL CONTACTS FOR IO CONNECTORS 审中-公开
标题翻译： IO连接器的可互换电源和信号触点
公开(公告)号：US20140197696A1
公开(公告)日：2014-07-17
申请号：US13995594
申请日：2011-10-17
申请人： Stephen R. Mooney , Howard L. Heck , James E. Jaussi , Frank T. Hady , Bryan K. Casper
发明人： Stephen R. Mooney , Howard L. Heck , James E. Jaussi , Frank T. Hady , Bryan K. Casper
IPC分类号： H01R13/66 , H01H9/54
CPC分类号： G06F13/385 , G06F1/266 , H01H9/54 , H01R13/6658 , Y10T307/74
摘要： Systems and methods of interconnecting devices may include an input/output (IO) connector assembly having a voltage regulator, one or more signaling circuits, a first set of contacts, a second set of contacts connected to the one or more signaling circuits, and logic to receive a configuration command. The logic may also connect the first set of contacts to the voltage regulator if the configuration command corresponds to a first protocol. If the configuration command corresponds to a second protocol, on the other hand, the logic can connect the first set of contacts to the one or more signaling circuits.
摘要翻译：互连设备的系统和方法可以包括具有电压调节器，一个或多个信令电路，第一组触点，连接到一个或多个信号电路的第二组触点和逻辑电路的输入/输出（IO）连接器组件接收配置命令。如果配置命令对应于第一协议，逻辑还可以将第一组触点连接到电压调节器。如果配置命令对应于第二协议，另一方面，逻辑可以将第一组联系人连接到一个或多个信令电路。

67. 发明申请

US20140184270A1 WIDTH SCALABLE CONNECTOR FOR HIGH BANDWIDTH IO INTERFACES 有权
标题翻译：宽带宽接口的宽度可调连接器
公开(公告)号：US20140184270A1
公开(公告)日：2014-07-03
申请号：US13977050
申请日：2011-12-06
申请人： James E. Jaussi , Bruce E. Pederson , Howard L. Heck , Stephen R. Mooney
发明人： James E. Jaussi , Bruce E. Pederson , Howard L. Heck , Stephen R. Mooney
IPC分类号： H03K19/00 , H03K19/0175
CPC分类号： H03K19/0008 , H01R12/722 , H01R12/727 , H01R13/6658 , H01R24/60 , H01R25/006 , H03K19/0175
摘要： Disclosed is a scalable input/output interface that has multiple bays and includes a housing surrounding a plurality of pairs of substrates. A first substrate of the pair of substrates may have a first contact surface and a second substrate of the pair of substrates may have a second contact surface that opposes the first contact surface, wherein each substrate has a connection edge. At least one integrated buffer can be coupled to either the first side or the second side of each substrate. A plurality of rows of contacts can be coupled to the opposing surfaces of each substrate of the pair of substrates, wherein each row of contacts can be stacked substantially parallel to the connection edge. Each connection edge can also be coupled to a separate integrated buffer.
摘要翻译：公开了具有多个托架并且包括围绕多对基板的壳体的可伸缩输入/输出接口。一对基板中的第一基板可以具有第一接触表面，并且该对基板的第二基板可以具有与第一接触表面相对的第二接触表面，其中每个基板具有连接边缘。至少一个集成缓冲器可以耦合到每个衬底的第一侧或第二侧。可以将多排触点耦合到一对基板的每个基板的相对表面，其中每排触点可以基本上平行于连接边缘堆叠。每个连接边缘也可以耦合到单独的集成缓冲器。

68. 发明授权

US06420912B1 Voltage to current converter 有权
标题翻译：电压到电流转换器
公开(公告)号：US06420912B1
公开(公告)日：2002-07-16
申请号：US09735858
申请日：2000-12-13
申请人： Michael Pang-Cheng Hsu , Rajendran Nair , Stephen R. Mooney
发明人： Michael Pang-Cheng Hsu , Rajendran Nair , Stephen R. Mooney
IPC分类号： H02M1100
CPC分类号： H03F3/45219 , H03D13/003 , H03F3/45183 , H03F2203/45318 , H03F2203/45394 , H03F2203/45674 , H03L7/091
摘要： A voltage-to-current circuit utilizes an NMOS-input voltage-to-current (V-I) converter and a PMOS-input V-I converter, with both driving a common gate output stage. Each of the V-I converters includes a transconductance amplifier and a current mirror. The common gate output stage includes two series connected complementary pairs of transistors. One complementary pair drives the output, and the other complementary pair biases the first. The V-I circuit can be utilized as part of a phase detector, which is in turn can be utilized as part of a phase lock loop or a delay lock loop.
摘要翻译：电压 - 电流电路使用NMOS输入电压 - 电流（V-I）转换器和PMOS输入V-I转换器，同时驱动公共栅极输出级。每个V-I转换器包括跨导放大器和电流镜。公共栅极输出级包括两个串联的互补晶体管对。一对互补对驱动输出，另一个互补对偏置第一个。 V-I电路可以用作相位检测器的一部分，相位检测器又可以用作锁相环或延迟锁定环路的一部分。

69. 发明授权

US06351191B1 Differential delay cell with common delay control and power supply 失效
标题翻译：具有通用延迟控制和电源的差分延迟单元
公开(公告)号：US06351191B1
公开(公告)日：2002-02-26
申请号：US09584565
申请日：2000-05-31
申请人： Rajendran Nair , Stephen R. Mooney
发明人： Rajendran Nair , Stephen R. Mooney
IPC分类号： H03B524
CPC分类号： H03B5/24 , H03K3/011 , H03K3/0231 , H03K5/133 , H03K2005/00032 , H03K2005/00208 , H03L7/0995
摘要： A differential delay cell includes load transistors and a current source transistor biased linearly. The delay control input of the differential delay cell is also the power supply input such that when the power supply voltage changes, the delay in the differential delay cell changes. The resistance presented by the load transistors changes as a function of the power supply voltage, as does the current sourced by the variable current source. The combination of changing resistance and changing current as the power supply voltage changes results in a substantially constant output voltage swing. A ring of differential delay cells is included in a voltage controlled oscillator, which is in turn included in a phase lock loop. The phase lock loop has a wide loop bandwidth and the voltage controlled oscillator has a good power supply rejection ratio.
摘要翻译：差分延迟单元包括负载晶体管和线性偏置的电流源晶体管。差分延迟单元的延迟控制输入也是电源输入，使得当电源电压变化时，差分延迟单元中的延迟变化。由负载晶体管提供的电阻随着电源电压的变化而变化，与可变电流源的电流一样。随着电源电压变化，电阻变化和电流变化的组合导致基本恒定的输出电压摆幅。差分延迟单元的环包括在压控振荡器中，其又包括在锁相环中。锁相环具有宽环路带宽，压控振荡器具有良好的电源抑制比。

70. 发明授权

US10089270B2 Interchangeable power and signal contacts for IO connectors 有权
公开(公告)号：US10089270B2
公开(公告)日：2018-10-02
申请号：US13995594
申请日：2011-10-17
申请人： Stephen R. Mooney , Howard L. Heck , James E. Jaussi , Frank T. Hady , Bryan K. Casper
发明人： Stephen R. Mooney , Howard L. Heck , James E. Jaussi , Frank T. Hady , Bryan K. Casper
IPC分类号： H01H35/00 , H01H83/00 , G06F13/38 , G06F1/26 , H01H9/54 , H01R13/66
摘要： Systems and methods of interconnecting devices may include an input/output (IO) connector assembly having a voltage regulator, one or more signaling circuits, a first set of contacts, a second set of contacts connected to the one or more signaling circuits, and logic to receive a configuration command. The logic may also connect the first set of contacts to the voltage regulator if the configuration command corresponds to a first protocol. If the configuration command corresponds to a second protocol, on the other hand, the logic can connect the first set of contacts to the one or more signaling circuits.

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