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61. 发明授权

US06410954B1 Multilayered capacitor structure with alternately connected concentric lines for deep sub-micron CMOS 有权
标题翻译：用于深亚微米CMOS的具有交替连接的同心线的多层电容器结构
公开(公告)号：US06410954B1
公开(公告)日：2002-06-25
申请号：US09546125
申请日：2000-04-10
申请人： Tirdad Sowlati , Vickram Vathulya
发明人： Tirdad Sowlati , Vickram Vathulya
IPC分类号： H01L27108
CPC分类号： H01L28/90 , H01L27/0805
摘要： A capacitor structure having a first and at least a second level of electrically conductive concentric lines of an open-loop configuration. The conductive lines of the at least second level overlie the conductive lines of the first level. A dielectric material is disposed between the first and second levels of conductive lines and between the conductive lines in each of the first and second levels. The conductive lines are electrically connected in an alternating manner to terminals of opposing polarity so that capacitance is generated between adjacent lines in each level and in adjacent levels. The capacitor especially useful in deep sub-micron CMOS.
摘要翻译：一种电容器结构，其具有开环构造的第一和至少第二水平的导电同心线。至少第二级的导线覆盖第一级的导线。电介质材料设置在第一级和第二级的导线之间，并且在第一级和第二级中的每一级之间的导线之间。导线以交替的方式电连接到具有相反极性的端子，使得在每个电平和相邻电平中的相邻线之间产生电容。该电容器特别适用于深亚微米CMOS。

62. 发明授权

US06359516B1 High-frequency amplifier circuit with independent control of quiescent current and bias impedance 有权
标题翻译：具有独立控制静态电流和偏置阻抗的高频放大器电路
公开(公告)号：US06359516B1
公开(公告)日：2002-03-19
申请号：US09621525
申请日：2000-07-21
申请人： Sifen Luo , Tirdad Sowlati
发明人： Sifen Luo , Tirdad Sowlati
IPC分类号： H03F304
CPC分类号： H03F1/302 , H03F1/0261 , H03F3/19
摘要： A high-frequency amplifier circuit includes an amplifying transistor and a bias circuit coupled to the amplifying transistor. The bias circuit includes a first bias subcircuit for controlling a quiescent current in the amplifying transistor and a second bias subcircuit for independently controlling a bias impedance of the amplifying transistor. Using this configuration, it is possible to set the gain and class of operation of the amplifying transistor, while independently controlling the bias impedance of the amplifying transistor to obtain improved linearity and tuning capability as well as increased efficiency.
摘要翻译：高频放大器电路包括放大晶体管和耦合到放大晶体管的偏置电路。偏置电路包括用于控制放大晶体管中的静态电流的第一偏置子电路和用于独立地控制放大晶体管的偏置阻抗的第二偏置子电路。使用该配置，可以设置放大晶体管的增益和工作类别，同时独立地控制放大晶体管的偏置阻抗，以获得改善的线性度和调谐能力以及提高的效率。

63. 发明授权

US06297524B1 Multilayer capacitor structure having an array of concentric ring-shaped plates for deep sub-micron CMOS 有权
标题翻译：具有用于深亚微米CMOS的同心环形板阵列的多层电容器结构
公开(公告)号：US06297524B1
公开(公告)日：2001-10-02
申请号：US09542712
申请日：2000-04-04
申请人： Vickram Vathulya , Tirdad Sowlati
发明人： Vickram Vathulya , Tirdad Sowlati
IPC分类号： H01G430
CPC分类号： H01L28/82 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： A capacitor structure having a first and at least a second conductor level of electrically conductive concentric ring-shaped lines. The conductive lines of the first and at least second levels are arranged in concentric ring-shaped stacks. A dielectric material is disposed between the first and second conductor levels and between the concentric conductive lines in each of the levels. At least one electrically conductive via electrically connects the conductive lines in each stack, thereby forming a concentric array of ring-shaped capacitor plates. The concentric array of capacitor plates are electrically connected in an alternating manner to first and second terminals of opposite polarity so that capacitance is generated between adjacent plates of the array. The capacitor structure is especially useful in deep sub-micron CMOS.
摘要翻译：一种具有导电同心环形线的第一和至少第二导体水平的电容器结构。第一和至少第二级的导线被布置成同心环形的叠层。电介质材料设置在第一和第二导体层之间以及在每一层中的同心导电线之间。至少一个导电通孔电连接每个叠层中的导电线，由此形成环形电容器板的同心阵列。电容器板的同心阵列以交替的方式电连接到具有相反极性的第一和第二端子，使得在阵列的相邻板之间产生电容。电容器结构在深亚微米CMOS中特别有用。

64. 发明授权

US08933757B2 Low phase noise voltage controlled oscillators 有权
标题翻译：低相位噪声电压控制振荡器
公开(公告)号：US08933757B2
公开(公告)日：2015-01-13
申请号：US13610016
申请日：2012-09-11
申请人： Farid Shirinfar , Tirdad Sowlati , Maryam Rofougaran , Ahmadreza Rofougaran
发明人： Farid Shirinfar , Tirdad Sowlati , Maryam Rofougaran , Ahmadreza Rofougaran
IPC分类号： H03B5/12
CPC分类号： H03B1/04 , H03B5/1215 , H03B5/1228 , H03B5/1243 , H03B5/1262 , H03B5/1293 , H03B5/1296 , H03B5/1852 , H03B27/00 , H03B2200/0048 , H03B2200/0052 , H03B2200/0074
摘要： A voltage controlled oscillator (VCO) with low phase noise and a sharp output spectrum is desirable. The present disclosure provides embodiments of LC tank VCOs that generate output signals with less phase noise compared with conventional LC tank VCOs, while at the same time limiting additional cost, size, and/or power. The embodiments of the present disclosure can be used, for example, in wired or wireless communication systems that require low-phase noise oscillator signals for performing up-conversion and/or down-conversion.
摘要翻译：具有低相位噪声和尖锐输出频谱的压控振荡器（VCO）是理想的。本公开提供了与常规LC箱VCO相比产生具有较少相位噪声的输出信号的LC槽VCO的实施例，同时限制了额外的成本，尺寸和/或功率。本公开的实施例可以用于例如需要用于执行上变频和/或下变频的低相位噪声振荡器信号的有线或无线通信系统。

65. 发明授权

US08578222B2 SerDes power throttling as a function of detected error rate 有权
标题翻译： SerDes功率节流作为检测到的错误率的函数
公开(公告)号：US08578222B2
公开(公告)日：2013-11-05
申请号：US13029934
申请日：2011-02-17
申请人： Dexter T Chun , Jack K Wolf , Jungwon Suh , Tirdad Sowlati
发明人： Dexter T Chun , Jack K Wolf , Jungwon Suh , Tirdad Sowlati
IPC分类号： G06F11/00
CPC分类号： H04L12/12 , H04L1/0001 , H04L1/0036 , H04L25/02 , H04W52/0209 , Y02D70/00
摘要： A system involves a first SerDes link from a first integrated circuit (IC) to a second IC and a second link from the second IC to the first IC. Power consumption settings in circuitry of the first link are adjusted to control power consumption such that the bit error rate of the first link is maintained in a range, where the lower bound of the range is substantially greater than zero. Power consumption settings in circuitry for the second link are adjusted to control power consumption such that the bit error rate of the second link is maintained in range, where the lower bound of the range is substantially greater than zero. In one example, circuitry in the second IC detects errors in the first link and reports back via the second link. The first IC uses the reported information to determine a bit error rate for the first link.
摘要翻译：系统涉及从第一集成电路（IC）到第二IC的第一SerDes链路以及从第二IC到第一IC的第二链路。调整第一链路的电路中的功率消耗设置以控制功率消耗，使得第一链路的误码率保持在范围的下限基本上大于零的范围内。调整用于第二链路的电路中的功率消耗设置以控制功率消耗，使得第二链路的误码率保持在范围内，其范围的下限基本上大于零。在一个示例中，第二IC中的电路检测第一链路中的错误并通过第二链路报告。第一个IC使用报告的信息来确定第一个链路的误码率。

66. 发明申请

US20130082744A1 Apparatus to Implement Symmetric Single-Ended Termination in Differential Voltage-Mode Drivers 有权
标题翻译：在差分电压模式驱动器中实现对称单端终止的装置
公开(公告)号：US20130082744A1
公开(公告)日：2013-04-04
申请号：US13248485
申请日：2011-09-29
申请人： Cheng Zhong , Vannam Dang , Miao Li , Fares K. Maarouf , Tirdad Sowlati
发明人： Cheng Zhong , Vannam Dang , Miao Li , Fares K. Maarouf , Tirdad Sowlati
IPC分类号： H03K3/00
CPC分类号： H04L25/0274 , H04L25/0278
摘要： A differential voltage mode driver for implementing symmetric single ended termination includes an output driver circuitry having a predefined termination impedance. The differential voltage mode driver also includes an output driver replica having independently controlled first and second portions. The first and second portions are independently controlled to establish a substantially equal on-resistance of the first and the second portions. The output driver replica controls the predefined termination impedance of the output driver circuitry.
摘要翻译：用于实现对称单端终端的差分电压模式驱动器包括具有预定义的终端阻抗的输出驱动器电路。差分电压模式驱动器还包括具有独立控制的第一和第二部分的输出驱动器副本。独立地控制第一和第二部分以建立第一和第二部分的基本相等的导通电阻。输出驱动器副本控制输出驱动器电路的预定终止阻抗。

67. 发明申请

US20120216084A1 SERDES POWER THROTTLING AS A FUNCTION OF DETECTED ERROR RATE 有权
标题翻译：作为检测到的错误率的功能将功率节制作为电源
公开(公告)号：US20120216084A1
公开(公告)日：2012-08-23
申请号：US13029934
申请日：2011-02-17
申请人： Dexter T. Chun , Jack K. Wolf , Jungwon Suh , Tirdad Sowlati
发明人： Dexter T. Chun , Jack K. Wolf , Jungwon Suh , Tirdad Sowlati
IPC分类号： G06F11/00
CPC分类号： H04L12/12 , H04L1/0001 , H04L1/0036 , H04L25/02 , H04W52/0209 , Y02D70/00
摘要： A system involves a first SerDes link from a first integrated circuit (IC) to a second IC and a second link from the second IC to the first IC. Power consumption settings in circuitry of the first link are adjusted to control power consumption such that the bit error rate of the first link is maintained in a range, where the lower bound of the range is substantially greater than zero. Power consumption settings in circuitry for the second link are adjusted to control power consumption such that the bit error rate of the second link is maintained in range, where the lower bound of the range is substantially greater than zero. In one example, circuitry in the second IC detects errors in the first link and reports back via the second link. The first IC uses the reported information to determine a bit error rate for the first link.
摘要翻译：系统涉及从第一集成电路（IC）到第二IC的第一SerDes链路以及从第二IC到第一IC的第二链路。调整第一链路的电路中的功率消耗设置以控制功率消耗，使得第一链路的误码率保持在范围的下限基本上大于零的范围内。调整用于第二链路的电路中的功率消耗设置以控制功率消耗，使得第二链路的误码率保持在范围内，其范围的下限基本上大于零。在一个示例中，第二IC中的电路检测第一链路中的错误并通过第二链路报告。第一个IC使用报告的信息来确定第一个链路的误码率。

68. 发明申请

US20120153994A1 Methods and Implementation of Low-Power Power-On Control Circuits 有权
标题翻译：低功耗开机控制电路的方法与实现
公开(公告)号：US20120153994A1
公开(公告)日：2012-06-21
申请号：US12971527
申请日：2010-12-17
申请人： Chang Ki Kwon , Craig E. Borden , Steve J. Halter , Tirdad Sowlati
发明人： Chang Ki Kwon , Craig E. Borden , Steve J. Halter , Tirdad Sowlati
IPC分类号： G01R19/155 , G06F17/50
CPC分类号： H03K17/22 , G01R19/2503 , G06F1/26 , G06F1/32
摘要： Methods and implementation of low-power power-on control circuits are disclosed. In a particular embodiment, an apparatus includes a power detector circuit powered by a first voltage supply. At least one voltage level-shifting device is coupled to a second voltage supply and a test input is provided to the power detector circuit. An optional leakage self-control device may reduce unwanted leakage currents associated with the first supply and the second supply.
摘要翻译：公开了低功率上电控制电路的方法和实现。在特定实施例中，一种装置包括由第一电压源供电的功率检测器电路。至少一个电压电平移位装置耦合到第二电压源，并且将测试输入提供给功率检测器电路。可选的泄漏自控装置可以减少与第一电源和第二电源相关联的不想要的泄漏电流。

69. 发明申请

US20120134401A1 SYSTEM AND METHOD FOR CLOSED LOOP POWER CONTROL CALIBRATION 有权
标题翻译：闭环功率控制校准的系统和方法
公开(公告)号：US20120134401A1
公开(公告)日：2012-05-31
申请号：US13311355
申请日：2011-12-05
申请人： Dmitriy Rozenblit , Tirdad Sowlati , Dongsoo Daniel Koh , Rajasekhar Pullela
发明人： Dmitriy Rozenblit , Tirdad Sowlati , Dongsoo Daniel Koh , Rajasekhar Pullela
IPC分类号： H04B17/00
CPC分类号： H03G3/3047 , H03G3/3042 , H04B17/21 , H04B2001/0416 , H04W52/06
摘要： A system for calibrating a closed power control loop includes an adder configured to inject a test signal into an adjustable element, a first peak detector configured to determine an amplitude of the injected test signal, a second peak detector configured to determine an amplitude of a return test signal, a comparator configured to determine the difference between the injected test signal and the return test signal, and a calibration engine configured to adjust the adjustable element so that the return test signal is offset from the injected test signal by a predetermined amount.
摘要翻译：用于校准闭合功率控制回路的系统包括被配置为将测试信号注入到可调元件中的加法器，被配置为确定注入的测试信号的幅度的第一峰值检测器，被配置为确定返回幅度的第二峰值检测器测试信号，比较器，被配置为确定注入的测试信号与返回测试信号之间的差异;以及校准引擎，被配置为调整可调节元件，使得返回测试信号偏离注入的测试信号预定量。

70. 发明授权

US08073410B2 System and method for closed loop power control calibration 有权
标题翻译：闭环功率控制校准的系统和方法
公开(公告)号：US08073410B2
公开(公告)日：2011-12-06
申请号：US11589472
申请日：2006-10-30
申请人： Dmitriy Rozenblit , Tirdad Sowlati , Dongsoo Daniel Koh , Rajasekhar Pullela
发明人： Dmitriy Rozenblit , Tirdad Sowlati , Dongsoo Daniel Koh , Rajasekhar Pullela
IPC分类号： H01Q11/12 , H04B1/04
CPC分类号： H03G3/3047 , H03G3/3042 , H04B17/21 , H04B2001/0416 , H04W52/06
摘要： A system for calibrating a closed power control loop includes an adder configured to inject a test signal into an adjustable element, a first peak detector configured to determine an amplitude of the injected test signal, a second peak detector configured to determine an amplitude of a return test signal, a comparator configured to determine the difference between the injected test signal and the return test signal, and a calibration engine configured to adjust the adjustable element so that the return test signal is offset from the injected test signal by a predetermined amount.
摘要翻译：用于校准闭合功率控制回路的系统包括被配置为将测试信号注入到可调节元件中的加法器，被配置为确定所注入的测试信号的幅度的第一峰值检测器，被配置为确定返回幅度的第二峰值检测器测试信号，比较器，被配置为确定注入的测试信号与返回测试信号之间的差异;以及校准引擎，被配置为调整可调节元件，使得返回测试信号偏离注入的测试信号预定量。

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