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61. 发明授权

US07295486B2 Memory and driving method therefor 有权
标题翻译：记忆和驾驶方法
公开(公告)号：US07295486B2
公开(公告)日：2007-11-13
申请号：US11391990
申请日：2006-03-29
申请人： Chung-Kuang Chen
发明人： Chung-Kuang Chen
IPC分类号： G11C8/00
CPC分类号： G11C16/0491 , G11C17/126
摘要： A memory and a driving method therefor is provided. A j-th bank select MOS transistor is coupled to a j-th bit line and controlled by a bank select line. A j-th BD region is coupled to the j-th bank select MOS transistor. Gate(i, j) of memory cell M (i, j) is coupled to the i-th word line, the first source/drain(i, j) of memory cell M (i, j) is coupled to the j-th BD region, and the second source/drain(i, j) of memory cell M (i, j) is coupled to the first source/drain(i, j+1). In order to compensate the voltage drop resulting from the resistance of the j-th bit line and the j-th BD region, at least one of the voltage applied to the i-th word line and the voltage applied to the j-th bit line is adjusted according to the position of the bank which the memory cell M (i, j) belongs to.
摘要翻译：提供了一种存储器及其驱动方法。第j组选择MOS晶体管被耦合到第j位线并由存储体选择线控制。第j个BD区域耦合到第j个存储体选择MOS晶体管。存储单元M（i，j）的门（i，j）被耦合到第i个字线，存储单元M（i，j）的第一源/漏（i，j）并且存储单元M（i，j）的第二源极/漏极（i，j）耦合到第一源极/漏极（i，j + 1）。为了补偿由第j位线和第j个BD区域的电阻引起的电压降，施加到第i个字线的电压和施加到第j个位线的电压中的至少一个根据存储单元M（i，j）所属的存储体的位置来调整行。

62. 发明申请

US20070223266A1 One-time-programmable (OTP) memory device and method for testing the same 有权
标题翻译：一次性可编程（OTP）存储器件及其测试方法
公开(公告)号：US20070223266A1
公开(公告)日：2007-09-27
申请号：US11388905
申请日：2006-03-24
申请人： Chung-Kuang Chen
发明人： Chung-Kuang Chen
IPC分类号： G11C17/00 , G11C29/00 , G11C7/00
CPC分类号： G11C29/52 , G11C17/14 , G11C2216/26
摘要： An OTP memory device and method for testing the same is disclosed. The memory device includes a number of memory cells and each memory cell has an initial threshold voltage. Each memory cell is programmed to have a first threshold voltage larger than a maximum value of the initial threshold voltages in the test program operation. When the memory device is test pass, the memory device is directly provided for a user program operation without need of an erase operation.
摘要翻译：公开了一种OTP存储器件及其测试方法。存储器件包括多个存储器单元，并且每个存储器单元具有初始阈值电压。每个存储器单元被编程为在测试程序操作中具有大于初始阈值电压的最大值的第一阈值电压。当存储器件被测试通过时，存储器件直接被提供用于用户编程操作而不需要擦除操作。

63. 发明申请

US20070211538A1 Methods and apparatus for a non-volatile memory device with reduced program disturb 有权
标题翻译：减少程序干扰的非易失性存储器件的方法和装置
公开(公告)号：US20070211538A1
公开(公告)日：2007-09-13
申请号：US11370368
申请日：2006-03-08
申请人： Chung-Kuang Chen
发明人： Chung-Kuang Chen
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C5/14 , G11C7/12 , G11C16/0491 , G11C16/24 , G11C16/3427
摘要： A non-volatile memory device includes a polarity of power control circuits interfaced via a single Y multiplexer with an array of memory cells. The multiple power control circuits provide multiple pre-charge paths configured to pre-charge the drain node of a target memory cell in the array, as well as the drain and/or source nodes of unselected memory cells in the array. The multiple pre-charge paths decrease the current through the array cells and also decrease the pre-charge and set up times for the array.
摘要翻译：非易失性存储器件包括经由单个Y复用器与存储器单元阵列接口的功率控制电路的极性。多个功率控制电路提供多个预充电路径，其被配置为对阵列中的目标存储器单元的漏极节点以及阵列中未选择的存储器单元的漏极和/或源节点进行预充电。多个预充电路径减少了通过阵列单元的电流，并且还减少了阵列的预充电和设置时间。

64. 发明申请

US20070024325A1 Sense amplifier with input offset compensation 审中-公开
标题翻译：具有输入偏移补偿的感应放大器
公开(公告)号：US20070024325A1
公开(公告)日：2007-02-01
申请号：US11193453
申请日：2005-08-01
申请人： Chung-Kuang Chen
发明人： Chung-Kuang Chen
IPC分类号： H03F3/45
CPC分类号： G11C7/065 , G11C7/04 , G11C7/08
摘要： A sense amplifier, including a first stage amplifier and a second stage amplifier, for compensating input offset voltage changes due to temperature variation of the sense amplifier. The first stage amplifier receives a data voltage and a reference voltage, and outputs a first data output and a second data output. The first stage amplifier receives an adjusted voltage, and is biased at an internal voltage. The second stage amplifier includes a latch, for level-shifting and amplifying the first and second data output, and is biased at an external voltage. The sense amplifier further includes a bias circuit, for generating the adjusted voltage according to temperature variation of the sense amplifier, to reduce the input offset voltage changes.
摘要翻译：包括第一级放大器和第二级放大器的读出放大器，用于补偿由于读出放大器的温度变化引起的输入偏移电压变化。第一级放大器接收数据电压和参考电压，并输出第一数据输出和第二数据输出。第一级放大器接收经调整的电压，并被偏置在内部电压。第二级放大器包括用于电平移位和放大第一和第二数据输出的锁存器，并被偏置在外部电压。读出放大器还包括偏置电路，用于根据读出放大器的温度变化产生调整的电压，以减少输入失调电压的变化。

65. 发明授权

US09159434B2 Bit line bias circuit with varying voltage drop 有权
标题翻译：位线偏置电路具有变化的电压降
公开(公告)号：US09159434B2
公开(公告)日：2015-10-13
申请号：US13458485
申请日：2012-04-27
申请人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C16/06 , G11C11/34 , G11C16/26 , G11C7/06 , G11C16/24 , G11C7/12
CPC分类号： G11C16/26 , G11C7/06 , G11C7/065 , G11C7/12 , G11C16/24
摘要： A bit line bias circuit of a memory architecture includes a varying voltage drop. In some embodiments, the voltage drop can depend on the threshold voltage of the memory cell selected to be read, or on the sense current flowing through the memory cell selected to be read.
摘要翻译：存储器架构的位线偏置电路包括变化的电压降。在一些实施例中，电压降可以取决于选择要读取的存储器单元的阈值电压，或取决于流经选择读取的存储器单元的检测电流。

66. 发明授权

US08879332B2 Flash memory with read tracking clock and method thereof 有权
标题翻译：具有读追踪时钟的闪存及其方法
公开(公告)号：US08879332B2
公开(公告)日：2014-11-04
申请号：US13370833
申请日：2012-02-10
申请人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C16/06
摘要： The configurations of a flash memory having a read tracking clock and method thereof are provided. The proposed flash memory includes a first and a second storage capacitors, a first current source providing a first current flowing through the first storage capacitor, a second current source providing a second current flowing through the second storage capacitor, and a comparator electrically connected to the first and the second current sources, and sending out a signal indicating a developing time being accomplished when the second current is larger than the first current.
摘要翻译：提供具有读追踪时钟及其方法的闪速存储器的配置。所提出的闪速存储器包括第一和第二存储电容器，提供流过第一存储电容器的第一电流的第一电流源，提供流过第二存储电容器的第二电流的第二电流源，以及电连接到第一和第二电流源，并且当第二电流大于第一电流时发出指示正在完成的显影时间的信号。

67. 发明授权

US08736358B2 Current source with tunable voltage-current coefficient 有权
标题翻译：具有可调电压 - 电流系数的电流源
公开(公告)号：US08736358B2
公开(公告)日：2014-05-27
申请号：US12840943
申请日：2010-07-21
申请人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F1/561
摘要： A current source providing an output current with a fixed current range includes a bias circuit, a resistor, a current mirror, and a controller. The bias circuit provides a first voltage weighted with a first tunable coefficient and a second voltage weighted with a second tunable coefficient. The resistor has a tunable resistance for determining a bias current according to a voltage difference between the first and the second voltages and the tunable resistance. The current mirror generates the output current according to the bias current. The controller adjusts the tunable resistance and one of the first and the second tunable coefficients to achieve a voltage-current coefficient with different values, while the bias current and the output current are kept within a fixed current range.
摘要翻译：提供具有固定电流范围的输出电流的电流源包括偏置电路，电阻器，电流镜和控制器。偏置电路提供用第一可调系数和第二可调系数加权的第二电压加权的第一电压。电阻器具有根据第一和第二电压之间的电压差以及可调谐电阻来确定偏置电流的可调电阻。电流镜根据偏置电流产生输出电流。控制器调节可调谐电阻和第一和第二可调谐系数之一，以实现具有不同值的电压 - 电流系数，而偏置电流和输出电流保持在固定电流范围内。

68. 发明授权

US08537630B2 Memory program discharge circuit of bit lines with multiple discharge paths 有权
标题翻译：具有多个放电路径的位线的存储器程序放电电路
公开(公告)号：US08537630B2
公开(公告)日：2013-09-17
申请号：US13722530
申请日：2012-12-20
申请人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/06 , G11C16/24 , G11C16/26 , Y10T29/49117
摘要： A memory integrated circuit has an array of nonvolatile memory cells, bit lines accessing the array of nonvolatile memory cells, and bit line discharge circuitry. The bit lines have multiple discharge paths for a bit line at a same time, during a program operation.
摘要翻译：存储器集成电路具有非易失性存储单元的阵列，访问非易失性存储单元阵列的位线和位线放电电路。在编程操作期间，位线在同一时间对于位线具有多个放电路径。

69. 发明申请

US20130128670A1 MEMORY ACCESS METHOD AND FLASH MEMORY USING THE SAME 有权
标题翻译：存储器访问方法和使用该存储器的闪存存储器
公开(公告)号：US20130128670A1
公开(公告)日：2013-05-23
申请号：US13298443
申请日：2011-11-17
申请人： Chung-Kuang Chen , Shuo-Nan Hung , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Shuo-Nan Hung , Chun-Hsiung Hung
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/06 , G11C16/32
摘要： A memory access method is applied in a memory controller for accessing an NAND memory array, including a number of respective select switches globally controlled with a string select signal. The memory access method includes the following steps. A stream bias signal and a selected word line signal are respectively provided on a selected stream and on a selected cell of the selected stream, and the rest of memory cells are turned on as pass transistors, in the setup phase. A discharge path is provided to eliminate coupling charge presented on unselected streams, in the setup phase. Then, the string select signal is enabled to have the selected stream connected to a sense unit via a metal bit line and according read the selected cell in a voltage sensing scheme, in a read phase, which does not overlap with the setup phase.
摘要翻译：存储器访问方法应用于存储器控制器中，用于访问NAND存储器阵列，包括通过字符串选择信号全局控制的多个相应的选择开关。存储器访问方法包括以下步骤。在所选择的流和所选择的流的所选择的单元上分别提供流偏置信号和选择的字线信号，并且在设置阶段中，剩余的存储器单元作为传输晶体管被导通。提供放电路径以消除在设置阶段中呈现在未选择的流上的耦合电荷。然后，串选择信号被使能以使所选择的流通过金属位线连接到感测单元，并且在读取阶段以读取阶段读取所选择的单元，其不与设置阶段重叠。

70. 发明申请

US20130107637A1 Memory Program Discharge Circuit of Bit Lines With Multiple Discharge Paths 有权
标题翻译：具有多个放电路径的位线的存储器程序放电电路
公开(公告)号：US20130107637A1
公开(公告)日：2013-05-02
申请号：US13722530
申请日：2012-12-20
申请人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C7/12 , G11C7/06
CPC分类号： G11C7/12 , G11C7/06 , G11C16/24 , G11C16/26 , Y10T29/49117
摘要： A memory integrated circuit has an array of nonvolatile memory cells, bit lines accessing the array of nonvolatile memory cells, and bit line discharge circuitry. The bit lines have multiple discharge paths for a bit line at a same time, during a program operation.
摘要翻译：存储器集成电路具有非易失性存储单元的阵列，访问非易失性存储单元阵列的位线和位线放电电路。在编程操作期间，位线在同一时间对于位线具有多个放电路径。

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