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61. 发明授权

US4595874A Temperature insensitive CMOS precision current source 失效
标题翻译：温度不敏感的CMOS精密电流源
公开(公告)号：US4595874A
公开(公告)日：1986-06-17
申请号：US654411
申请日：1984-09-26
申请人： Jerrell P. Hein , Navdeep S. Sooch
发明人： Jerrell P. Hein , Navdeep S. Sooch
IPC分类号： H03F1/30 , G05F3/24 , G05F3/30 , G05F3/16
CPC分类号： G05F3/30 , Y10S323/907
摘要： A CMOS precision current source which is insensitive to changes in both ambient temperature and processing conditions. In particular, a CMOS circuit exhibits both a temperature dependent voltage (V(T)) and a temperature dependent on-chip resistance (R(T)) where the dependencies of both voltage and resistance are linear functions of temperature of the form y=mx+b. The ratio of the slopes (m.sub.V /m.sub.R) is constructed to be equal to the ratio of the y-intercepts (b.sub.v /b.sub.R), where this ratio is a constant value, denoted s. Therefore, since a constant output current I.sub.o is equal to V(T)/R(T), I.sub.o will be equal to the constant value s. Additionally, a constant reference voltage (V.sub.o) may also be provided with a minimal increase in the circuitry needed to provide the constant current.
摘要翻译： CMOS精密电流源对环境温度和加工条件的变化不敏感。特别地，CMOS电路表现出温度相关电压（V（T））和温度依赖的片上电阻（R（T）），其中电压和电阻两者的依赖性是y = mx + b。斜率（mV / mR）的比率被构造为等于y截距（bv / bR）的比率，其中该比率是常数值，表示为s。因此，由于恒定的输出电流Io等于V（T）/ R（T），所以Io将等于常数值s。另外，恒定参考电压（Vo）也可以提供提供恒定电流所需的电路的最小增加。

62. 发明授权

US06934384B1 Subscriber line interface circuitry 失效
标题翻译：用户线接口电路
公开(公告)号：US06934384B1
公开(公告)日：2005-08-23
申请号：US09502282
申请日：2000-02-10
申请人： Jerrell P. Hein , Navdeep S. Sooch
发明人： Jerrell P. Hein , Navdeep S. Sooch
IPC分类号： H04M3/00 , H04M3/22 , H04M19/00 , H04M1/00 , H04M9/00
CPC分类号： H04M1/738 , H04M1/745 , H04M3/005 , H04M3/04 , H04M3/2272 , H04M19/00 , H04M19/005
摘要： A subscriber line interface circuit apparatus includes a signal processor having sense inputs for sensed tip and ring signals of a subscriber loop. The signal processor generates linefeed driver control signals in response to the sensed signals. The signal processor resides on an integrated circuit die. In another embodiment, a subscriber line interface circuit apparatus includes a signal processor generating subscriber loop control signals in response to sensed tip and ring signals from the subscriber loop. A linefeed driver portion drives the subscriber loop in accordance with the subscriber loop control signals. The linefeed driver portion provides the sensed tip and ring signals. Each of the linefeed driver portion and the signal processor resides on an integrated circuit die. In one packaging implementation, the signal processor and the linefeed driver portion reside on separate integrated circuit die within separate integrated circuit packages. In another packaging implementation, the signal processor and linefeed driver portion reside on separate integrated circuit die within the same integrated circuit package. In yet another packaging implementation, the signal processor and the linefeed driver portion reside on the same integrated circuit die. Regardless of packaging, the common mode and differential mode components are calculated by the signal processor rather than the linefeed driver.
摘要翻译：用户线接口电路设备包括信号处理器，其具有用于感测到的用户环路的尖端和环形信号的感测输入。信号处理器响应于感测到的信号而产生线路馈送驱动器控制信号。信号处理器驻留在集成电路管芯上。在另一个实施例中，用户线接口电路设备包括信号处理器，响应于来自用户环路的感测到的尖端和环形信号而产生用户环路控制信号。换行驱动器部分根据用户回路控制信号来驱动用户回路。换行驱动器部分提供感测到的尖端和振铃信号。每个换行驱动器部分和信号处理器驻留在集成电路管芯上。在一个封装实现中，信号处理器和换行驱动器部分驻留在分开的集成电路封装内的单独的集成电路管芯上。在另一个封装实现中，信号处理器和换行驱动器部分驻留在同一集成电路封装内的分离的集成电路管芯上。在又一个封装实现中，信号处理器和换行驱动器部分驻留在相同的集成电路管芯上。无论包装如何，共模和差分模式组件都由信号处理器而不是换行驱动器计算。

63. 发明授权

US6064326A Analog-to-digital conversion overload detection and suppression 失效
标题翻译：模数转换过载检测和抑制
公开(公告)号：US6064326A
公开(公告)日：2000-05-16
申请号：US50316
申请日：1998-03-30
申请人： Andrew W. Krone , Navdeep S. Sooch
发明人： Andrew W. Krone , Navdeep S. Sooch
IPC分类号： H03M3/02 , H03M3/00 , H03M1/06
CPC分类号： H03M3/362 , H03M3/452
摘要： A technique for detecting and suppressing overload conditions in an analog-to-digital converter which uses a delta-sigma modulator. In order to prevent overloading in modulator, a detection unit is used to detect a preset amplitude level associated with an input signal and when such level is detected, the performance of the modulator is degraded in order to prevent the overload condition from occurring. The degrading is achieved by changing the coefficients of operation of the integrator(s) in the modulator.
摘要翻译：一种用于检测和抑制使用Δ-Σ调制器的模拟 - 数字转换器中的过载状况的技术。为了防止调制器中的过载，使用检测单元来检测与输入信号相关联的预设幅度电平，并且当检测到这种电平时，调制器的性能下降以便防止发生过载状况。降解是通过改变调制器中积分器的操作系数来实现的。

64. 发明授权

US5087914A DC calibration system for a digital-to-analog converter 失效
标题翻译：用于数模转换器的直流校准系统
公开(公告)号：US5087914A
公开(公告)日：1992-02-11
申请号：US571375
申请日：1990-08-22
申请人： Navdeep S. Sooch , Jeffrey W. Scott , Tadashi Tanaka
发明人： Navdeep S. Sooch , Jeffrey W. Scott , Tadashi Tanaka
IPC分类号： H03M1/10 , H03H17/00 , H03H17/02 , H03M3/02
CPC分类号： H03M3/384 , H03M3/50
摘要： A calibration system for a digital-to-analog converter (DAC) includes a digital portion (10) having a interpolation section (14) for receiving the digital input and increasing the sampling frequency thereof for input to a delta-sigma modulator (16). A summing junction (24) is disposed between the interpolation circuit (14) and the delta-sigma modulator (16) to allow an offset voltage to be summed therewith. The offset value is stored in an offset register (26), which is controlled by a calibration control circuit (40). The output of the delta-sigma modulator (16) is input to an analog section (12), which is comprised of an analog filter (22) and an output amplifier (28). The output amplifier (28) is operable to sample the output of the analog filter (22) and feed this back to a gate (38). The gate (38) is activated during a calibration cycle to feed the comparator output back to the calibration control circuit (40). During the calibration cycle, the output is isolated by an isolation amplifier (32 ) and the analog output pad connected to ground by a switch (44) to provide a low impedance output on the analog output. The calibration control circuit (40) is operable to perform a binary search while sampling the output of the analog section (12) with the input to the interpolation circuit (14) forced to a logic low.
摘要翻译：用于数模转换器（DAC）的校准系统包括具有用于接收数字输入并将其采样频率增加以用于输入到Δ-Σ调制器（16）的内插部分（14）的数字部分（10）。在插值电路（14）和Δ-Σ调制器（16）之间设置求和结（24），以允许偏移电压与其相加。偏移值存储在由校准控制电路（40）控制的偏移寄存器（26）中。 Δ-Σ调制器（16）的输出被输入到由模拟滤波器（22）和输出放大器（28）组成的模拟部分（12）。输出放大器（28）可操作以对模拟滤波器（22）的输出进行采样并将其馈送到门（38）。门（38）在校准周期期间被激活，以将比较器输出反馈给校准控制电路（40）。在校准周期期间，输出由隔离放大器（32）隔离，模拟输出焊盘通过开关（44）连接到地，以在模拟输出端提供低阻抗输出。校准控制电路（40）可操作用于对强制为逻辑低的内插电路（14）的输入对模拟部分（12）的输出进行采样，执行二进制搜索。

65. 发明授权

US5248970A Offset calibration of a DAC using a calibrated ADC 失效
标题翻译：使用校准ADC对DAC进行偏移校准
公开(公告)号：US5248970A
公开(公告)日：1993-09-28
申请号：US790574
申请日：1991-11-08
申请人： Navdeep S. Sooch , Michael L. Duffy
发明人： Navdeep S. Sooch , Michael L. Duffy
IPC分类号： H03M1/10 , H03H17/00 , H03H17/02 , H03M3/02
CPC分类号： H03M3/356 , H03M3/50
摘要： A calibrated digital-to-analog converter (DAC) is provided that includes a DAC having an interpolation circuit (40) and delta-sigma converter (44). The output of the delta-sigma converter (44) is input to a one-bit DAC (48) and the output thereof filtered by an analog low pass filter section (50). During a calibration procedure, a calibrated analog-to-digital converter (ADC) (22) is utilized that is operable to receive the analog output of the DAC with a "0" value input thereto through a multiplexer (58). The output of the ADC (22) represents the inherent error in the delta-sigma converter (44) and the analog filter section (50). This is stored in a register (62). In a second step of the operation, the contents of the register (62) are input through the interpolation circuit for interpolation thereof and storage in an offset register/latch circuit (56). The contents of the latch (56) are input to a summing junction (54) which, in normal operation, are summed with the output of the interpolation circuit (40) for input to the delta-sigma converter (44). By disposing the summing junction (54) between the interpolation circuit (40) and the delta-sigma modulator (44), the bit load on the input of the interpolation (40) can be reduced. By utilizing the interpolation circuit (40) in the calibration procedure, the gain thereof can be compensated for in the value stored in the register/latch (56).
摘要翻译：提供了一种校准的数模转换器（DAC），其包括具有内插电路（40）和Δ-Σ转换器（44）的DAC。 Δ-Σ转换器（44）的输出被输入到一位DAC（48），并且其输出由模拟低通滤波器部分（50）滤波。在校准过程中，使用经校准的模数转换器（ADC）（22），其可操作以通过多路复用器（58）向其输入的“0”值接收DAC的模拟输出。 ADC（22）的输出表示Δ-Σ转换器（44）和模拟滤波器部分（50）中的固有误差。这被存储在寄存器（62）中。在该操作的第二步骤中，寄存器（62）的内容通过用于其插值的插值电路输入，并存储在偏移寄存器/锁存电路（56）中。锁存器（56）的内容被输入到求和结点（54），在正常操作中，与用于输入到Δ-Σ转换器（44）的内插电路（40）的输出相加。通过在内插电路（40）和Δ-Σ调制器（44）之间设置加法结（54），可以减少内插（40）的输入上的位负载。通过在校准过程中利用内插电路（40），可以以存储在寄存器/锁存器（56）中的值来补偿其增益。

66. 发明授权

US5196850A Fourth order digital delta-sigma modulator 失效
标题翻译：四阶数字delta-sigma调制器
公开(公告)号：US5196850A
公开(公告)日：1993-03-23
申请号：US791977
申请日：1991-11-13
申请人： Michael L. Duffy , Navdeep S. Sooch
发明人： Michael L. Duffy , Navdeep S. Sooch
IPC分类号： H03M3/02 , H03M7/32
CPC分类号： H03M7/3015 , H03M7/3011 , H03M7/3028 , H03M7/3037
摘要： A delta-sigma modulator for a digital-to-analog converter includes a single adder (60) that has one input thereof multiplexed by multiplexer (62). Four shift registers (64), (66), (68) and (70) are connected in a serial fashion such that the data output by the adder (60) is input to the shift register (64) and the other input of adder (60) is connected to the output of register (70). In operation, the multiplexer (62) first selects the input data for input to the one input of adder (60) and selects the output of register (70) for the other input. This represents the first stage of integration wherein the accumulated value from a previous cycle is added to the present data. The output of the first stage of integration will be cycled through the registers for each overall cycle of the delta-sigma modulator. In the second stage of integration on the next clock cycle of the 4.times. clock, the multiplexer (62) selects the output of the register (68) for adding to the output of the register (70). This represents the operation of the second stage of integration. The output of register (64) represents the output of each stage of integration after the accumulation step, which is then input to one of four shift left registers (82)-(88), which performs a gain scaling function. An overflow condition is also accommodated with an exclusive-OR gate (78).
摘要翻译：用于数模转换器的Δ-Σ调制器包括具有通过多路复用器（62）复用的一个输入的单个加法器（60）。四个移位寄存器（64），（66），（68）和（70）以串行方式连接，使得加法器（60）输出的数据被输入到移位寄存器（64），另一个输入加法器（60）连接到寄存器（70）的输出端。在操作中，多路复用器（62）首先选择用于输入到加法器（60）的一个输入的输入数据，并选择另一个输入的寄存器（70）的输出。这表示集成的第一阶段，其中来自前一周期的累积值被添加到当前数据。对于Δ-Σ调制器的每个整个周期，第一级积分的输出将循环通过寄存器。在4倍时钟的下一个时钟周期的第二级积分中，多路复用器（62）选择寄存器（68）的输出以加到寄存器（70）的输出端。这代表了第二阶段整合的运作。寄存器（64）的输出表示在积累步骤之后的每个积分级的输出，然后输入到执行增益缩放功能的四个移位左寄存器（82） - （88）中的一个。溢出条件也适用于异或门（78）。

67. 发明授权

US5079550A Combining continuous time and discrete time signal processing in a delta-sigma modulator 失效
标题翻译：在Δ-Σ调制器中组合连续时间和离散时间信号处理
公开(公告)号：US5079550A
公开(公告)日：1992-01-07
申请号：US428396
申请日：1989-10-27
申请人： Navdeep S. Sooch , Donald A. Kerth , Bruce P. Del Signore , Eric J. Swanson
发明人： Navdeep S. Sooch , Donald A. Kerth , Bruce P. Del Signore , Eric J. Swanson
IPC分类号： H03M3/02
CPC分类号： H03M3/496 , H03M3/43 , H03M3/438
摘要： An oversampling analog-to-digital modulator includes an analog loop filter which has a first integrator stage which operates as a continuous time integrator. the second, third, and fourth integrator stages are discrete time or sampling integrators. The continuous time first integrator provides the required thermal noise characteristics of the loop filter while the discrete time integrator stages provide loop stability and transfer characteristics which are advantageous to the overall operation of the analog-to-digital modulator.
摘要翻译：过采样模数转换器包括具有作为连续时间积分器工作的第一积分器级的模拟环路滤波器。第二，第三和第四积分器级是离散时间或采样积分器。连续时间第一积分器提供环路滤波器所需的热噪声特性，而离散时间积分器级提供有利于模数转换器的整体运行的环路稳定性和传输特性。

68. 发明授权

US4851841A Gain scaling of oversampled analog-to-digital converters 失效
标题翻译：过采样模数转换器的增益缩放
公开(公告)号：US4851841A
公开(公告)日：1989-07-25
申请号：US104439
申请日：1987-10-02
申请人： Navdeep S. Sooch
发明人： Navdeep S. Sooch
IPC分类号： H03M3/02
CPC分类号： H03M3/488 , H03M3/43
摘要： Method of operation of an A/D converter having an oversampling front end quantizer coupled to a digital decimation filter. The method includes setting an effective feedback reference voltage to a value that is a predetermined factor greater than a specified maximum analog input voltage; and increasing the gain of the digital decimation filter by an amount substantially equal to the predetermined factor. In accordance with another aspect of the invention, an A/D converter includes a delta-sigma modulator wherein the full-scale analog input voltage is set below a maximum effective feedback reference voltage by a predetermined factor; and, the impulse-response coefficients of a digital decimation filter coupled to the output of the delta-sigma modulator are selected to provide full-scale digital output when a full-scale analog input voltage is applied to the analog voltage input.
摘要翻译：具有耦合到数字抽取滤波器的过采样前端量化器的A / D转换器的操作方法。该方法包括将有效反馈参考电压设置为大于指定的最大模拟输入电压的预定因子的值; 并且将数字抽取滤波器的增益增加基本上等于预定因子的量。根据本发明的另一方面，A / D转换器包括Δ-Σ调制器，其中满量程模拟输入电压被设置在最大有效反馈参考电压以下预定因子; 并且当将满量程模拟输入电压施加到模拟电压输入时，选择耦合到Δ-Σ调制器的输出的数字抽取滤波器的脉冲响应系数以提供满量程数字输出。

69. 发明授权

US4746899A Method for reducing effects of electrical noise in an analog-to-digital converter 失效
标题翻译：降低模数转换器电噪声影响的方法
公开(公告)号：US4746899A
公开(公告)日：1988-05-24
申请号：US916160
申请日：1986-10-07
申请人： Eric J. Swanson , Navdeep S. Sooch , David J. Knapp
发明人： Eric J. Swanson , Navdeep S. Sooch , David J. Knapp
IPC分类号： H03M1/08 , H03M3/02
CPC分类号： H03M3/324 , H03M3/458
摘要： Method for reducing deleterious effects of electrical noise in an analog-to-digital converter wherein both the analog and digital circuitry of the A/D converter are embodied in the same integrated circuit. The method includes sampling an analog input voltage with a first clock signal, generating a second clock signal that is delayed with respect to the first clock signal, and using the second clock signal as a clock for the digital circuitry. In accordance with another aspect of the invention, the method for reducing effects of noise in an A/D converter wherein such noise is generated by a digital decimation filter includes synchronously pipelining the arithmetic operations of the digital decimation filter.
摘要翻译：用于减少模数转换器中电噪声的有害影响的方法，其中A / D转换器的模拟和数字电路都体现在相同的集成电路中。该方法包括用第一时钟信号对模拟输入电压进行采样，产生相对于第一时钟信号被延迟的第二时钟信号，并且使用第二时钟信号作为数字电路的时钟。根据本发明的另一方面，用于减少A / D转换器中的噪声影响的方法，其中这种噪声由数字抽取滤波器产生，包括同步流水线数字抽取滤波器的算术运算。

70. 发明授权

US07324496B1 Highly integrated radio-frequency apparatus and associated methods 有权
标题翻译：高度集成的射频设备及相关方法
公开(公告)号：US07324496B1
公开(公告)日：2008-01-29
申请号：US10426042
申请日：2003-04-29
申请人： Navdeep S. Sooch , G. Tyson Tuttle
发明人： Navdeep S. Sooch , G. Tyson Tuttle
IPC分类号： H04J3/00
CPC分类号： H04B15/04
摘要： A method of operating a radio-frequency (RF) circuitry and a signal-processing circuitry in a mobile telephone apparatus includes operating the RF circuitry during a first time period. During the first period, the RF circuitry generates a set of data from an RF signal received by the mobile telephone apparatus. The method further includes storing the set of data in a storage device. The method also includes operating the signal-processing circuitry during a second time period to process the set of data.
摘要翻译：在移动电话设备中操作射频（RF）电路和信号处理电路的方法包括在第一时间段内操作RF电路。在第一时段期间，RF电路从由移动电话设备接收的RF信号产生一组数据。该方法还包括将该组数据存储在存储设备中。该方法还包括在第二时间段期间操作信号处理电路以处理该组数据。

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